Searched refs:EncodingMap (Results 1 - 13 of 13) sorted by relevance

/art/compiler/dex/quick/x86/
H A Dtarget_x86.cc139 uint64_t flags = X86Mir2Lir::EncodingMap[lir->opcode].flags;
513 if (X86Mir2Lir::EncodingMap[i].opcode != i) {
514 LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name
516 << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode);
533 return X86Mir2Lir::EncodingMap[opcode].flags;
537 return X86Mir2Lir::EncodingMap[opcode].name;
541 return X86Mir2Lir::EncodingMap[opcode].fmt;
H A Dx86_lir.h217 * assembler. Their corresponding EncodingMap positions will be defined in
402 /* Struct used to define the EncodingMap positions for each X86 opcode */
438 extern X86EncodingMap EncodingMap[kX86Last];
H A Dassemble_x86.cc25 const X86EncodingMap X86Mir2Lir::EncodingMap[kX86Last] = { member in class:art::X86Mir2Lir
366 const X86EncodingMap* entry = &X86Mir2Lir::EncodingMap[lir->opcode];
485 ComputeSize(&X86Mir2Lir::EncodingMap[kX86Sub32RI], 0, 0, false) -
1149 EmitRegImm(&X86Mir2Lir::EncodingMap[kX86Sub32RI], reg, offset + 5 /* size of call +0 */);
1282 const X86EncodingMap *entry = &X86Mir2Lir::EncodingMap[lir->opcode];
1392 << "Instruction size mismatch for entry: " << X86Mir2Lir::EncodingMap[lir->opcode].name;
H A Dcodegen_x86.h167 static const X86EncodingMap EncodingMap[kX86Last]; member in class:art::X86Mir2Lir
H A Dutility_x86.cc43 DCHECK_NE((EncodingMap[opcode].flags & IS_BINARY_OP), 0ULL);
/art/compiler/dex/quick/arm/
H A Dtarget_arm.cc125 uint64_t flags = ArmMir2Lir::EncodingMap[lir->opcode].flags;
496 if (ArmMir2Lir::EncodingMap[i].opcode != i) {
497 LOG(FATAL) << "Encoding order for " << ArmMir2Lir::EncodingMap[i].name
499 << static_cast<int>(ArmMir2Lir::EncodingMap[i].opcode);
721 return ArmMir2Lir::EncodingMap[opcode].flags;
725 return ArmMir2Lir::EncodingMap[opcode].name;
729 return ArmMir2Lir::EncodingMap[opcode].fmt;
H A Dutility_arm.cc335 if (EncodingMap[opcode].flags & IS_BINARY_OP) {
337 } else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) {
338 if (EncodingMap[opcode].field_loc[2].kind == kFmtShift) {
343 } else if (EncodingMap[opcode].flags & IS_QUAD_OP) {
413 if (EncodingMap[opcode].flags & IS_QUAD_OP) {
416 DCHECK(EncodingMap[opcode].flags & IS_TERTIARY_OP);
539 if (EncodingMap[alt_opcode].flags & IS_QUAD_OP)
H A Dcodegen_arm.h170 static const ArmEncodingMap EncodingMap[kArmLast]; member in class:art::ArmMir2Lir
H A Dassemble_arm.cc79 const ArmEncodingMap ArmMir2Lir::EncodingMap[kArmLast] = { member in class:art::ArmMir2Lir
1278 const ArmEncodingMap *encoder = &EncodingMap[lir->opcode];
1391 return EncodingMap[lir->opcode].size;
/art/compiler/dex/quick/mips/
H A Dtarget_mips.cc127 uint64_t flags = MipsMir2Lir::EncodingMap[lir->opcode].flags;
548 if (MipsMir2Lir::EncodingMap[i].opcode != i) {
549 LOG(FATAL) << "Encoding order for " << MipsMir2Lir::EncodingMap[i].name
551 << static_cast<int>(MipsMir2Lir::EncodingMap[i].opcode);
562 return MipsMir2Lir::EncodingMap[opcode].flags;
566 return MipsMir2Lir::EncodingMap[opcode].name;
570 return MipsMir2Lir::EncodingMap[opcode].fmt;
H A Dassemble_mips.cc84 const MipsEncodingMap MipsMir2Lir::EncodingMap[kMipsLast] = { member in class:art::MipsMir2Lir
649 const MipsEncodingMap *encoder = &EncodingMap[lir->opcode];
698 const MipsEncodingMap *encoder = &EncodingMap[kMipsNop];
710 return EncodingMap[lir->opcode].size;
H A Dmips_lir.h303 * assembler. Their corresponding EncodingMap positions will be defined in
424 extern MipsEncodingMap EncodingMap[kMipsLast];
H A Dcodegen_mips.h169 static const MipsEncodingMap EncodingMap[kMipsLast]; member in class:art::MipsMir2Lir

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