Searched refs:displacement (Results 1 - 11 of 11) sorted by relevance

/art/compiler/dex/quick/x86/
H A Dutility_x86.cc346 int displacement, int r_dest, int r_dest_hi, OpSize size,
371 DCHECK_EQ((displacement & 0x3), 0);
380 DCHECK_EQ((displacement & 0x3), 0);
384 DCHECK_EQ((displacement & 0x1), 0);
388 DCHECK_EQ((displacement & 0x1), 0);
402 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
406 displacement + HIWORD_OFFSET);
407 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
409 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET);
411 displacement
345 LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_dest, int r_dest_hi, OpSize size, int s_reg) argument
451 LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) argument
457 LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, int s_reg) argument
463 StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg) argument
550 StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) argument
557 StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) argument
[all...]
H A Dcodegen_x86.h33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
34 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
H A Dassemble_x86.cc334 static size_t ComputeSize(const X86EncodingMap* entry, int base, int displacement, bool has_sib) { argument
354 if (displacement != 0 || base == rBP) {
355 // BP requires an explicit displacement, even when it's 0.
359 size += IS_SIMM8(displacement) ? 1 : 4;
395 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit
411 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit
456 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit
469 return ComputeSize(entry, 0, 0x12345678, false); // displacement size is always 32bit
484 return 5 /* call opcode + 4 byte displacement */ + 1 /* pop reg */ +
/art/compiler/dex/quick/mips/
H A Dutility_mips.cc434 LIR* MipsMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest, argument
437 * Load value from base + displacement. Optionally perform null check
448 bool short_form = IS_SIMM16(displacement);
466 short_form = IS_SIMM16_2WORD(displacement);
467 DCHECK_EQ((displacement & 0x3), 0);
476 DCHECK_EQ((displacement & 0x3), 0);
480 DCHECK_EQ((displacement & 0x1), 0);
484 DCHECK_EQ((displacement & 0x1), 0);
498 load = res = NewLIR3(opcode, r_dest, displacement, rBase);
501 displacement
532 LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) argument
538 LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, int s_reg) argument
543 StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size) argument
625 StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) argument
630 StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) argument
645 StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg) argument
657 LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_dest, int r_dest_hi, OpSize size, int s_reg) argument
[all...]
H A Dcodegen_mips.h33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
34 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
42 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
164 LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
166 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size);
/art/compiler/dex/quick/arm/
H A Dutility_arm.cc767 * Load value from base + displacement. Optionally perform null check
771 LIR* ArmMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest, argument
776 bool thumb2Form = (displacement < 4092 && displacement >= 0);
778 int encoded_disp = displacement;
791 if (displacement <= 1020) {
797 if (displacement <= 1020) {
798 load = NewLIR4(kThumb2LdrdI8, r_dest, r_dest_hi, rBase, displacement >> 2);
800 load = LoadBaseDispBody(rBase, displacement, r_dest,
802 LoadBaseDispBody(rBase, displacement
891 LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) argument
896 LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, int s_reg) argument
902 StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size) argument
1005 StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) argument
1010 StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) argument
1045 StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg) argument
1057 LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_dest, int r_dest_hi, OpSize size, int s_reg) argument
[all...]
H A Dcodegen_arm.h32 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg);
33 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
36 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
40 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size);
41 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi);
43 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
164 LIR* LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size,
166 LIR* StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size);
/art/compiler/jni/quick/
H A Dcalling_convention.h54 // Place iterator at start of arguments. The displacement is applied to
57 void ResetIterator(FrameOffset displacement) { argument
58 displacement_ = displacement;
/art/compiler/dex/quick/
H A Dgen_loadstore.cc77 /* Load a word at base + displacement. Displacement must be word multiple */
78 LIR* Mir2Lir::LoadWordDisp(int rBase, int displacement, int r_dest) { argument
79 return LoadBaseDisp(rBase, displacement, r_dest, kWord,
83 LIR* Mir2Lir::StoreWordDisp(int rBase, int displacement, int r_src) { argument
84 return StoreBaseDisp(rBase, displacement, r_src, kWord);
H A Dmir_to_lir.h507 LIR* LoadWordDisp(int rBase, int displacement, int r_dest);
514 LIR* StoreWordDisp(int rBase, int displacement, int r_src);
531 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0;
532 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi,
535 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
539 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0;
540 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0;
542 virtual LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement,
/art/runtime/
H A Ddisassembler_x86.cc715 int32_t displacement; local
717 displacement = *reinterpret_cast<const int8_t*>(instr);
721 displacement = *reinterpret_cast<const int32_t*>(instr);
724 args << StringPrintf("%+d (%p)", displacement, instr + displacement);

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