/art/compiler/utils/arm/ |
H A D | managed_register_arm_test.cc | 25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); local 26 EXPECT_TRUE(reg.IsNoRegister()); 27 EXPECT_TRUE(!reg.Overlaps(reg)); 31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); local 32 EXPECT_TRUE(!reg.IsNoRegister()); 33 EXPECT_TRUE(reg.IsCoreRegister()); 34 EXPECT_TRUE(!reg.IsSRegister()); 35 EXPECT_TRUE(!reg.IsDRegister()); 36 EXPECT_TRUE(!reg 69 ArmManagedRegister reg = ArmManagedRegister::FromSRegister(S0); local 126 ArmManagedRegister reg = ArmManagedRegister::FromDRegister(D0); local 227 ArmManagedRegister reg = ArmManagedRegister::FromRegisterPair(R0_R1); local 459 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); local [all...] |
H A D | managed_register_arm.h | 38 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg); 256 ArmManagedRegister reg(reg_id); 257 CHECK(reg.IsValidManagedRegister()); 258 return reg; 262 std::ostream& operator<<(std::ostream& os, const ArmManagedRegister& reg); 267 arm::ArmManagedRegister reg(id_); 268 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister()); 269 return reg;
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/art/compiler/utils/x86/ |
H A D | managed_register_x86_test.cc | 25 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); local 26 EXPECT_TRUE(reg.IsNoRegister()); 27 EXPECT_TRUE(!reg.Overlaps(reg)); 31 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local 32 EXPECT_TRUE(!reg.IsNoRegister()); 33 EXPECT_TRUE(reg.IsCpuRegister()); 34 EXPECT_TRUE(!reg.IsXmmRegister()); 35 EXPECT_TRUE(!reg.IsX87Register()); 36 EXPECT_TRUE(!reg 65 X86ManagedRegister reg = X86ManagedRegister::FromXmmRegister(XMM0); local 91 X86ManagedRegister reg = X86ManagedRegister::FromX87Register(ST0); local 117 X86ManagedRegister reg = X86ManagedRegister::FromRegisterPair(EAX_EDX); local 255 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); local [all...] |
H A D | managed_register_x86.cc | 53 RegisterPair reg; // Used to verify that the enum is in sync. member in struct:art::x86::RegisterPairDescriptor 65 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { argument 66 os << X86ManagedRegister::FromRegisterPair(reg); 92 CHECK_EQ(r, kRegisterPairs[r].reg); 101 CHECK_EQ(r, kRegisterPairs[r].reg); 122 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg) { argument 123 reg.Print(os);
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H A D | managed_register_x86.h | 44 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg); 200 X86ManagedRegister reg(reg_id); 201 CHECK(reg.IsValidManagedRegister()); 202 return reg; 206 std::ostream& operator<<(std::ostream& os, const X86ManagedRegister& reg); 211 x86::X86ManagedRegister reg(id_); 212 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister()); 213 return reg;
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H A D | assembler_x86.h | 83 bool IsRegister(Register reg) const { 85 && ((encoding_[0] & 0x07) == reg); // Register codes match. 122 explicit Operand(Register reg) { SetModRM(3, reg); } argument 221 void call(Register reg); 225 void pushl(Register reg); 229 void popl(Register reg); 338 void xchgl(Register reg, const Address& address); 340 void cmpl(Register reg, const Immediate& imm); 342 void cmpl(Register reg, cons 444 LockCmpxchgl(const Address& address, Register reg) argument 616 EmitRegisterOperand(int rm, int reg) argument 622 EmitXmmRegisterOperand(int rm, XmmRegister reg) argument [all...] |
H A D | assembler_x86.cc | 38 std::ostream& operator<<(std::ostream& os, const XmmRegister& reg) { argument 39 return os << "XMM" << static_cast<int>(reg); 42 std::ostream& operator<<(std::ostream& os, const X87Register& reg) { argument 43 return os << "ST" << static_cast<int>(reg); 46 void X86Assembler::call(Register reg) { argument 49 EmitRegisterOperand(2, reg); 68 void X86Assembler::pushl(Register reg) { argument 70 EmitUint8(0x50 + reg); 93 void X86Assembler::popl(Register reg) { argument 95 EmitUint8(0x58 + reg); 749 xchgl(Register reg, const Address& address) argument 756 cmpl(Register reg, const Immediate& imm) argument 769 cmpl(Register reg, const Address& address) argument 783 addl(Register reg, const Address& address) argument 790 cmpl(const Address& address, Register reg) argument 810 testl(Register reg, const Immediate& immediate) argument 868 addl(Register reg, const Immediate& imm) argument 874 addl(const Address& address, Register reg) argument 887 adcl(Register reg, const Immediate& imm) argument 914 subl(Register reg, const Immediate& imm) argument 920 subl(Register reg, const Address& address) argument 933 idivl(Register reg) argument 948 imull(Register reg, const Immediate& imm) argument 956 imull(Register reg, const Address& address) argument 964 imull(Register reg) argument 978 mull(Register reg) argument 999 sbbl(Register reg, const Immediate& imm) argument 1012 incl(Register reg) argument 1025 decl(Register reg) argument 1038 shll(Register reg, const Immediate& imm) argument 1048 shrl(Register reg, const Immediate& imm) argument 1058 sarl(Register reg, const Immediate& imm) argument 1076 negl(Register reg) argument 1083 notl(Register reg) argument 1163 jmp(Register reg) argument 1203 cmpxchgl(const Address& address, Register reg) argument 1224 AddImmediate(Register reg, const Immediate& imm) argument 1275 DoubleAbs(XmmRegister reg) argument 1377 EmitGenericShift(int reg_or_opcode, Register reg, const Immediate& imm) argument 1593 X86ManagedRegister reg = mreg.AsX86(); local 1604 X86ManagedRegister reg = mreg.AsX86(); local [all...] |
/art/runtime/entrypoints/portable/ |
H A D | portable_thread_entrypoints.cc | 45 for (size_t reg = 0; reg < num_regs; ++reg) { 46 if (TestBitmap(reg, reg_bitmap)) { 47 new_frame->SetVRegReference(reg, cur_frame->GetVRegReference(reg)); 49 new_frame->SetVReg(reg, cur_frame->GetVReg(reg)); 68 static bool TestBitmap(int reg, const uint8_t* reg_vector) { argument 69 return ((reg_vector[reg / [all...] |
/art/runtime/arch/arm/ |
H A D | context_arm.h | 48 virtual uintptr_t GetGPR(uint32_t reg) { argument 49 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); 50 return *gprs_[reg]; 53 virtual void SetGPR(uint32_t reg, uintptr_t value);
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H A D | context_arm.cc | 72 void ArmContext::SetGPR(uint32_t reg, uintptr_t value) { argument 73 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); 74 DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. 75 DCHECK(gprs_[reg] != NULL); 76 *gprs_[reg] = value;
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/art/runtime/arch/mips/ |
H A D | context_mips.h | 46 virtual uintptr_t GetGPR(uint32_t reg) { argument 47 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); 48 return *gprs_[reg]; 51 virtual void SetGPR(uint32_t reg, uintptr_t value);
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H A D | context_mips.cc | 71 void MipsContext::SetGPR(uint32_t reg, uintptr_t value) { argument 72 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); 73 CHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. 74 CHECK(gprs_[reg] != NULL); 75 *gprs_[reg] = value;
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/art/runtime/arch/x86/ |
H A D | context_x86.h | 46 virtual uintptr_t GetGPR(uint32_t reg) { argument 48 DCHECK_LT(reg, kNumberOfCpuRegisters); 49 return *gprs_[reg]; 52 virtual void SetGPR(uint32_t reg, uintptr_t value);
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H A D | context_x86.cc | 64 void X86Context::SetGPR(uint32_t reg, uintptr_t value) { argument 65 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); 66 CHECK_NE(gprs_[reg], &gZero); 67 CHECK(gprs_[reg] != NULL); 68 *gprs_[reg] = value;
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H A D | asm_support_x86.S | 79 MACRO1(PUSH, reg) 80 pushl REG_VAR(reg, 0) 82 .cfi_rel_offset REG_VAR(reg, 0), 0 85 MACRO1(POP, reg) 86 popl REG_VAR(reg,0) 88 .cfi_restore REG_VAR(reg,0)
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/art/compiler/dex/quick/ |
H A D | ralloc_util.cc | 51 regs[i].reg = reg_nums[i]; 66 p[i].reg, p[i].is_temp, p[i].in_use, p[i].pair, p[i].partner, 138 void Mir2Lir::RecordCorePromotion(int reg, int s_reg) { argument 141 GetRegInfo(reg)->in_use = true; 142 core_spill_mask_ |= (1 << reg); 143 // Include reg for later sort 144 core_vmap_table_.push_back(reg << VREG_NUM_WIDTH | (v_reg & ((1 << VREG_NUM_WIDTH) - 1))); 147 promotion_map_[p_map_idx].core_reg = reg; 156 res = core_regs[i].reg; 164 void Mir2Lir::RecordFpPromotion(int reg, in argument 414 FreeTemp(int reg) argument 440 IsLive(int reg) argument 458 IsTemp(int reg) argument 463 IsPromoted(int reg) argument 468 IsDirty(int reg) argument 478 LockTemp(int reg) argument 502 ResetDef(int reg) argument 633 RegClassMatches(int reg_class, int reg) argument 643 MarkLive(int reg, int s_reg) argument 660 MarkTemp(int reg) argument 665 UnmarkTemp(int reg) argument 700 MarkInUse(int reg) argument 1021 int reg = AllocPreservedFPReg(FpRegs[i].s_reg, local 1035 int reg = AllocPreservedCoreReg(core_regs[i].s_reg); local [all...] |
/art/runtime/arch/ |
H A D | context.h | 50 virtual uintptr_t GetGPR(uint32_t reg) = 0; 53 virtual void SetGPR(uint32_t reg, uintptr_t value) = 0;
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/art/compiler/utils/mips/ |
H A D | managed_register_mips.h | 44 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg); 210 MipsManagedRegister reg(reg_id); 211 CHECK(reg.IsValidManagedRegister()); 212 return reg; 216 std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg); 221 mips::MipsManagedRegister reg(id_); 222 CHECK(reg.IsNoRegister() || reg.IsValidManagedRegister()); 223 return reg;
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H A D | managed_register_mips.cc | 103 std::ostream& operator<<(std::ostream& os, const MipsManagedRegister& reg) { argument 104 reg.Print(os); 108 std::ostream& operator<<(std::ostream& os, const RegisterPair& reg) { argument 109 os << MipsManagedRegister::FromRegisterPair(reg);
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/art/compiler/dex/quick/x86/ |
H A D | target_x86.cc | 69 int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { argument 71 switch (reg) { 98 // Return mask to strip off fp reg flags and bias. 111 uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) { argument 116 reg_id = reg & 0xf; 120 shift = X86_FPREG(reg) ? kX86FPReg0 : 0; 309 void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) { argument 320 (info1->partner == info2->reg) && 321 (info2->partner == info1->reg)); 333 StoreBaseDispWide(rX86_SP, VRegOffset(v_reg), info1->reg, info 337 FlushReg(int reg) argument 347 IsFpReg(int reg) argument 378 GetRegInfo(int reg) argument [all...] |
H A D | codegen_x86.h | 49 bool IsFpReg(int reg); 54 int TargetReg(SpecialTargetRegister reg); 55 RegisterInfo* GetRegInfo(int reg); 63 uint64_t GetRegMaskCommon(int reg); 66 void FlushReg(int reg); 71 void MarkPreservedSingle(int v_reg, int reg); 141 LIR* OpCmpImmBranch(ConditionCode cond, int reg, int check_value, LIR* target); 143 LIR* OpDecAndBranch(ConditionCode c_code, int reg, LIR* target); 147 LIR* OpPcRelLoad(int reg, LIR* target); 175 void EmitOpReg(const X86EncodingMap* entry, uint8_t reg); [all...] |
/art/compiler/dex/quick/mips/ |
H A D | target_mips.cc | 60 int MipsMir2Lir::TargetReg(SpecialTargetRegister reg) { argument 62 switch (reg) { 89 // Return mask to strip off fp reg flags and bias. 102 uint64_t MipsMir2Lir::GetRegMaskCommon(int reg) { argument 108 reg_id = reg & 0x1f; 110 seed = MIPS_DOUBLEREG(reg) ? 3 : 1; 112 shift = MIPS_FPREG(reg) ? kMipsFPReg0 : 0; 308 void MipsMir2Lir::MarkPreservedSingle(int s_reg, int reg) { argument 316 (info1->partner == info2->reg) && 317 (info2->partner == info1->reg)); 333 FlushReg(int reg) argument 343 IsFpReg(int reg) argument 402 GetRegInfo(int reg) argument [all...] |
/art/compiler/dex/quick/arm/ |
H A D | target_arm.cc | 58 int ArmMir2Lir::TargetReg(SpecialTargetRegister reg) { argument 60 switch (reg) { 88 // Return mask to strip off fp reg flags and bias. 101 uint64_t ArmMir2Lir::GetRegMaskCommon(int reg) { argument 107 reg_id = reg & 0x1f; 109 seed = ARM_DOUBLEREG(reg) ? 3 : 1; 111 shift = ARM_FPREG(reg) ? kArmFPReg0 : 0; 510 * Alloc a pair of core registers, or a double. Low reg in low byte, 511 * high reg in next byte. 597 void ArmMir2Lir::MarkPreservedSingle(int v_reg, int reg) { argument 634 FlushReg(int reg) argument 644 IsFpReg(int reg) argument 694 GetRegInfo(int reg) argument [all...] |
/art/test/StackWalk/ |
H A D | stack_walk_jni.cc | 33 #define REG(mh, reg_bitmap, reg) \ 34 (((reg) < mh.GetCodeItem()->registers_size_) && \ 35 ((*((reg_bitmap) + (reg)/8) >> ((reg) % 8) ) & 0x01))
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/art/runtime/verifier/ |
H A D | register_line.h | 305 bool IsSetLockDepth(size_t reg, size_t depth) { 306 SafeMap<uint32_t, uint32_t>::iterator it = reg_to_lock_depths_.find(reg); 314 void SetRegToLockDepth(size_t reg, size_t depth) { argument 316 DCHECK(!IsSetLockDepth(reg, depth)); 317 SafeMap<uint32_t, uint32_t>::iterator it = reg_to_lock_depths_.find(reg); 319 reg_to_lock_depths_.Put(reg, 1 << depth); 325 void ClearRegToLockDepth(size_t reg, size_t depth) { argument 327 DCHECK(IsSetLockDepth(reg, depth)); 328 SafeMap<uint32_t, uint32_t>::iterator it = reg_to_lock_depths_.find(reg); 338 void ClearAllRegToLockDepths(size_t reg) { argument [all...] |