/external/valgrind/main/VEX/test/ |
H A D | test-i386-shift.h | 37 flags &= ~CC_O; 50 flags &= ~CC_O; 73 flags &= ~CC_O; 86 flags &= ~CC_O; 102 flags &= ~CC_O; 118 flags_in = (o ? CC_O : 0)
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H A D | test-amd64-shift.h | 38 flags &= ~CC_O; 51 flags &= ~CC_O; 64 flags &= ~CC_O; 87 flags &= ~CC_O; 100 flags &= ~CC_O; 116 flags &= ~CC_O; 132 flags_in = (o ? CC_O : 0)
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H A D | test-amd64.c | 61 #define CC_O 0x0800 macro 67 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A) 116 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O) 357 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A) 359 #define CC_MASK (CC_O | CC_C) 860 TEST_BCD(aam, 0x12340547, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)); 861 TEST_BCD(aad, 0x12340407, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)); 1183 rflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
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H A D | test-i386.c | 51 #define CC_O 0x0800 macro 57 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A) 106 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O) 345 #define CC_MASK (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A) 347 #define CC_MASK (CC_O | CC_C) 822 TEST_BCD(aam, 0x12340547, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)); 823 TEST_BCD(aad, 0x12340407, CC_A, (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A)); 1143 eflags & (CC_C | CC_P | CC_Z | CC_S | CC_O | CC_A));\
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H A D | test-i386.h | 125 flags_in = (o ? CC_O : 0)
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H A D | test-amd64.h | 116 flags_in = (o ? CC_O : 0)
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/external/qemu/target-i386/ |
H A D | helper_template.h | 66 of = lshift((src1 ^ src2 ^ -1) & (src1 ^ CC_DST), 12 - DATA_BITS) & CC_O; 90 of = lshift((src1 ^ src2 ^ -1) & (src1 ^ CC_DST), 12 - DATA_BITS) & CC_O; 114 of = lshift((src1 ^ src2) & (src1 ^ CC_DST), 12 - DATA_BITS) & CC_O; 139 of = lshift((src1 ^ src2) & (src1 ^ CC_DST), 12 - DATA_BITS) & CC_O; 216 of = lshift(CC_SRC ^ CC_DST, 12 - DATA_BITS) & CC_O; 241 of = lshift(CC_SRC ^ CC_DST, 12 - DATA_BITS) & CC_O; 290 env->cc_tmp = (eflags & ~(CC_C | CC_O)) | 291 (lshift(src ^ t0, 11 - (DATA_BITS - 1)) & CC_O) | 319 env->cc_tmp = (eflags & ~(CC_C | CC_O)) | 320 (lshift(src ^ t0, 11 - (DATA_BITS - 1)) & CC_O) | [all...] |
H A D | exec.h | 279 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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H A D | cpu.h | 106 #define CC_O 0x0800 macro
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H A D | helper.c | 698 eflags & CC_O ? 'O' : '-', 725 eflags & CC_O ? 'O' : '-',
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H A D | op_helper.c | 1499 load_eflags(0, ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); 1563 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); 1579 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); 1877 if (eflags & CC_O) { 5022 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK)); 5378 ~(CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C | DF_MASK));
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H A D | translate.c | 871 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ 879 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */ 1627 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); 1630 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); 1706 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C)); 1709 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O); 6398 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
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/external/valgrind/main/none/tests/amd64/ |
H A D | amd64locked.c | 215 #define CC_O 0x0800 macro 217 #define CC_MASK (CC_C | CC_P | CC_A | CC_Z | CC_S | CC_O) 237 flags_in = (o ? CC_O : 0) \ 331 flags_in = (o ? CC_O : 0) \ 447 flags_in = (o ? CC_O : 0) \
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/external/valgrind/main/none/tests/x86/ |
H A D | x86locked.c | 200 #define CC_O 0x0800 macro 202 #define CC_MASK (CC_C | CC_P | CC_A | CC_Z | CC_S | CC_O) 222 flags_in = (o ? CC_O : 0) \ 309 flags_in = (o ? CC_O : 0) \ 411 flags_in = (o ? CC_O : 0) \
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/external/valgrind/main/memcheck/tests/amd64/ |
H A D | more_x87_fp.c | 67 #define CC_O 0x0800 macro
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/external/valgrind/main/memcheck/tests/x86/ |
H A D | more_x86_fp.c | 57 #define CC_O 0x0800 macro
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/external/qemu/ |
H A D | cpu-exec.c | 277 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 280 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 615 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nv50/codegen/ |
H A D | nv50_ir.h | 196 CC_O = 0x17 enumerator in enum:nv50_ir::CondCode
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H A D | nv50_ir_lowering_nv50.cpp | 639 const CondCode cc[4] = { CC_EQU, CC_S, CC_C, CC_O };
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H A D | nv50_ir_emit_nv50.cpp | 219 case CC_O: enc = 0x10; break;
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/external/mesa3d/src/gallium/drivers/nv50/codegen/ |
H A D | nv50_ir.h | 196 CC_O = 0x17 enumerator in enum:nv50_ir::CondCode
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H A D | nv50_ir_lowering_nv50.cpp | 639 const CondCode cc[4] = { CC_EQU, CC_S, CC_C, CC_O };
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H A D | nv50_ir_emit_nv50.cpp | 219 case CC_O: enc = 0x10; break;
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/nvc0/codegen/ |
H A D | nv50_ir_emit_nvc0.cpp | 216 case CC_O: val = 0x17; break;
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/external/mesa3d/src/gallium/drivers/nvc0/codegen/ |
H A D | nv50_ir_emit_nvc0.cpp | 216 case CC_O: val = 0x17; break;
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