/external/llvm/lib/Target/R600/ |
H A D | R600RegisterInfo.cpp | 29 BitVector Reserved(getNumRegs()); 31 Reserved.set(AMDGPU::ZERO); 32 Reserved.set(AMDGPU::HALF); 33 Reserved.set(AMDGPU::ONE); 34 Reserved.set(AMDGPU::ONE_INT); 35 Reserved.set(AMDGPU::NEG_HALF); 36 Reserved.set(AMDGPU::NEG_ONE); 37 Reserved.set(AMDGPU::PV_X); 38 Reserved.set(AMDGPU::ALU_LITERAL_X); 39 Reserved [all...] |
H A D | SIRegisterInfo.cpp | 27 BitVector Reserved(getNumRegs()); 28 return Reserved;
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/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/ |
H A D | R600RegisterInfo.cpp | 29 BitVector Reserved(getNumRegs()); 32 Reserved.set(AMDGPU::ZERO); 33 Reserved.set(AMDGPU::HALF); 34 Reserved.set(AMDGPU::ONE); 35 Reserved.set(AMDGPU::ONE_INT); 36 Reserved.set(AMDGPU::NEG_HALF); 37 Reserved.set(AMDGPU::NEG_ONE); 38 Reserved.set(AMDGPU::PV_X); 39 Reserved.set(AMDGPU::ALU_LITERAL_X); 40 Reserved [all...] |
H A D | SIRegisterInfo.cpp | 29 BitVector Reserved(getNumRegs()); 30 return Reserved;
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/external/mesa3d/src/gallium/drivers/radeon/ |
H A D | R600RegisterInfo.cpp | 29 BitVector Reserved(getNumRegs()); 32 Reserved.set(AMDGPU::ZERO); 33 Reserved.set(AMDGPU::HALF); 34 Reserved.set(AMDGPU::ONE); 35 Reserved.set(AMDGPU::ONE_INT); 36 Reserved.set(AMDGPU::NEG_HALF); 37 Reserved.set(AMDGPU::NEG_ONE); 38 Reserved.set(AMDGPU::PV_X); 39 Reserved.set(AMDGPU::ALU_LITERAL_X); 40 Reserved [all...] |
H A D | SIRegisterInfo.cpp | 29 BitVector Reserved(getNumRegs()); 30 return Reserved;
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/external/llvm/lib/Target/Mips/ |
H A D | MipsRegisterInfo.cpp | 117 BitVector Reserved(getNumRegs()); 121 Reserved.set(ReservedGPR32[I]); 124 Reserved.set(ReservedGPR64[I]); 130 Reserved.set(*Reg); 135 Reserved.set(*Reg); 140 Reserved.set(Mips::S0); 142 Reserved.set(Mips::FP); 143 Reserved.set(Mips::FP_64); 148 Reserved.set(Mips::HWR29); 149 Reserved [all...] |
/external/llvm/lib/Target/Sparc/ |
H A D | SparcRegisterInfo.cpp | 48 BitVector Reserved(getNumRegs()); 50 Reserved.set(SP::G1); 54 Reserved.set(SP::G2); 55 Reserved.set(SP::G3); 56 Reserved.set(SP::G4); 60 Reserved.set(SP::G5); 62 Reserved.set(SP::O6); 63 Reserved.set(SP::I6); 64 Reserved.set(SP::I7); 65 Reserved [all...] |
/external/llvm/lib/Target/AArch64/ |
H A D | AArch64RegisterInfo.cpp | 62 BitVector Reserved(getNumRegs()); 65 Reserved.set(AArch64::XSP); 66 Reserved.set(AArch64::WSP); 68 Reserved.set(AArch64::XZR); 69 Reserved.set(AArch64::WZR); 72 Reserved.set(AArch64::X29); 73 Reserved.set(AArch64::W29); 76 return Reserved;
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/external/llvm/lib/Target/SystemZ/ |
H A D | SystemZRegisterInfo.cpp | 39 BitVector Reserved(getNumRegs()); 44 Reserved.set(SystemZ::R11D); 45 Reserved.set(SystemZ::R11W); 46 Reserved.set(SystemZ::R10Q); 50 Reserved.set(SystemZ::R15D); 51 Reserved.set(SystemZ::R15W); 52 Reserved.set(SystemZ::R14Q); 53 return Reserved;
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/external/llvm/lib/Target/MSP430/ |
H A D | MSP430RegisterInfo.cpp | 77 BitVector Reserved(getNumRegs()); 81 Reserved.set(MSP430::PCB); 82 Reserved.set(MSP430::SPB); 83 Reserved.set(MSP430::SRB); 84 Reserved.set(MSP430::CGB); 85 Reserved.set(MSP430::PCW); 86 Reserved.set(MSP430::SPW); 87 Reserved.set(MSP430::SRW); 88 Reserved.set(MSP430::CGW); 92 Reserved [all...] |
/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonRegisterInfo.cpp | 74 BitVector Reserved(getNumRegs()); 75 Reserved.set(HEXAGON_RESERVED_REG_1); 76 Reserved.set(HEXAGON_RESERVED_REG_2); 77 Reserved.set(Hexagon::R29); 78 Reserved.set(Hexagon::R30); 79 Reserved.set(Hexagon::R31); 80 Reserved.set(Hexagon::D14); 81 Reserved.set(Hexagon::D15); 82 Reserved.set(Hexagon::LC0); 83 Reserved [all...] |
/external/chromium_org/third_party/icu/source/test/testdata/ |
H A D | tstfiles.mk | 1 # Copyright (C) 2007, International Business Machines Corporation and others. All Rights Reserved.
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/external/icu4c/data/mappings/ |
H A D | ucmlocal.mk | 1 # Copyright 2008 Google Inc. All Rights Reserved.
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/external/icu4c/test/testdata/ |
H A D | tstfiles.mk | 1 # Copyright (C) 2007, International Business Machines Corporation and others. All Rights Reserved.
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/external/llvm/lib/Target/XCore/ |
H A D | XCoreRegisterInfo.cpp | 73 BitVector Reserved(getNumRegs()); 76 Reserved.set(XCore::CP); 77 Reserved.set(XCore::DP); 78 Reserved.set(XCore::SP); 79 Reserved.set(XCore::LR); 81 Reserved.set(XCore::R10); 83 return Reserved;
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/external/llvm/lib/Target/PowerPC/ |
H A D | PPCRegisterInfo.cpp | 141 BitVector Reserved(getNumRegs()); 147 Reserved.set(PPC::ZERO); 148 Reserved.set(PPC::ZERO8); 152 Reserved.set(PPC::FP); 153 Reserved.set(PPC::FP8); 157 Reserved.set(PPC::BP); 158 Reserved.set(PPC::BP8); 162 Reserved.set(PPC::CTR); 163 Reserved.set(PPC::CTR8); 165 Reserved [all...] |
/external/chromium_org/third_party/freetype/src/sfnt/ |
H A D | ttmtx.c | 135 FT_FRAME_SHORT ( Reserved[0] ), 136 FT_FRAME_SHORT ( Reserved[1] ), 137 FT_FRAME_SHORT ( Reserved[2] ), 138 FT_FRAME_SHORT ( Reserved[3] ),
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/external/freetype/src/sfnt/ |
H A D | ttmtx.c | 135 FT_FRAME_SHORT ( Reserved[0] ), 136 FT_FRAME_SHORT ( Reserved[1] ), 137 FT_FRAME_SHORT ( Reserved[2] ), 138 FT_FRAME_SHORT ( Reserved[3] ),
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/external/libppp/src/ |
H A D | chap.h | 68 char Reserved[8]; member in struct:MSCHAPv2_resp
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/external/llvm/lib/CodeGen/ |
H A D | RegisterClassInfo.cpp | 65 if (Reserved.size() != RR.size() || RR != Reserved) { 67 Reserved = RR; 99 if (Reserved.test(PhysReg))
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/external/chromium_org/third_party/icu/source/test/perf/unisetperf/draft/ |
H A D | contperf.bat | 2 rem others. All Rights Reserved.
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H A D | span16perf.bat | 2 rem others. All Rights Reserved.
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H A D | span8perf.bat | 2 rem others. All Rights Reserved.
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/external/chromium_org/third_party/icu/source/test/perf/utrie2perf/ |
H A D | utrie2perf.bat | 2 rem All Rights Reserved.
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