Searched refs:Undef (Results 1 - 25 of 25) sorted by relevance

/external/clang/test/SemaCXX/
H A Dqualified-id-lookup.cpp100 struct Undef { // expected-note{{definition of 'Undef' is not complete until the closing '}'}} struct
103 Undef::type member;
105 static int size = sizeof(Undef); // expected-error{{invalid application of 'sizeof' to an incomplete type 'Undef'}}
110 int Undef::f() {
111 return sizeof(Undef);
/external/valgrind/main/memcheck/tests/
H A Dorigin1-yes.stderr.exp2 Undef 1 of 8 (stack, 32 bit)
9 Undef 2 of 8 (stack, 32 bit)
16 Undef 3 of 8 (stack, 64 bit)
23 Undef 4 of 8 (mallocd, 32-bit)
31 Undef 5 of 8 (realloc)
39 Undef 6 of 8 (MALLOCLIKE_BLOCK)
46 Undef 7 of 8 (brk)
50 Undef 8 of 8 (MAKE_MEM_UNDEFINED)
H A Dorigin3-no.stderr.exp2 Undef 1 of 8 (8 bit undef)
12 Undef 2 of 8 (8 bits of 32 undef)
20 Undef 3 of 8 (32 bit undef)
30 Undef 4 of 8 (32 bit undef, unaligned)
40 Undef 5 of 8 (32 bit undef, modified)
50 Undef 6 of 8 (32 bit undef, unaligned, strange, #1)
59 Undef 7 of 8 (32 bit undef, unaligned, strange, #2)
68 Undef 8 of 8 (32 bit undef, unaligned, strange, #3)
H A Dorigin2-not-quite.stderr.exp2 Undef 1 of 3 (64-bit FP)
12 Undef 2 of 3 (32-bit FP)
22 Undef 3 of 3 (int)
/external/llvm/include/llvm/CodeGen/
H A DMachineInstrBuilder.h35 Undef = 0x20, enumerator in enum:llvm::RegState::__anon21841
39 DefineNoRead = Define | Undef,
73 flags & RegState::Undef,
396 return B ? RegState::Undef : 0;
/external/llvm/unittests/IR/
H A DConstantsTest.cpp27 Constant* Undef = UndefValue::get(Int1); local
55 EXPECT_EQ(Undef, ConstantExpr::getShl(One, One));
63 EXPECT_EQ(Undef, ConstantExpr::getLShr(One, One));
67 EXPECT_EQ(Undef, ConstantExpr::getAShr(One, One));
/external/llvm/lib/Transforms/Scalar/
H A DStructurizeCFG.cpp513 Value *Undef = UndefValue::get(Phi.getType()); local
514 Phi.addIncoming(Undef, From);
536 Value *Undef = UndefValue::get(Phi->getType()); local
538 Updater.AddAvailableValue(&Func->getEntryBlock(), Undef);
539 Updater.AddAvailableValue(To, Undef);
551 Updater.AddAvailableValue(Dominator.getResult(), Undef);
832 Value *Undef = UndefValue::get(II->getType()); local
834 Updater.AddAvailableValue(&Func->getEntryBlock(), Undef);
H A DReassociate.cpp798 Constant *Undef = UndefValue::get(I->getType()); local
800 Undef, Undef, "", I);
/external/llvm/lib/Transforms/InstCombine/
H A DInstCombinePHI.cpp786 Value *Undef = UndefValue::get(FirstPhi.getType()); local
788 ReplaceInstUsesWith(*PHIsToSlice[i], Undef);
789 return ReplaceInstUsesWith(FirstPhi, Undef);
H A DInstCombineSimplifyDemanded.cpp940 Constant *Undef = UndefValue::get(EltTy); local
945 Elts.push_back(Undef);
954 Elts.push_back(Undef);
/external/chromium_org/third_party/angle/tests/preprocessor_tests/
H A Ddefine_test.cpp721 TEST_F(DefineTest, Undef)
/external/valgrind/main/coregrind/m_debuginfo/
H A Dpriv_storage.h327 } Undef; member in union:__anon28051::__anon28052
/external/clang/lib/CodeGen/
H A DCodeGenFunction.cpp529 llvm::Value *Undef = llvm::UndefValue::get(Int32Ty); local
530 AllocaInsertPt = new llvm::BitCastInst(Undef, Int32Ty, "", EntryBB);
H A DItaniumCXXABI.cpp920 RValue Undef = RValue::get(llvm::UndefValue::get(T)); local
921 return ItaniumCXXABI::EmitReturnFromThunk(CGF, Undef, ResultType);
/external/llvm/include/llvm/IR/
H A DIRBuilder.h1392 Value *Undef = UndefValue::get(VectorType::get(V->getType(), NumElts)); local
1393 V = CreateInsertElement(Undef, V, ConstantInt::get(I32Ty, 0),
1398 return CreateShuffleVector(V, Undef, Zeros, Name + ".splat");
/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp480 // Undef for 0b11 just in case it occurs. Don't want the compiler to optimise
482 enum OpcTypes { SBFM = 0, BFM, UBFM, Undef } Opc; enumerator in enum:OpcTypes
/external/llvm/lib/Target/X86/
H A DX86InstrInfo.cpp1825 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
3699 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
3998 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
4004 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
H A DX86ISelLowering.cpp5008 else if (Elt.getOpcode() == ISD::UNDEF) // Undef as zero up to PreferredNum.
6140 // of the result come from the same quadword of one of the two inputs. Undef
8779 SDValue Undef = DAG.getUNDEF(InVT); local
8781 SDValue OpLo = getUnpackl(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8782 SDValue OpHi = getUnpackh(DAG, dl, InVT, In, NeedZero ? ZeroVec : Undef);
8864 SDValue Undef = DAG.getUNDEF(VT); local
8865 OpLo = DAG.getVectorShuffle(VT, DL, OpLo, Undef, ShufMask1);
8866 OpHi = DAG.getVectorShuffle(VT, DL, OpHi, Undef, ShufMask1);
8917 SDValue Undef = DAG.getUNDEF(MVT::v16i8); local
8918 OpLo = DAG.getVectorShuffle(MVT::v16i8, DL, OpLo, Undef, ShufMask
10176 SDValue Undef = DAG.getUNDEF(InVT); local
13830 unsigned Undef = MRI.createVirtualRegister(RC32); local
[all...]
H A DX86ISelDAGToDAG.cpp1836 SDValue Undef = SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, local
1848 SDValue RetVals[] = { Undef, Ret };
/external/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAG.cpp4475 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4476 return getLoad(ISD::UNINDEXED, ISD::NON_EXTLOAD, VT, dl, Chain, Ptr, Undef,
4486 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4487 return getLoad(ISD::UNINDEXED, ExtType, VT, dl, Chain, Ptr, Undef,
4538 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4539 SDValue Ops[] = { Chain, Val, Ptr, Undef };
4606 SDValue Undef = getUNDEF(Ptr.getValueType()); local
4607 SDValue Ops[] = { Chain, Val, Ptr, Undef };
H A DDAGCombiner.cpp2575 // Undef bits can contribute to a possible optimisation if set, so
5761 /// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
7414 SDValue Undef = DAG.getUNDEF(N->getValueType(0)); local
7418 Undef.getNode()->dump(&DAG);
7421 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Undef); local
/external/llvm/lib/Transforms/Vectorize/
H A DSLPVectorizer.cpp1458 Value *Undef = UndefValue::get(Ty); local
1459 Scalar->replaceAllUsesWith(Undef);
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp1985 SDValue Chain = LD->getChain(), Undef = DAG.getUNDEF(VT); local
1995 SDValue LDL = createLoadLR(MipsISD::LDL, DAG, LD, Chain, Undef,
2001 SDValue LWL = createLoadLR(MipsISD::LWL, DAG, LD, Chain, Undef,
/external/llvm/lib/CodeGen/
H A DIfConversion.cpp1004 MIB.addReg(Reg, RegState::Implicit | RegState::Undef);
/external/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp3873 .addReg(DReg, RegState::Undef)

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