Searched refs:operands (Results 1 - 14 of 14) sorted by relevance

/art/compiler/dex/quick/x86/
H A Dassemble_x86.cc371 return lir->operands[0]; // length of nop is sole operand
374 case kReg: // lir operands - 0: reg
376 case kMem: // lir operands - 0: base, 1: disp
377 return ComputeSize(entry, lir->operands[0], lir->operands[1], false);
378 case kArray: // lir operands - 0: base, 1: index, 2: scale, 3: disp
379 return ComputeSize(entry, lir->operands[0], lir->operands[3], true);
380 case kMemReg: // lir operands - 0: base, 1: disp, 2: reg
381 return ComputeSize(entry, lir->operands[
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H A Dtarget_x86.cc215 DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands.
217 int operand = lir->operands[operand_number];
/art/compiler/dex/quick/
H A Dmir_to_lir-inl.h46 insn->operands[0] = op0;
47 insn->operands[1] = op1;
48 insn->operands[2] = op2;
49 insn->operands[3] = op3;
50 insn->operands[4] = op4;
63 * operands.
169 SetupRegMask(&lir->def_mask, lir->operands[0]);
173 SetupRegMask(&lir->def_mask, lir->operands[1]);
186 SetupRegMask(&lir->use_mask, lir->operands[i]);
H A Dlocal_optimizations.cc23 /* Check RAW, WAR, and RAW dependency on the register operands */
102 native_reg_id = (GetTargetInstFlags(this_lir->opcode) & IS_STORE) ? this_lir->operands[2]
103 : this_lir->operands[0];
105 native_reg_id = this_lir->operands[0];
164 SameRegType(check_lir->operands[0], native_reg_id)) {
169 if (check_lir->operands[0] != native_reg_id) {
170 ConvertMemOpIntoMove(check_lir, check_lir->operands[0], native_reg_id);
178 bool reg_compatible = SameRegType(check_lir->operands[0], native_reg_id);
187 if (check_lir->operands[0] !=
189 ConvertMemOpIntoMove(check_lir, check_lir->operands[
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H A Dcodegen_util.cc118 int dest = lir->operands[0];
137 if (lir->operands[0] == 0) {
138 lir->operands[0] = reinterpret_cast<uintptr_t>("No instruction string");
141 << lir->dalvik_offset << " @ " << reinterpret_cast<char*>(lir->operands[0]);
174 << std::hex << lir->operands[0] << "|" << std::dec <<
175 lir->operands[0];
268 lir_insn->operands[0]);
288 if ((static_cast<unsigned>(value - data_target->operands[0])) <= delta)
300 if (lo_match && (data_target->operands[0] == val_hi)) {
302 lo_target->operands[
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H A Dgen_common.cc510 LIR* resume_lab = reinterpret_cast<LIR*>(lab->operands[0]);
511 current_dalvik_offset_ = lab->operands[1];
525 CallInfo* info = reinterpret_cast<CallInfo*>(lab->operands[0]);
530 LIR* resume_lab = reinterpret_cast<LIR*>(lab->operands[2]);
543 current_dalvik_offset_ = lab->operands[1];
546 int v1 = lab->operands[2];
547 int v2 = lab->operands[3];
551 switch (lab->operands[0]) {
637 LOG(FATAL) << "Unexpected throw kind: " << lab->operands[0];
H A Dgen_invoke.cc354 data_target->operands[1] = type;
368 data_target->operands[1] = type;
397 data_target->operands[1] = type;
512 data_target->operands[1] = kInterface;
929 launch_pad->operands[2] = 0; // no resumption
1083 launch_pad->operands[2] = reinterpret_cast<uintptr_t>(resume_tgt);
1120 launch_pad->operands[2] = 0; // No return possible
H A Dmir_to_lir.cc695 block_label_list_[block_id].operands[0] = bb->start_offset;
H A Dmir_to_lir.h118 int operands[5]; // [0..4] = [dest, src1, src2, extra, extra2]. member in struct:art::LIR
/art/compiler/dex/quick/mips/
H A Dassemble_mips.cc37 * operands: number of operands (for sanity check purposes)
51 * 0 -> operands[0] (dest)
52 * 1 -> operands[1] (src1)
53 * 2 -> operands[2] (src2)
54 * 3 -> operands[3] (extra)
485 LIR* hop_branch = RawLIR(dalvik_offset, opcode, lir->operands[0],
486 lir->operands[1], 0, 0, 0, hop_target);
534 * found in operands[0]. The delta is determined by
536 * kPseudoTargetLabel and is stored in operands[
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H A Dtarget_mips.cc172 operand = lir->operands[nc-'0'];
212 int offset_1 = lir->operands[0];
213 int offset_2 = NEXT_LIR(lir)->operands[0];
/art/compiler/dex/quick/arm/
H A Dassemble_arm.cc35 * operands: number of operands (for sanity check purposes)
49 * 0 -> operands[0] (dest)
50 * 1 -> operands[1] (src1)
51 * 2 -> operands[2] (src2)
52 * 3 -> operands[3] (extra)
1012 if ((lir->opcode == kPseudoPseudoAlign4) && (lir->operands[0] == 1)) {
1039 ((lir->opcode == kThumb2Vldrd) && (lir->operands[1] == r15pc)) ||
1040 ((lir->opcode == kThumb2Vldrs) && (lir->operands[1] == r15pc))) {
1071 ? lir->operands[
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H A Dtarget_arm.cc137 lir->def_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
141 lir->def_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
145 lir->def_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
149 for (int i = 0; i < lir->operands[2]; i++) {
150 SetupRegMask(&lir->def_mask, lir->operands[1] + i);
164 lir->use_mask |= ENCODE_ARM_REG_LIST(lir->operands[0]);
168 lir->use_mask |= ENCODE_ARM_REG_LIST(lir->operands[1]);
172 lir->use_mask |= ENCODE_ARM_REG_FPCS_LIST(lir->operands[0]);
176 for (int i = 0; i < lir->operands[2]; i++) {
177 SetupRegMask(&lir->use_mask, lir->operands[
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/art/compiler/dex/
H A Dmir_optimization.cc426 * the Phi node has more than two operands, we will arbitrarily use the SSA
718 * the "and" of all the Phi's operands.
722 int operands = (df_attributes & DF_NULL_TRANSFER_0) ? 1 : local
725 for (int i = 0; i < operands; i++) {

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