/art/compiler/dex/quick/x86/ |
H A D | utility_x86.cc | 198 LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, int rBase, argument 218 return NewLIR3(opcode, r_dest, rBase, offset); 307 LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp) { argument 315 return NewLIR2(opcode, rBase, disp); 345 LIR* X86Mir2Lir::LoadBaseIndexedDisp(int rBase, int r_index, int scale, argument 402 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET); 404 if (rBase == r_dest) { 405 load2 = NewLIR3(opcode, r_dest_hi, rBase, 407 load = NewLIR3(opcode, r_dest, rBase, displacement + LOWORD_OFFSET); 409 load = NewLIR3(opcode, r_dest, rBase, displacemen 445 LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) argument 451 LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) argument 457 LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, int s_reg) argument 463 StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg) argument 544 StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) argument 550 StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) argument 557 StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) argument [all...] |
H A D | codegen_x86.h | 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg); 34 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size); 37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size); 42 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi); 43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size); 44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 146 LIR* OpMem(OpKind op, int rBase, int disp); 152 LIR* OpRegMem(OpKind op, int r_dest, int rBase, in [all...] |
H A D | int_x86.cc | 239 void X86Mir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) { argument 240 NewLIR5(kX86Lea32RA, rBase, reg1, reg2, scale, offset); 257 LIR* X86Mir2Lir::OpVldm(int rBase, int count) { argument 262 LIR* X86Mir2Lir::OpVstm(int rBase, int count) { argument
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/art/compiler/dex/quick/mips/ |
H A D | utility_mips.cc | 336 LIR* MipsMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest, argument 353 first = NewLIR3(kMipsAddu, t_reg , rBase, r_index); 356 NewLIR3(kMipsAddu, t_reg , rBase, t_reg); 388 LIR* MipsMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, argument 405 first = NewLIR3(kMipsAddu, t_reg , rBase, r_index); 408 NewLIR3(kMipsAddu, t_reg , rBase, t_reg); 434 LIR* MipsMir2Lir::LoadBaseDispBody(int rBase, int displacement, int r_dest, argument 498 load = res = NewLIR3(opcode, r_dest, displacement, rBase); 501 displacement + LOWORD_OFFSET, rBase); 503 displacement + HIWORD_OFFSET, rBase); 532 LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) argument 538 LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, int s_reg) argument 543 StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size) argument 625 StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) argument 630 StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) argument 640 OpMem(OpKind op, int rBase, int disp) argument 645 StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg) argument 651 OpRegMem(OpKind op, int r_dest, int rBase, int offset) argument 657 LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_dest, int r_dest_hi, OpSize size, int s_reg) argument [all...] |
H A D | codegen_mips.h | 33 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg); 34 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 36 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size); 37 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 41 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size); 42 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi); 43 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size); 44 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 146 LIR* OpMem(OpKind op, int rBase, int disp); 152 LIR* OpRegMem(OpKind op, int r_dest, int rBase, in [all...] |
H A D | call_mips.cc | 48 * addiu rBase, r_RA, <table> - <BaseLabel> ; table relative to BaseLabel 49 addu rEnd, rEnd, rBase ; end of table 52 * beq rBase, rEnd, done 53 * lw r_key, 0(rBase) 54 * addu rBase, 8 56 * lw r_disp, -4(rBase) 103 int rBase = AllocTemp(); local 104 NewLIR4(kMipsDelta, rBase, 0, reinterpret_cast<uintptr_t>(base_label), 106 OpRegRegReg(kOpAdd, rEnd, rEnd, rBase); 114 LIR* exit_branch = OpCmpBranch(kCondEq, rBase, rEn 198 int rBase = AllocTemp(); local [all...] |
H A D | int_mips.cc | 253 void MipsMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) { argument 276 LIR* MipsMir2Lir::OpVldm(int rBase, int count) { argument 281 LIR* MipsMir2Lir::OpVstm(int rBase, int count) { argument
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/art/compiler/dex/quick/arm/ |
H A D | utility_arm.cc | 642 LIR* ArmMir2Lir::LoadBaseIndexed(int rBase, int r_index, int r_dest, argument 644 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_dest); 672 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index, 675 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_index); 699 load = NewLIR3(opcode, r_dest, rBase, r_index); 701 load = NewLIR4(opcode, r_dest, rBase, r_index, scale); 706 LIR* ArmMir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src, argument 708 bool all_low_regs = ARM_LOWREG(rBase) && ARM_LOWREG(r_index) && ARM_LOWREG(r_src); 736 NewLIR4(kThumb2AddRRR, reg_ptr, rBase, r_index, 739 OpRegRegReg(kOpAdd, reg_ptr, rBase, r_inde 771 LoadBaseDispBody(int rBase, int displacement, int r_dest, int r_dest_hi, OpSize size, int s_reg) argument 891 LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) argument 896 LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, int s_reg) argument 902 StoreBaseDispBody(int rBase, int displacement, int r_src, int r_src_hi, OpSize size) argument 1005 StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) argument 1010 StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) argument 1040 OpMem(OpKind op, int rBase, int disp) argument 1045 StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_src, int r_src_hi, OpSize size, int s_reg) argument 1052 OpRegMem(OpKind op, int r_dest, int rBase, int offset) argument 1057 LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, int r_dest, int r_dest_hi, OpSize size, int s_reg) argument [all...] |
H A D | codegen_arm.h | 32 LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg); 33 LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 35 LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size); 36 LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 40 LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size); 41 LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi); 42 LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size); 43 LIR* StoreBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 145 LIR* OpMem(OpKind op, int rBase, int disp); 151 LIR* OpRegMem(OpKind op, int r_dest, int rBase, in [all...] |
H A D | call_arm.cc | 300 * adr rBase, <table> 304 * ldmia rBase!, {r_key, r_disp} 329 int rBase = AllocTemp(); local 340 NewLIR3(kThumb2Adr, rBase, 0, reinterpret_cast<uintptr_t>(tab_rec)); 347 NewLIR2(kThumb2LdmiaWB, rBase, (1 << r_key) | (1 << r_disp));
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H A D | int_arm.cc | 497 void ArmMir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) { argument 568 LIR* ArmMir2Lir::OpVldm(int rBase, int count) { argument 569 return NewLIR3(kThumb2Vldms, rBase, fr0, count); 572 LIR* ArmMir2Lir::OpVstm(int rBase, int count) { argument 573 return NewLIR3(kThumb2Vstms, rBase, fr0, count);
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/art/compiler/dex/quick/ |
H A D | gen_common.cc | 345 int rBase; local 349 rBase = AllocTemp(); 351 mirror::ArtMethod::DeclaringClassOffset().Int32Value(), rBase); 366 rBase = TargetReg(kArg0); 367 LockTemp(rBase); 370 rBase); 371 LoadWordDisp(rBase, 373 sizeof(int32_t*) * ssb_index, rBase); 374 // rBase now points at appropriate static storage base (Class*) 377 LIR* branch_over = OpCmpImmBranch(kCondNe, rBase, 431 int rBase; local [all...] |
H A D | gen_loadstore.cc | 78 LIR* Mir2Lir::LoadWordDisp(int rBase, int displacement, int r_dest) { argument 79 return LoadBaseDisp(rBase, displacement, r_dest, kWord, 83 LIR* Mir2Lir::StoreWordDisp(int rBase, int displacement, int r_src) { argument 84 return StoreBaseDisp(rBase, displacement, r_src, kWord);
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H A D | mir_to_lir.h | 507 LIR* LoadWordDisp(int rBase, int displacement, int r_dest); 514 LIR* StoreWordDisp(int rBase, int displacement, int r_src); 531 virtual LIR* LoadBaseDisp(int rBase, int displacement, int r_dest, OpSize size, int s_reg) = 0; 532 virtual LIR* LoadBaseDispWide(int rBase, int displacement, int r_dest_lo, int r_dest_hi, 534 virtual LIR* LoadBaseIndexed(int rBase, int r_index, int r_dest, int scale, OpSize size) = 0; 535 virtual LIR* LoadBaseIndexedDisp(int rBase, int r_index, int scale, int displacement, 539 virtual LIR* StoreBaseDisp(int rBase, int displacement, int r_src, OpSize size) = 0; 540 virtual LIR* StoreBaseDispWide(int rBase, int displacement, int r_src_lo, int r_src_hi) = 0; 541 virtual LIR* StoreBaseIndexed(int rBase, int r_index, int r_src, int scale, OpSize size) = 0; 542 virtual LIR* StoreBaseIndexedDisp(int rBase, in [all...] |