1#ifndef __LINUX_MFD_TIMPANI_AUDIO_H 2#define __LINUX_MFD_TIMPANI_AUDIO_H 3 4/* 5 * MREF 6 */ 7#define TIMPANI_A_MREF (0x3) 8#define TIMPANI_MREF_RWC "RW" 9#define TIMPANI_MREF_POR 0xe2 10#define TIMPANI_MREF_S 0 11#define TIMPANI_MREF_M 0xFF 12 13#define TIMPANI_MREF_MREF_BG_EN_S 7 14#define TIMPANI_MREF_MREF_BG_EN_M 0x80 15#define TIMPANI_MREF_MREF_BG_EN_ENABLE 0x0 16#define TIMPANI_MREF_MREF_BG_EN_DISABLE 0x1 17 18#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_S 6 19#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_M 0x40 20#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_ENABLE_NORMAL_OP 0x0 21#define TIMPANI_MREF_MREF_BG_REF_CUR_EN_DISABLE 0x1 22 23#define TIMPANI_MREF_MREF_200K_MODE_EN_S 5 24#define TIMPANI_MREF_MREF_200K_MODE_EN_M 0x20 25#define TIMPANI_MREF_MREF_200K_MODE_EN_ENABLE 0x0 26#define TIMPANI_MREF_MREF_200K_MODE_EN_DISABLE 0x1 27 28#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_S 4 29#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_M 0x10 30#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_DISABLE 0x0 31#define TIMPANI_MREF_MREF_PRE_CHARGE_EN_ENABLE 0x1 32 33#define TIMPANI_MREF_MREF_100UA_CUR_CONN_S 3 34#define TIMPANI_MREF_MREF_100UA_CUR_CONN_M 0x8 35#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ON_CHIP_RESISTOR_NORMAL_OP 0x0 36#define TIMPANI_MREF_MREF_100UA_CUR_CONN_ATEST 0x1 37 38#define TIMPANI_MREF_MREF_PTAT_CURRENT_S 2 39#define TIMPANI_MREF_MREF_PTAT_CURRENT_M 0x4 40#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_10UA_PTAT_NORMAL_OP 0x0 41#define TIMPANI_MREF_MREF_PTAT_CURRENT_V_5UA_PTAT_BIAS_CURRENT 0x1 42 43#define TIMPANI_MREF_MREF_400K_MODE_EN_S 1 44#define TIMPANI_MREF_MREF_400K_MODE_EN_M 0x2 45#define TIMPANI_MREF_MREF_400K_MODE_EN_ENABLE 0x0 46#define TIMPANI_MREF_MREF_400K_MODE_EN_DISABLE 0x1 47 48#define TIMPANI_MREF_RESERVED_S 0 49#define TIMPANI_MREF_RESERVED_M 0x1 50 51 52/* For CDAC_IDAC_REF_CUR */ 53#define TIMPANI_A_CDAC_IDAC_REF_CUR (0x4) 54#define TIMPANI_CDAC_IDAC_REF_CUR_RWC "RW" 55#define TIMPANI_CDAC_IDAC_REF_CUR_POR 0x8c 56#define TIMPANI_CDAC_IDAC_REF_CUR_S 0 57#define TIMPANI_CDAC_IDAC_REF_CUR_M 0xFF 58 59 60#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_S 5 61#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_M 0xE0 62#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_4UA 0x0 63#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_6UA 0x1 64#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_8UA 0x2 65#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_9UA 0x3 66#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_10UA_NORMAL_OP 0x4 67#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_11UA 0x5 68#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_13UA 0x6 69#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_REF_BUFF_CUR_V_15UA 0x7 70 71#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_S 2 72#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_M 0x1C 73#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_8_5UA 0x0 74#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_0UA 0x1 75#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_9_5UA 0x2 76#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_0UA_NORMAL_OP 0x3 77#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_10_5UA 0x4 78#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_0UA 0x5 79#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_11_5UA 0x6 80#define TIMPANI_CDAC_IDAC_REF_CUR_CDAC_BIAS_CUR_V_12_0UA 0x7 81 82#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_S 0 83#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_M 0x3 84#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_2UA 0x0 85#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_3UA 0x1 86#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_5UA_NORMAL_OP 0x2 87#define TIMPANI_CDAC_IDAC_REF_CUR_IDAC_REF_CUR_V_8UA 0x3 88 89 90/* -- For TXADC12_REF_CURR */ 91#define TIMPANI_A_TXADC12_REF_CURR (0x5) 92#define TIMPANI_TXADC12_REF_CURR_RWC "RW" 93#define TIMPANI_TXADC12_REF_CURR_POR 0xa0 94#define TIMPANI_TXADC12_REF_CURR_S 0 95#define TIMPANI_TXADC12_REF_CURR_M 0xFF 96 97 98#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_S 6 99#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_M 0xC0 100#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_50UA 0x0 101#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_45UA 0x1 102#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2 103#define TIMPANI_TXADC12_REF_CURR_TXADC1_REF_BUFF_CUR_V_35UA 0x3 104 105#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_S 4 106#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_M 0x30 107#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_50UA 0x0 108#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_45UA 0x1 109#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_40UA_NORMAL_OP 0x2 110#define TIMPANI_TXADC12_REF_CURR_TXADC2_REF_BUFF_CUR_V_35UA 0x3 111 112#define TIMPANI_TXADC12_REF_CURR_RESERVED_S 0 113#define TIMPANI_TXADC12_REF_CURR_RESERVED_M 0xF 114 115 116/* -- For TXADC3_EN */ 117#define TIMPANI_A_TXADC3_EN (0x9) 118#define TIMPANI_TXADC3_EN_RWC "RW" 119#define TIMPANI_TXADC3_EN_POR 0 120#define TIMPANI_TXADC3_EN_S 0 121#define TIMPANI_TXADC3_EN_M 0xFF 122 123 124#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_S 7 125#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_M 0x80 126#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_DISABLE 0x0 127#define TIMPANI_TXADC3_EN_TXADC3_REF_EN_ENABLE 0x1 128 129#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_S 6 130#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_M 0x40 131#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 132#define TIMPANI_TXADC3_EN_TXADC3_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 133 134#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_S 5 135#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_M 0x20 136#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_DISABLE 0x0 137#define TIMPANI_TXADC3_EN_TXADC3_OTA1_EN_ENABLE 0x1 138 139#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_S 4 140#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_M 0x10 141#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_DISABLE 0x0 142#define TIMPANI_TXADC3_EN_TXADC3_OTA2_EN_ENABLE 0x1 143 144#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_S 3 145#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_M 0x8 146#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_DISABLE 0x0 147#define TIMPANI_TXADC3_EN_TXADC3_COMP_EN_ENABLE 0x1 148 149#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_S 2 150#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_M 0x4 151#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_DISABLE 0x0 152#define TIMPANI_TXADC3_EN_TXADC3_DEM_EN_ENABLE 0x1 153 154#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_S 1 155#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_M 0x2 156#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_DISABLE 0x0 157#define TIMPANI_TXADC3_EN_TXADC3_DEM_ERROR_DET_EN_ENABLE 0x1 158 159#define TIMPANI_TXADC3_EN_RESERVED_S 0 160#define TIMPANI_TXADC3_EN_RESERVED_M 0x1 161 162 163/* -- For TXADC4_EN */ 164#define TIMPANI_A_TXADC4_EN (0xA) 165#define TIMPANI_TXADC4_EN_RWC "RW" 166#define TIMPANI_TXADC4_EN_POR 0 167#define TIMPANI_TXADC4_EN_S 0 168#define TIMPANI_TXADC4_EN_M 0xFF 169 170 171#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_S 7 172#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_M 0x80 173#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_DISABLE 0x0 174#define TIMPANI_TXADC4_EN_TXADC4_REF_EN_ENABLE 0x1 175 176#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_S 6 177#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_M 0x40 178#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 179#define TIMPANI_TXADC4_EN_TXADC4_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 180 181#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_S 5 182#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_M 0x20 183#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_DISABLE 0x0 184#define TIMPANI_TXADC4_EN_TXADC4_OTA1_EN_ENABLE 0x1 185 186#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_S 4 187#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_M 0x10 188#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_DISABLE 0x0 189#define TIMPANI_TXADC4_EN_TXADC4_OTA2_EN_ENABLE 0x1 190 191#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_S 3 192#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_M 0x8 193#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_DISABLE 0x0 194#define TIMPANI_TXADC4_EN_TXADC4_COMP_EN_ENABLE 0x1 195 196#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_S 2 197#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_M 0x4 198#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_DISABLE 0x0 199#define TIMPANI_TXADC4_EN_TXADC4_DEM_EN_ENABLE 0x1 200 201#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_S 1 202#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_M 0x2 203#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_DISABLE 0x0 204#define TIMPANI_TXADC4_EN_TXADC4_DEM_ERROR_DET_EN_ENABLE 0x1 205 206#define TIMPANI_TXADC4_EN_RESERVED_S 0 207#define TIMPANI_TXADC4_EN_RESERVED_M 0x1 208 209 210/* -- For CODEC_TXADC_STATUS_REGISTER_1 */ 211#define TIMPANI_A_CODEC_TXADC_STATUS_REGISTER_1 (0xB) 212#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RWC "R" 213#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_POR 0 214#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_S 0 215#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_M 0xFF 216 217 218#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_S 7 219#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC1_DEM_ERROR_M 0x80 220 221#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_S 6 222#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC2_DEM_ERROR_M 0x40 223 224#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_S 5 225#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC3_DEM_ERROR_M 0x20 226 227#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_S 4 228#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_TXADC4_DEM_ERROR_M 0x10 229 230#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_S 0 231#define TIMPANI_CODEC_TXADC_STATUS_REGISTER_1_RESERVED_M 0xF 232 233 234/* -- For TXFE1 */ 235#define TIMPANI_A_TXFE1 (0xD) 236#define TIMPANI_TXFE1_RWC "RW" 237#define TIMPANI_TXFE1_POR 0 238#define TIMPANI_TXFE1_S 0 239#define TIMPANI_TXFE1_M 0xFF 240 241 242#define TIMPANI_TXFE1_TXFE1_EN_S 7 243#define TIMPANI_TXFE1_TXFE1_EN_M 0x80 244#define TIMPANI_TXFE1_TXFE1_EN_DISABLE 0x0 245#define TIMPANI_TXFE1_TXFE1_EN_ENABLE 0x1 246 247#define TIMPANI_TXFE1_TXFE1_GAIN_S 5 248#define TIMPANI_TXFE1_TXFE1_GAIN_M 0x60 249#define TIMPANI_TXFE1_TXFE1_GAIN_V_0DB 0x0 250#define TIMPANI_TXFE1_TXFE1_GAIN_V_4_5DB 0x1 251#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_1 0x2 252#define TIMPANI_TXFE1_TXFE1_GAIN_V_24DB_2 0x3 253 254#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_S 4 255#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_M 0x10 256#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_NO_CONNECT 0x0 257#define TIMPANI_TXFE1_TXFE1_IN_MIC1_CONN_CONNECT 0x1 258 259#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_S 3 260#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_M 0x8 261#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_NO_CONNECT 0x0 262#define TIMPANI_TXFE1_TXFE1_IN_MIC2_CONN_CONNECT 0x1 263 264#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_S 2 265#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_M 0x4 266#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_NO_CONNECT 0x0 267#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_L_CONN_CONNECT 0x1 268 269#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_S 1 270#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_M 0x2 271#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_NO_CONNECT 0x0 272#define TIMPANI_TXFE1_TXFE1_IN_LINE_I_R_CONN_CONNECT 0x1 273 274#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_S 0 275#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_M 0x1 276#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_NO_CONNECT 0x0 277#define TIMPANI_TXFE1_TXFE1_IN_AUXI_CONN_CONNECT 0x1 278 279 280/* -- For TXFE2 */ 281#define TIMPANI_A_TXFE2 (0xE) 282#define TIMPANI_TXFE2_RWC "RW" 283#define TIMPANI_TXFE2_POR 0 284#define TIMPANI_TXFE2_S 0 285#define TIMPANI_TXFE2_M 0xFF 286 287 288#define TIMPANI_TXFE2_TXFE2_EN_S 7 289#define TIMPANI_TXFE2_TXFE2_EN_M 0x80 290#define TIMPANI_TXFE2_TXFE2_EN_DISABLE 0x0 291#define TIMPANI_TXFE2_TXFE2_EN_ENABLE 0x1 292 293#define TIMPANI_TXFE2_TXFE2_GAIN_S 5 294#define TIMPANI_TXFE2_TXFE2_GAIN_M 0x60 295#define TIMPANI_TXFE2_TXFE2_GAIN_V_0DB 0x0 296#define TIMPANI_TXFE2_TXFE2_GAIN_V_4_5DB 0x1 297#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_1 0x2 298#define TIMPANI_TXFE2_TXFE2_GAIN_V_24DB_2 0x3 299 300#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_S 4 301#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_M 0x10 302#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_NO_CONNECT 0x0 303#define TIMPANI_TXFE2_TXFE2_IN_MIC1_CONN_CONNECT 0x1 304 305#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_S 3 306#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_M 0x8 307#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_NO_CONNECT 0x0 308#define TIMPANI_TXFE2_TXFE2_IN_MIC2_CONN_CONNECT 0x1 309 310#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_S 2 311#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_M 0x4 312#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_NO_CONNECT 0x0 313#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_L_CONN_CONNECT 0x1 314 315#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_S 1 316#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_M 0x2 317#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_NO_CONNECT 0x0 318#define TIMPANI_TXFE2_TXFE2_IN_LINE_I_R_CONN_CONNECT 0x1 319 320#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_S 0 321#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_M 0x1 322#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_NO_CONNECT 0x0 323#define TIMPANI_TXFE2_TXFE2_IN_AUXI_CONN_CONNECT 0x1 324 325 326/* -- For TXFE12_ATEST */ 327#define TIMPANI_A_TXFE12_ATEST (0xF) 328#define TIMPANI_TXFE12_ATEST_RWC "RW" 329#define TIMPANI_TXFE12_ATEST_POR 0 330#define TIMPANI_TXFE12_ATEST_S 0 331#define TIMPANI_TXFE12_ATEST_M 0xFF 332 333 334#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_S 7 335#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_M 0x80 336#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 337#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 338 339#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_S 6 340#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_M 0x40 341#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_DISABLE 0x0 342#define TIMPANI_TXFE12_ATEST_TXFE1_BYPASS_EN_ENABLE 0x1 343 344#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_S 5 345#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_M 0x20 346#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_NO_CONNECT 0x0 347#define TIMPANI_TXFE12_ATEST_TXFE1_CMOUT_ATEST_CONN_CONNECT 0x1 348 349#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_S 4 350#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_M 0x10 351#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_NO_CONNECT 0x0 352#define TIMPANI_TXFE12_ATEST_TXFE1_OUT_ATEST_CONN_CONNECT 0x1 353 354#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_S 3 355#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_M 0x8 356#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 357#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 358 359#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_S 2 360#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_M 0x4 361#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_DISABLE 0x0 362#define TIMPANI_TXFE12_ATEST_TXFE2_BYPASS_EN_ENABLE 0x1 363 364#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_S 1 365#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_M 0x2 366#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_NO_CONNECT 0x0 367#define TIMPANI_TXFE12_ATEST_TXFE2_CMOUT_ATEST_CONN_CONNECT 0x1 368 369#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_S 0 370#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_M 0x1 371#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_NO_CONNECT 0x0 372#define TIMPANI_TXFE12_ATEST_TXFE2_OUT_ATEST_CONN_CONNECT 0x1 373 374 375/* -- For TXFE_CLT */ 376#define TIMPANI_A_TXFE_CLT (0x10) 377#define TIMPANI_TXFE_CLT_RWC "RW" 378#define TIMPANI_TXFE_CLT_POR 0x68 379#define TIMPANI_TXFE_CLT_S 0 380#define TIMPANI_TXFE_CLT_M 0xFF 381 382 383#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_S 5 384#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_M 0xE0 385#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_125V 0x0 386#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_100V 0x1 387#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_075V 0x2 388#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_050V_NORMAL_OP 0x3 389#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_025V 0x4 390#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_1_000V 0x5 391#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_975V 0x6 392#define TIMPANI_TXFE_CLT_TXFE_OUT_CM_VOLT_V_0_950V 0x7 393 394#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_S 3 395#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_M 0x18 396#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_3UA 0x0 397#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_4UA_NORMAL_OP 0x1 398#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_6UA 0x2 399#define TIMPANI_TXFE_CLT_TXFE_BIAS_CUR_V_8UA 0x3 400 401#define TIMPANI_TXFE_CLT_RESERVED_S 0 402#define TIMPANI_TXFE_CLT_RESERVED_M 0x7 403 404 405/* -- For TXADC1_EN */ 406#define TIMPANI_A_TXADC1_EN (0x11) 407#define TIMPANI_TXADC1_EN_RWC "RW" 408#define TIMPANI_TXADC1_EN_POR 0 409#define TIMPANI_TXADC1_EN_S 0 410#define TIMPANI_TXADC1_EN_M 0xFF 411 412 413#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_S 7 414#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_M 0x80 415#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_DISABLE 0x0 416#define TIMPANI_TXADC1_EN_TXADC1_REF_EN_ENABLE 0x1 417 418#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_S 6 419#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_M 0x40 420#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 421#define TIMPANI_TXADC1_EN_TXADC1_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 422 423#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_S 5 424#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_M 0x20 425#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_DISABLE 0x0 426#define TIMPANI_TXADC1_EN_TXADC1_OTA1_EN_ENABLE 0x1 427 428#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_S 4 429#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_M 0x10 430#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_DISABLE 0x0 431#define TIMPANI_TXADC1_EN_TXADC1_OTA2_EN_ENABLE 0x1 432 433#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_S 3 434#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_M 0x8 435#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_DISABLE 0x0 436#define TIMPANI_TXADC1_EN_TXADC1_COMP_EN_ENABLE 0x1 437 438#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_S 2 439#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_M 0x4 440#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_DISABLE 0x0 441#define TIMPANI_TXADC1_EN_TXADC1_DEM_EN_ENABLE 0x1 442 443#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_S 1 444#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_M 0x2 445#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_DISABLE 0x0 446#define TIMPANI_TXADC1_EN_TXADC1_DEM_ERROR_DET_EN_ENABLE 0x1 447 448#define TIMPANI_TXADC1_EN_RESERVED_S 0 449#define TIMPANI_TXADC1_EN_RESERVED_M 0x1 450 451 452/* -- For TXADC2_EN */ 453#define TIMPANI_A_TXADC2_EN (0x12) 454#define TIMPANI_TXADC2_EN_RWC "RW" 455#define TIMPANI_TXADC2_EN_POR 0 456#define TIMPANI_TXADC2_EN_S 0 457#define TIMPANI_TXADC2_EN_M 0xFF 458 459 460#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_S 7 461#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_M 0x80 462#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_DISABLE 0x0 463#define TIMPANI_TXADC2_EN_TXADC2_REF_EN_ENABLE 0x1 464 465#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_S 6 466#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_M 0x40 467#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_DISABLE 0x0 468#define TIMPANI_TXADC2_EN_TXADC2_DAC_REF_CUR_COMPENSATION_EN_ENABLE 0x1 469 470#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_S 5 471#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_M 0x20 472#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_DISABLE 0x0 473#define TIMPANI_TXADC2_EN_TXADC2_OTA1_EN_ENABLE 0x1 474 475#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_S 4 476#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_M 0x10 477#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_DISABLE 0x0 478#define TIMPANI_TXADC2_EN_TXADC2_OTA2_EN_ENABLE 0x1 479 480#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_S 3 481#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_M 0x8 482#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_DISABLE 0x0 483#define TIMPANI_TXADC2_EN_TXADC2_COMP_EN_ENABLE 0x1 484 485#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_S 2 486#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_M 0x4 487#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_DISABLE 0x0 488#define TIMPANI_TXADC2_EN_TXADC2_DEM_EN_ENABLE 0x1 489 490#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_S 1 491#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_M 0x2 492#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_DISABLE 0x0 493#define TIMPANI_TXADC2_EN_TXADC2_DEM_ERROR_DET_EN_ENABLE 0x1 494 495#define TIMPANI_TXADC2_EN_RESERVED_S 0 496#define TIMPANI_TXADC2_EN_RESERVED_M 0x1 497 498 499/* -- For TXADC_CTL */ 500#define TIMPANI_A_TXADC_CTL (0x13) 501#define TIMPANI_TXADC_CTL_RWC "RW" 502#define TIMPANI_TXADC_CTL_POR 0x58 503#define TIMPANI_TXADC_CTL_S 0 504#define TIMPANI_TXADC_CTL_M 0xFF 505 506 507#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_S 6 508#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_M 0xC0 509#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_5UA 0x0 510#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_10UA_NORMAL_OP 0x1 511#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_15UA 0x2 512#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_DDA_AMP_BIAS_CUR_V_20UA 0x3 513 514#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_S 4 515#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_M 0x30 516#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_40UA 0x0 517#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_80UA 0x1 518#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_120UA 0x2 519#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_SRC_FOLLOWER_BIAS_CUR_V_160UA 0x3 520 521#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_S 2 522#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_M 0xC 523#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_8V 0x0 524#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_7V 0x1 525#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_6V_NORMAL_OP 0x2 526#define TIMPANI_TXADC_CTL_TXADC_DAC_REF_VOLT_V_1_5V 0x3 527 528#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_S 0 529#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_M 0x3 530#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_20UA_NORMAL_OP 0x0 531#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_40UA 0x1 532#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_80UA 0x2 533#define TIMPANI_TXADC_CTL_TXADC_VREFMID_BIAS_CUR_V_160UA 0x3 534 535 536/* -- For TXADC_CTL2 */ 537#define TIMPANI_A_TXADC_CTL2 (0x14) 538#define TIMPANI_TXADC_CTL2_RWC "RW" 539#define TIMPANI_TXADC_CTL2_POR 0x64 540#define TIMPANI_TXADC_CTL2_S 0 541#define TIMPANI_TXADC_CTL2_M 0xFF 542 543 544#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_S 6 545#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_M 0xC0 546#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_333MV 0x0 547#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_356MV_NORMAL_OP 0x1 548#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_378MV 0x2 549#define TIMPANI_TXADC_CTL2_TXADC_COMP_THRESH_VOLT_V_400MV 0x3 550 551#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_S 4 552#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_M 0x30 553#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_50UA 0x0 554#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_100UA 0x1 555#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_200UA_NORMAL_OP 0x2 556#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_BIAS_CUR_V_400UA 0x3 557 558#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_S 2 559#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_M 0xC 560#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_1V 0x0 561#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_15V_NORMAL_OP 0x1 562#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_2V 0x2 563#define TIMPANI_TXADC_CTL2_TXADC_VICM_REF_BUFF_OUT_VOLT_V_1_25V 0x3 564 565#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_S 1 566#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_M 0x2 567#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_50UA_NORMAL_OP 0x0 568#define TIMPANI_TXADC_CTL2_TXADC_VOCM_BUFFER_BIAS_CUR_V_100UA 0x1 569 570#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_S 0 571#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_M 0x1 572#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_DISABLE 0x0 573#define TIMPANI_TXADC_CTL2_TXADC_DIG_OUT_EN_ENABLE_NORMAL_OP 0x1 574 575 576/* -- For TXADC_CTL3 */ 577#define TIMPANI_A_TXADC_CTL3 (0x15) 578#define TIMPANI_TXADC_CTL3_RWC "RW" 579#define TIMPANI_TXADC_CTL3_POR 0x64 580#define TIMPANI_TXADC_CTL3_S 0 581#define TIMPANI_TXADC_CTL3_M 0xFF 582 583 584#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_S 6 585#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_M 0xC0 586#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_85V 0x0 587#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_90V_NORMAL_OP 0x1 588#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_0_95V 0x2 589#define TIMPANI_TXADC_CTL3_TXADC_VOCM_REF_BUFF_VOLT_V_1_00V 0x3 590 591#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_S 4 592#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_M 0x30 593#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_10UA 0x0 594#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_15UA 0x1 595#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_20UA_NORMAL_OP 0x2 596#define TIMPANI_TXADC_CTL3_TXADC_OTA1_BIAS_CUR_V_25UA 0x3 597 598#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_S 2 599#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_M 0xC 600#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_5UA 0x0 601#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_10UA_NORMAL_OP 0x1 602#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_15UA 0x2 603#define TIMPANI_TXADC_CTL3_TXADC_OTA2_BIAS_CUR_V_20UA 0x3 604 605#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_S 1 606#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_M 0x2 607#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_5UA_NORMAL_OP 0x0 608#define TIMPANI_TXADC_CTL3_TXADC_COMP_BIAS_CUR_V_10UA 0x1 609 610#define TIMPANI_TXADC_CTL3_RESERVED_S 0 611#define TIMPANI_TXADC_CTL3_RESERVED_M 0x1 612 613 614/* -- For TXADC_CHOP_CTL */ 615#define TIMPANI_A_TXADC_CHOP_CTL (0x16) 616#define TIMPANI_TXADC_CHOP_CTL_RWC "RW" 617#define TIMPANI_TXADC_CHOP_CTL_POR 0 618#define TIMPANI_TXADC_CHOP_CTL_S 0 619#define TIMPANI_TXADC_CHOP_CTL_M 0xFF 620 621 622#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_S 7 623#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_M 0x80 624#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_DISABLE 0x0 625#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_EN_ENABLE 0x1 626 627#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_S 4 628#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_M 0x70 629#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_2_NORMAL_OP 0x0 630#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_4 0x1 631#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_8 0x2 632#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_16 0x3 633#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_32 0x4 634#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_64 0x5 635#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_128 0x6 636#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_DIV_RATIO_V_256 0x7 637 638#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_S 3 639#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_M 0x8 640#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_NORMAL_OP 0x0 641#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_STATE_RESET_RESET_CHOP 0x1 642 643#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_S 2 644#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_M 0x4 645#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK1 0x0 646#define TIMPANI_TXADC_CHOP_CTL_TXADC_CHOP_CLK_PHASE_SEL_FALLING_EDGE_CK2 0x1 647 648#define TIMPANI_TXADC_CHOP_CTL_RESERVED_S 0 649#define TIMPANI_TXADC_CHOP_CTL_RESERVED_M 0x3 650 651 652/* -- For TXFE3 */ 653#define TIMPANI_A_TXFE3 (0x18) 654#define TIMPANI_TXFE3_RWC "RW" 655#define TIMPANI_TXFE3_POR 0 656#define TIMPANI_TXFE3_S 0 657#define TIMPANI_TXFE3_M 0xFF 658 659 660#define TIMPANI_TXFE3_TXFE3_EN_S 7 661#define TIMPANI_TXFE3_TXFE3_EN_M 0x80 662#define TIMPANI_TXFE3_TXFE3_EN_DISABLE 0x0 663#define TIMPANI_TXFE3_TXFE3_EN_ENABLE 0x1 664 665#define TIMPANI_TXFE3_TXFE3_GAIN_S 5 666#define TIMPANI_TXFE3_TXFE3_GAIN_M 0x60 667#define TIMPANI_TXFE3_TXFE3_GAIN_V_0DB 0x0 668#define TIMPANI_TXFE3_TXFE3_GAIN_V_4_5DB 0x1 669#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_1 0x2 670#define TIMPANI_TXFE3_TXFE3_GAIN_V_24DB_2 0x3 671 672#define TIMPANI_TXFE3_RESERVED_1_S 2 673#define TIMPANI_TXFE3_RESERVED_1_M 0x1C 674 675#define TIMPANI_TXFE3_TXFE3_IN_CONN_S 1 676#define TIMPANI_TXFE3_TXFE3_IN_CONN_M 0x2 677#define TIMPANI_TXFE3_TXFE3_IN_CONN_NO_CONNECT 0x0 678#define TIMPANI_TXFE3_TXFE3_IN_CONN_LINE_IN_L 0x1 679 680#define TIMPANI_TXFE3_RESERVED_2_S 0 681#define TIMPANI_TXFE3_RESERVED_2_M 0x1 682 683 684/* -- For TXFE4 */ 685#define TIMPANI_A_TXFE4 (0x19) 686#define TIMPANI_TXFE4_RWC "RW" 687#define TIMPANI_TXFE4_POR 0 688#define TIMPANI_TXFE4_S 0 689#define TIMPANI_TXFE4_M 0xFF 690 691 692#define TIMPANI_TXFE4_TXFE4_EN_S 7 693#define TIMPANI_TXFE4_TXFE4_EN_M 0x80 694#define TIMPANI_TXFE4_TXFE4_EN_DISABLE 0x0 695#define TIMPANI_TXFE4_TXFE4_EN_ENABLE 0x1 696 697#define TIMPANI_TXFE4_TXFE4_GAIN_S 5 698#define TIMPANI_TXFE4_TXFE4_GAIN_M 0x60 699#define TIMPANI_TXFE4_TXFE4_GAIN_V_0DB 0x0 700#define TIMPANI_TXFE4_TXFE4_GAIN_V_4_5DB 0x1 701#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_1 0x2 702#define TIMPANI_TXFE4_TXFE4_GAIN_V_24DB_2 0x3 703 704#define TIMPANI_TXFE4_RESERVED_1_S 2 705#define TIMPANI_TXFE4_RESERVED_1_M 0x1C 706 707#define TIMPANI_TXFE4_TXFE4_IN_CONN_S 1 708#define TIMPANI_TXFE4_TXFE4_IN_CONN_M 0x2 709#define TIMPANI_TXFE4_TXFE4_IN_CONN_NO_CONNECT 0x0 710#define TIMPANI_TXFE4_TXFE4_IN_CONN_LINE_IN_R 0x1 711 712#define TIMPANI_TXFE4_RESERVED_2_S 0 713#define TIMPANI_TXFE4_RESERVED_2_M 0x1 714 715 716/* -- For TXFE3_ATEST */ 717#define TIMPANI_A_TXFE3_ATEST (0x1A) 718#define TIMPANI_TXFE3_ATEST_RWC "RW" 719#define TIMPANI_TXFE3_ATEST_POR 0 720#define TIMPANI_TXFE3_ATEST_S 0 721#define TIMPANI_TXFE3_ATEST_M 0xFF 722 723 724#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_S 7 725#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_M 0x80 726#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 727#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 728 729#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_S 6 730#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_M 0x40 731#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_DISABLE 0x0 732#define TIMPANI_TXFE3_ATEST_TXFE3_BYPASS_EN_ENABLE 0x1 733 734#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_S 5 735#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_M 0x20 736#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_NO_CONNECT 0x0 737#define TIMPANI_TXFE3_ATEST_TXFE3_CMOUT_ATEST_CONN_CONNECT 0x1 738 739#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_S 4 740#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_M 0x10 741#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_NO_CONNECT 0x0 742#define TIMPANI_TXFE3_ATEST_TXFE3_OUT_ATEST_CONN_CONNECT 0x1 743 744#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_S 3 745#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_M 0x8 746#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_DISABLE 0x0 747#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_SHORT_TO_VICM_EN_ENABLE 0x1 748 749#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_S 2 750#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_M 0x4 751#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_DISABLE 0x0 752#define TIMPANI_TXFE3_ATEST_TXFE4_BYPASS_EN_ENABLE 0x1 753 754#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_S 1 755#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_M 0x2 756#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_NO_CONNECT 0x0 757#define TIMPANI_TXFE3_ATEST_TXFE4_CMOUT_ATEST_CONN_CONNECT 0x1 758 759#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_S 0 760#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_M 0x1 761#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_NO_CONNECT 0x0 762#define TIMPANI_TXFE3_ATEST_TXFE4_OUT_ATEST_CONN_CONNECT 0x1 763 764 765/* -- For TXFE_DIFF_SE */ 766#define TIMPANI_A_TXFE_DIFF_SE (0x1B) 767#define TIMPANI_TXFE_DIFF_SE_RWC "RW" 768#define TIMPANI_TXFE_DIFF_SE_POR 0 769#define TIMPANI_TXFE_DIFF_SE_S 0 770#define TIMPANI_TXFE_DIFF_SE_M 0xFF 771 772 773#define TIMPANI_TXFE_DIFF_SE_RESERVED_S 4 774#define TIMPANI_TXFE_DIFF_SE_RESERVED_M 0xF0 775 776#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_S 3 777#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_M 0x8 778#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_DIFF 0x0 779#define TIMPANI_TXFE_DIFF_SE_TXADC1_IN_MODE_SINGLE_ENDED 0x1 780 781#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_S 2 782#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_M 0x4 783#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_DIFF 0x0 784#define TIMPANI_TXFE_DIFF_SE_TXADC2_IN_MODE_SINGLE_ENDED 0x1 785 786#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_S 1 787#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_M 0x2 788#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_DIFF 0x0 789#define TIMPANI_TXFE_DIFF_SE_TXADC3_IN_MODE_SINGLE_ENDED 0x1 790 791#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_S 0 792#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_M 0x1 793#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_DIFF 0x0 794#define TIMPANI_TXFE_DIFF_SE_TXADC4_IN_MODE_SINGLE_ENDED 0x1 795 796 797/* -- For CDAC_RX_CLK_CTL */ 798#define TIMPANI_A_CDAC_RX_CLK_CTL (0x20) 799#define TIMPANI_CDAC_RX_CLK_CTL_RWC "RW" 800#define TIMPANI_CDAC_RX_CLK_CTL_POR 0x98 801#define TIMPANI_CDAC_RX_CLK_CTL_S 0 802#define TIMPANI_CDAC_RX_CLK_CTL_M 0xFF 803 804 805#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_S 7 806#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_M 0x80 807#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_DISABLE 0x0 808#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_EN_ENABLE_NORMAL_OP 0x1 809 810#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_S 6 811#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_M 0x40 812#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_DISABLE_NORMAL_OP 0x0 813#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_CTRL_EN_ENABLE 0x1 814 815#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_S 2 816#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_M 0x3C 817#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_6NS 0x0 818#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_8_4NS 0x1 819#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_10_8NS 0x2 820#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_13_2NS 0x3 821#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_15_6NS 0x4 822#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_18NS 0x5 823#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_20_4NS_NORMAL_OP 0x6 824#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_22_8NS 0x7 825#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_25_2NS 0x8 826#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_27_6NS 0x9 827#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_30NS 0xA 828#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_32_4NS 0xB 829#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_34_8NS 0xC 830#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_37_2NS 0xD 831#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_39_6NS 0xE 832#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_EXTERNAL_DELAY_V_42NS 0xF 833 834#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_S 1 835#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_M 0x2 836#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_ENABLE 0x1 837#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_FF_RESET_DISABLE 0x0 838 839#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_S 0 840#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_M 0x1 841#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_NO_CONNECT 0x0 842#define TIMPANI_CDAC_RX_CLK_CTL_CDAC_RESET_PULSE_GEN_ATEST_CONN_CONNECT 0x1 843 844 845/* -- For CDAC_BUFF_CTL */ 846#define TIMPANI_A_CDAC_BUFF_CTL (0x21) 847#define TIMPANI_CDAC_BUFF_CTL_RWC "RW" 848#define TIMPANI_CDAC_BUFF_CTL_POR 0x60 849#define TIMPANI_CDAC_BUFF_CTL_S 0 850#define TIMPANI_CDAC_BUFF_CTL_M 0xFF 851 852 853#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_S 5 854#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_M 0xE0 855#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_40UA 0x0 856#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_60UA_NORMAL_OP 0x1 857#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_80UA 0x2 858#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_100UA 0x3 859#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_120UA 0x4 860#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_140UA 0x5 861#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_160UA 0x6 862#define TIMPANI_CDAC_BUFF_CTL_CDAC_DM_BUFF_CUR_V_180UA 0x7 863 864#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_S 3 865#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_M 0x18 866#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_20UA 0x0 867#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_30UA_NORMAL_OP 0x1 868#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_40UA 0x2 869#define TIMPANI_CDAC_BUFF_CTL_CDAC_CM_BUFF_CUR_V_50UA 0x3 870 871#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_S 1 872#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_M 0x6 873#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_5UA 0x0 874#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_5UA_10UA 0x1 875#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_5UA 0x2 876#define TIMPANI_CDAC_BUFF_CTL_CDAC_REF_BUFF_OTA_BIAS_CUR_V_10UA_10UA 0x3 877 878#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_S 0 879#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_M 0x1 880#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_CURRENT_TO_VCOM_NORMAL_OP 0x0 881#define TIMPANI_CDAC_BUFF_CTL_CDAC_VCOM_SOURCE_MASTER_BIAS_TO_VCOM 0x1 882 883 884/* -- For CDAC_REF_CTL1 */ 885#define TIMPANI_A_CDAC_REF_CTL1 (0x22) 886#define TIMPANI_CDAC_REF_CTL1_RWC "RW" 887#define TIMPANI_CDAC_REF_CTL1_POR 0xe1 888#define TIMPANI_CDAC_REF_CTL1_S 0 889#define TIMPANI_CDAC_REF_CTL1_M 0xFF 890 891 892#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_S 5 893#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_M 0xE0 894#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_8V 0x0 895#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_825V 0x1 896#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_85V 0x2 897#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_9V 0x3 898#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_925V 0x4 899#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_95V_NORMAL_OP 0x5 900#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_1_975 0x6 901#define TIMPANI_CDAC_REF_CTL1_CDAC_DACH_VOLT_V_2_0V 0x7 902 903#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_S 2 904#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_M 0x1C 905#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_1V 0x0 906#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_125V 0x1 907#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_15V_NORMAL_OP 0x2 908#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_175V 0x3 909#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_2V 0x4 910#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_25V 0x5 911#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_275V 0x6 912#define TIMPANI_CDAC_REF_CTL1_CDAC_DACL_VOLT_V_0_3V 0x7 913 914#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_S 0 915#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_M 0x3 916#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_025V 0x0 917#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_05V_NORMAL_OP 0x1 918#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_075V 0x2 919#define TIMPANI_CDAC_REF_CTL1_CDAC_CM_VOLT_V_1_1V 0x3 920 921 922/* -- For IDAC_DWA_FIR_CTL */ 923#define TIMPANI_A_IDAC_DWA_FIR_CTL (0x23) 924#define TIMPANI_IDAC_DWA_FIR_CTL_RWC "RW" 925#define TIMPANI_IDAC_DWA_FIR_CTL_POR 0x28 926#define TIMPANI_IDAC_DWA_FIR_CTL_S 0 927#define TIMPANI_IDAC_DWA_FIR_CTL_M 0xFF 928 929 930#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_S 7 931#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_M 0x80 932#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_NORMAL_OP 0x0 933#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_CLK_NON_OL_TIME_V_150PSEC_REDUCTION 0x1 934 935#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_S 4 936#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_M 0x70 937#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR0 0x0 938#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR1 0x1 939#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR2 0x2 940#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR3 0x3 941#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_FIR_FIR4 0x4 942 943#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_S 3 944#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_M 0x8 945#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_INTERNAL_NORMAL_OP 0x1 946#define TIMPANI_IDAC_DWA_FIR_CTL_IDAC_EN_SOURCE_EXTERNAL 0x0 947 948#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_S 0 949#define TIMPANI_IDAC_DWA_FIR_CTL_RESERVED_M 0x7 950 951 952/* -- For CDAC_REF_CTL2 */ 953#define TIMPANI_A_CDAC_REF_CTL2 (0x24) 954#define TIMPANI_CDAC_REF_CTL2_RWC "RW" 955#define TIMPANI_CDAC_REF_CTL2_POR 0xc 956#define TIMPANI_CDAC_REF_CTL2_S 0 957#define TIMPANI_CDAC_REF_CTL2_M 0xFF 958 959 960#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_S 7 961#define TIMPANI_CDAC_REF_CTL2_RESERVED_1_M 0x80 962 963#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_S 6 964#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_M 0x40 965#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_DISABLE 0x0 966#define TIMPANI_CDAC_REF_CTL2_CDAC_L_EN_ENABLE 0x1 967 968#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_S 5 969#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_M 0x20 970#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_DISABLE 0x0 971#define TIMPANI_CDAC_REF_CTL2_CDAC_R_EN_ENABLE 0x1 972 973#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_S 4 974#define TIMPANI_CDAC_REF_CTL2_RESERVED_2_M 0x10 975 976#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_S 2 977#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_M 0xC 978#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK11DBAR 0x1 979#define TIMPANI_CDAC_REF_CTL2_CDAC_DWA_RX_FILTER_TIMING_CLK_SYNC_CK21 0x3 980 981#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_S 0 982#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_M 0x3 983#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_256 0x0 984#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_128 0x1 985#define TIMPANI_CDAC_REF_CTL2_CDAC_OSR_V_64 0x3 986 987 988/* -- For CDAC_CTL1 */ 989#define TIMPANI_A_CDAC_CTL1 (0x25) 990#define TIMPANI_CDAC_CTL1_RWC "RW" 991#define TIMPANI_CDAC_CTL1_POR 0xb 992#define TIMPANI_CDAC_CTL1_S 0 993#define TIMPANI_CDAC_CTL1_M 0xFF 994 995 996#define TIMPANI_CDAC_CTL1_RESERVED_S 6 997#define TIMPANI_CDAC_CTL1_RESERVED_M 0xC0 998 999#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_S 5 1000#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_M 0x20 1001#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_DISABLE 0x0 1002#define TIMPANI_CDAC_CTL1_CDAC_L_OUT_SHORT_EN_ENABLE 0x1 1003 1004#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_S 4 1005#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_M 0x10 1006#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_DISABLE 0x0 1007#define TIMPANI_CDAC_CTL1_CDAC_R_OUT_SHORT_EN_ENABLE 0x1 1008 1009#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_S 2 1010#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_M 0xC 1011#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0V 0x0 1012#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_025V 0x1 1013#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_05V_NORMAL_OP 0x2 1014#define TIMPANI_CDAC_CTL1_CDAC_REF_RESISTOR_VOLT_V_1_0752V 0x3 1015 1016#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_S 1 1017#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_M 0x2 1018#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_DISABLE 0x0 1019#define TIMPANI_CDAC_CTL1_CDAC_SAMP_CAP_RESET_EN_ENABLE_NORMAL_OP 0x1 1020 1021#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_S 0 1022#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_M 0x1 1023#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_INTERNAL_NORMAL_OP 0x1 1024#define TIMPANI_CDAC_CTL1_CDAC_RESET_SOURCE_EXTERNAL_REGISTER_RESET 0x0 1025 1026 1027/* -- For CDAC_CTL2 */ 1028#define TIMPANI_A_CDAC_CTL2 (0x26) 1029#define TIMPANI_CDAC_CTL2_RWC "RW" 1030#define TIMPANI_CDAC_CTL2_POR 0xd0 1031#define TIMPANI_CDAC_CTL2_S 0 1032#define TIMPANI_CDAC_CTL2_M 0xFF 1033 1034 1035#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_S 5 1036#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_M 0xE0 1037#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_10UA 0x0 1038#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_8_75UA 0x1 1039#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_7_5UA 0x2 1040#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_6_25UA 0x3 1041#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_5UA 0x4 1042#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_3_75UA 0x5 1043#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_2_5UA_NORMAL_OP 0x6 1044#define TIMPANI_CDAC_CTL2_CDAC_OTA_BIAS_V_1_25UA 0x7 1045 1046#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_S 2 1047#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_M 0x1C 1048#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_10UA 0x0 1049#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_8_75UA 0x1 1050#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_7_5UA 0x2 1051#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_6_25UA 0x3 1052#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_5UA_NORMAL_OP 0x4 1053#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_3_75UA 0x5 1054#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_2_5UA 0x6 1055#define TIMPANI_CDAC_CTL2_CDAC_REF_BUFF_OTA_BIAS_V_1_25UA 0x7 1056 1057#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_S 0 1058#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_M 0x3 1059#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS 0x0 1060#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_8 0x1 1061#define TIMPANI_CDAC_CTL2_CDAC_RESET_PULSE_GEN_UPDATE_RATE_FS_BY_16 0x2 1062 1063 1064/* -- For IDAC_L_CTL */ 1065#define TIMPANI_A_IDAC_L_CTL (0x28) 1066#define TIMPANI_IDAC_L_CTL_RWC "RW" 1067#define TIMPANI_IDAC_L_CTL_POR 0xe 1068#define TIMPANI_IDAC_L_CTL_S 0 1069#define TIMPANI_IDAC_L_CTL_M 0xFF 1070 1071 1072#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_S 7 1073#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_M 0x80 1074#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_DISABLE 0x0 1075#define TIMPANI_IDAC_L_CTL_IDAC_L_EN_ENABLE 0x1 1076 1077#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_S 5 1078#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_M 0x60 1079#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_GROUND 0x0 1080#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_IBIAS_X_R_REF 0x1 1081#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2 1082#define TIMPANI_IDAC_L_CTL_IDAC_L_REF_SEL_VDD_BY_2 0x3 1083 1084#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_S 3 1085#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_M 0x18 1086#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_NEG_1_5DB 0x0 1087#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_V_0_0DB_NORMAL_OP 0x1 1088#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_1_5DB 0x2 1089#define TIMPANI_IDAC_L_CTL_IDAC_L_GAIN_POS_3_0DB 0x3 1090 1091#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_S 2 1092#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_M 0x4 1093#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_30K 0x0 1094#define TIMPANI_IDAC_L_CTL_IDAC_L_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1 1095 1096#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_S 1 1097#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_M 0x2 1098#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ASYNCHRONOUSLY 0x0 1099#define TIMPANI_IDAC_L_CTL_IDAC_L_SYNC_EN_ENABLE_NORMAL_OP 0x1 1100 1101#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_S 0 1102#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_M 0x1 1103#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0 1104#define TIMPANI_IDAC_L_CTL_IDAC_L_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1 1105 1106 1107/* -- For IDAC_R_CTL */ 1108#define TIMPANI_A_IDAC_R_CTL (0x29) 1109#define TIMPANI_IDAC_R_CTL_RWC "RW" 1110#define TIMPANI_IDAC_R_CTL_POR 0xe 1111#define TIMPANI_IDAC_R_CTL_S 0 1112#define TIMPANI_IDAC_R_CTL_M 0xFF 1113 1114 1115#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_S 7 1116#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_M 0x80 1117#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_DISABLED 0x0 1118#define TIMPANI_IDAC_R_CTL_IDAC_R_EN_ENABLED 0x1 1119 1120#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_S 5 1121#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_M 0x60 1122#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_GROUND 0x0 1123#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_IBIAS_X_R_REF 0x1 1124#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_BG_VOLTAGE_NORMAL_OP 0x2 1125#define TIMPANI_IDAC_R_CTL_IDAC_R_REF_SEL_VDD_BY_2 0x3 1126 1127#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_S 3 1128#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_M 0x18 1129#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_NEG_1_5DB 0x0 1130#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_V_0_0DB_NORMAL_OP 0x1 1131#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_1_5DB 0x2 1132#define TIMPANI_IDAC_R_CTL_IDAC_R_GAIN_POS_3_0DB 0x3 1133 1134#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_S 2 1135#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_M 0x4 1136#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_30K 0x0 1137#define TIMPANI_IDAC_R_CTL_IDAC_R_LOW_RESISTANCE_V_10K_NORMAL_OP 0x1 1138 1139#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_S 1 1140#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_M 0x2 1141#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ASYNCHRONOUSLY 0x0 1142#define TIMPANI_IDAC_R_CTL_IDAC_R_SYNC_EN_ENABLE_NORMAL_OP 0x1 1143 1144#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_S 0 1145#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_M 0x1 1146#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_REPLICA_BIAS_NORMAL_OP 0x0 1147#define TIMPANI_IDAC_R_CTL_IDAC_R_REPLICA_BIAS_SERVO_LOOP_BIAS 0x1 1148 1149 1150/* -- For PA_MASTER_BIAS */ 1151#define TIMPANI_A_PA_MASTER_BIAS (0x2D) 1152#define TIMPANI_PA_MASTER_BIAS_RWC "RW" 1153#define TIMPANI_PA_MASTER_BIAS_POR 0x6f 1154#define TIMPANI_PA_MASTER_BIAS_S 0 1155#define TIMPANI_PA_MASTER_BIAS_M 0xFF 1156 1157 1158#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_S 5 1159#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_M 0xE0 1160#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_17_5UA 0x0 1161#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_15_0UA 0x1 1162#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_12_5UA 0x2 1163#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_10_0UA 0x3 1164#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_7_5UA 0x4 1165#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_5_0UA 0x5 1166#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_2_5UA 0x6 1167#define TIMPANI_PA_MASTER_BIAS_LINE_MASTER_BIAS_CUR_V_0_0UA 0x7 1168 1169#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_S 2 1170#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_M 0x1C 1171#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_17_5UA 0x0 1172#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_15_0UA 0x1 1173#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_12_5UA 0x2 1174#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_10_0UA 0x3 1175#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_7_5UA 0x4 1176#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_5_0UA 0x5 1177#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_2_5UA 0x6 1178#define TIMPANI_PA_MASTER_BIAS_HPH_MASTER_BIAS_CUR_V_0_0UA 0x7 1179 1180#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_S 0 1181#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_M 0x3 1182#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_6_25UA 0x0 1183#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_5_0UA 0x1 1184#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_3_75UA 0x2 1185#define TIMPANI_PA_MASTER_BIAS_CLASSD_REF_BUF_MASTER_BIAS_CUR_V_2_5UA 0x3 1186 1187 1188/* -- For PA_CLASSD_BIAS */ 1189#define TIMPANI_A_PA_CLASSD_BIAS (0x2E) 1190#define TIMPANI_PA_CLASSD_BIAS_RWC "RW" 1191#define TIMPANI_PA_CLASSD_BIAS_POR 0x55 1192#define TIMPANI_PA_CLASSD_BIAS_S 0 1193#define TIMPANI_PA_CLASSD_BIAS_M 0xFF 1194 1195 1196#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_S 6 1197#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_M 0xC0 1198#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_6_25UA 0x0 1199#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_5_0UA 0x1 1200#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_3_75UA 0x2 1201#define TIMPANI_PA_CLASSD_BIAS_CLASSD_COMP_BIAS_CUR_V_2_5UA 0x3 1202 1203#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_S 4 1204#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_M 0x30 1205#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_6_25UA 0x0 1206#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_5_0U 0x1 1207#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_3_75UA 0x2 1208#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA1_BIAS_CUR_V_2_5UA 0x3 1209 1210#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_S 2 1211#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_M 0xC 1212#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_6_25UA 0x0 1213#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_5_0UA 0x1 1214#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_3_75UA 0x2 1215#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OTA2_BIAS_CUR_V_2_5UA 0x3 1216 1217#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_S 0 1218#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_M 0x3 1219#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_6_25UA 0x0 1220#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_5_0UA 0x1 1221#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_3_75UA 0x2 1222#define TIMPANI_PA_CLASSD_BIAS_CLASSD_OCP_BIAS_CUR_V_2_5UA 0x3 1223 1224 1225/* -- For AUXPGA_CUR */ 1226#define TIMPANI_A_AUXPGA_CUR (0x2F) 1227#define TIMPANI_AUXPGA_CUR_RWC "RW" 1228#define TIMPANI_AUXPGA_CUR_POR 0x44 1229#define TIMPANI_AUXPGA_CUR_S 0 1230#define TIMPANI_AUXPGA_CUR_M 0xFF 1231 1232 1233#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_S 4 1234#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_M 0xF0 1235#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0UA 0x0 1236#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_3125UA 0x1 1237#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_625UA 0x2 1238#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_0_9375UA 0x3 1239#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_25UA 0x4 1240#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_5625UA 0x5 1241#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_1_875UA 0x6 1242#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_1875UA 0x7 1243#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_5UA 0x8 1244#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_2_8125UA 0x9 1245#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_125UA 0xA 1246#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_4375UA 0xB 1247#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_3_75UA 0xC 1248#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_0625UA 0xD 1249#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_375UA 0xE 1250#define TIMPANI_AUXPGA_CUR_AUXPGA_PMOSAB_CUR_V_4_6875UA 0xF 1251 1252#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_S 0 1253#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_M 0xF 1254#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0UA 0x0 1255#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_3125UA 0x1 1256#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_625UA 0x2 1257#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_0_9375UA 0x3 1258#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_25UA 0x4 1259#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_5625UA 0x5 1260#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_1_875UA 0x6 1261#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_1875UA 0x7 1262#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_5UA 0x8 1263#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_2_8125UA 0x9 1264#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_125UA 0xA 1265#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_4375UA 0xB 1266#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_3_75UA 0xC 1267#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_0625UA 0xD 1268#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_375UA 0xE 1269#define TIMPANI_AUXPGA_CUR_AUXPGA_NMOSAB_CUR_V_4_6875UA 0xF 1270 1271 1272/* -- For AUXPGA_CM */ 1273#define TIMPANI_A_AUXPGA_CM (0x30) 1274#define TIMPANI_AUXPGA_CM_RWC "RW" 1275#define TIMPANI_AUXPGA_CM_POR 0x92 1276#define TIMPANI_AUXPGA_CM_S 0 1277#define TIMPANI_AUXPGA_CM_M 0xFF 1278 1279 1280#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_S 5 1281#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_M 0xE0 1282#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0 1283#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1 1284#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2 1285#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3 1286#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4 1287#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5 1288#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6 1289#define TIMPANI_AUXPGA_CM_AUXPGA_R_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7 1290 1291#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_S 2 1292#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_M 0x1C 1293#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_5UA 0x0 1294#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_7_925UA 0x1 1295#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_8_75UA 0x2 1296#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_9_375UA 0x3 1297#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10UA 0x4 1298#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_10_625UA 0x5 1299#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_25UA 0x6 1300#define TIMPANI_AUXPGA_CM_AUXPGA_L_CM_DIFF_PAIR_TAIL_CUR_V_11_875UA 0x7 1301 1302#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_S 1 1303#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_M 0x2 1304#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_VCMI_TO_R2R_CM 0x1 1305#define TIMPANI_AUXPGA_CM_AUXPGA_R2R_CM_R2R_CM_FLOATING 0x0 1306 1307#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_S 0 1308#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_M 0x1 1309#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_GEN_VCM_LOCALLY 0x1 1310#define TIMPANI_AUXPGA_CM_AUXPGA_VCM_REF_GEN_BG_VCM 0x0 1311 1312 1313/* -- For PA_HPH_EARPA_MSTB_EN */ 1314#define TIMPANI_A_PA_HPH_EARPA_MSTB_EN (0x31) 1315#define TIMPANI_PA_HPH_EARPA_MSTB_EN_RWC "RW" 1316#define TIMPANI_PA_HPH_EARPA_MSTB_EN_POR 0x4 1317#define TIMPANI_PA_HPH_EARPA_MSTB_EN_S 0 1318#define TIMPANI_PA_HPH_EARPA_MSTB_EN_M 0xFF 1319 1320 1321#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_S 7 1322#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_M 0x80 1323#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_ENABLE 0x1 1324#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_EN_DISABLE 0x0 1325 1326#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_S 6 1327#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_M 0x40 1328#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_ENABLE 0x1 1329#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_L_BIAS_EN_DISABLE 0x0 1330 1331#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_S 5 1332#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_M 0x20 1333#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_ENABLE 0x1 1334#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_EN_DISABLE 0x0 1335 1336#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_S 4 1337#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_M 0x10 1338#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_ENABLE 0x1 1339#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_R_BIAS_EN_DISABLE 0x0 1340 1341#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_S 3 1342#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_M 0x8 1343#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_ENABLE 0x1 1344#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_VCM_BUFFER_EN_DISABLE 0x0 1345 1346#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_S 2 1347#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_M 0x4 1348#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_CAPLESS 0x1 1349#define TIMPANI_PA_HPH_EARPA_MSTB_EN_HPH_CAPLESS_MODE_LEGACY 0x0 1350 1351#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_S 1 1352#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_M 0x2 1353#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_ENABLE 0x1 1354#define TIMPANI_PA_HPH_EARPA_MSTB_EN_EARPA_EN_DISABLE 0x0 1355 1356#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_S 0 1357#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_M 0x1 1358#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_ENABLE 0x1 1359#define TIMPANI_PA_HPH_EARPA_MSTB_EN_PA_MASTER_BIAS_EN_DISABLE 0x0 1360 1361 1362/* -- For PA_LINE_AUXO_EN */ 1363#define TIMPANI_A_PA_LINE_AUXO_EN (0x32) 1364#define TIMPANI_PA_LINE_AUXO_EN_RWC "RW" 1365#define TIMPANI_PA_LINE_AUXO_EN_POR 0 1366#define TIMPANI_PA_LINE_AUXO_EN_S 0 1367#define TIMPANI_PA_LINE_AUXO_EN_M 0xFF 1368 1369 1370#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_S 7 1371#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_M 0x80 1372#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_ENABLE 0x1 1373#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_EN_DISABLE 0x0 1374 1375#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_S 6 1376#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_M 0x40 1377#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_ENABLE 0x1 1378#define TIMPANI_PA_LINE_AUXO_EN_LINE_L_BIAS_EN_DISABLE 0x0 1379 1380#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_S 5 1381#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_M 0x20 1382#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_ENABLE 0x1 1383#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_EN_DISABLE 0x0 1384 1385#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_S 4 1386#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_M 0x10 1387#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_ENABLE 0x1 1388#define TIMPANI_PA_LINE_AUXO_EN_LINE_R_BIAS_EN_DISABLE 0x0 1389 1390#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_S 3 1391#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_M 0x8 1392#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_ENABLE 0x1 1393#define TIMPANI_PA_LINE_AUXO_EN_LINE_VCM_BUFFER_EN_DISABLE 0x0 1394 1395#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_S 2 1396#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_M 0x4 1397#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_ENABLE 0x1 1398#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_EN_DISABLE 0x0 1399 1400#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_S 1 1401#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_M 0x2 1402#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_ENABLE 0x1 1403#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_BIAS_EN_DISABLE 0x0 1404 1405#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_S 0 1406#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_M 0x1 1407#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_ENABLE 0x1 1408#define TIMPANI_PA_LINE_AUXO_EN_AUXOUT_VCM_BUFFER_EN_DISABLE 0x0 1409 1410 1411/* -- For PA_CLASSD_AUXPGA_EN */ 1412#define TIMPANI_A_PA_CLASSD_AUXPGA_EN (0x33) 1413#define TIMPANI_PA_CLASSD_AUXPGA_EN_RWC "RW" 1414#define TIMPANI_PA_CLASSD_AUXPGA_EN_POR 0 1415#define TIMPANI_PA_CLASSD_AUXPGA_EN_S 0 1416#define TIMPANI_PA_CLASSD_AUXPGA_EN_M 0xFF 1417 1418 1419#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_S 7 1420#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_M 0x80 1421#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_MUTE 0x1 1422#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_MUTE_UNMUTE 0x0 1423 1424#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_S 6 1425#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_M 0x40 1426#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_MUTE 0x1 1427#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_MUTE_UNMUTE 0x0 1428 1429#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_S 5 1430#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_M 0x20 1431#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_DISABLE 0x0 1432#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_L_EN_ENABLE 0x1 1433 1434#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_S 4 1435#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_M 0x10 1436#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_DISABLE 0x0 1437#define TIMPANI_PA_CLASSD_AUXPGA_EN_AUXPGA_R_EN_ENABLE 0x1 1438 1439#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_S 3 1440#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_M 0x8 1441#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_DISABLE 0x0 1442#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_REF_EN_ENABLE 0x1 1443 1444#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_S 2 1445#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_M 0x4 1446#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_DISABLE 0x0 1447#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_L_EN_ENABLE 0x1 1448 1449#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_S 1 1450#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_M 0x2 1451#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_DISABLE 0x0 1452#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_REF_EN_ENABLE 0x1 1453 1454#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_S 0 1455#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_M 0x1 1456#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_DISABLE 0x0 1457#define TIMPANI_PA_CLASSD_AUXPGA_EN_CLASSD_R_EN_ENABLE 0x1 1458 1459 1460/* -- For PA_LINE_L_GAIN */ 1461#define TIMPANI_A_PA_LINE_L_GAIN (0x34) 1462#define TIMPANI_PA_LINE_L_GAIN_RWC "RW" 1463#define TIMPANI_PA_LINE_L_GAIN_POR 0xac 1464#define TIMPANI_PA_LINE_L_GAIN_S 0 1465#define TIMPANI_PA_LINE_L_GAIN_M 0xFF 1466 1467 1468#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_S 2 1469#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_M 0xFC 1470#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_1_5 0x0 1471#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_POS_0_0 0x1 1472#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_1_5 0x2 1473#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_3_0 0x3 1474#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_4_5 0x4 1475#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_6_0 0x5 1476#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_7_5 0x6 1477#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_9_0 0x7 1478#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_10_5 0x8 1479#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_12_0 0x9 1480#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_13_5 0xA 1481#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_15_0 0xB 1482#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_16_5 0xC 1483#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_18_0 0xD 1484#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_19_5 0xE 1485#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_21_0 0xF 1486#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_22_5 0x10 1487#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_24_0 0x11 1488#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_25_5 0x12 1489#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_27_0 0x13 1490#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_28_5 0x14 1491#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_30_0 0x15 1492#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_31_5 0x16 1493#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_33_0 0x17 1494#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_34_5 0x18 1495#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_36_0 0x19 1496#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_37_5 0x1A 1497#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_39_0 0x1B 1498#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_40_5 0x1C 1499#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_42_0 0x1D 1500#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_43_5 0x1E 1501#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_45_0 0x1F 1502#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_46_5 0x20 1503#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_48_0 0x21 1504#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_49_5 0x22 1505#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_51_0 0x23 1506#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_52_5 0x24 1507#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_54_0 0x25 1508#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_55_5 0x26 1509#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_57_0 0x27 1510#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_58_5 0x28 1511#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_60_0 0x29 1512#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_61_5 0x2A 1513#define TIMPANI_PA_LINE_L_GAIN_LINE_L_GAIN_NEG_63_0 0x2B 1514 1515#define TIMPANI_PA_LINE_L_GAIN_RESERVED_S 0 1516#define TIMPANI_PA_LINE_L_GAIN_RESERVED_M 0x3 1517 1518 1519/* -- For PA_LINE_R_GAIN */ 1520#define TIMPANI_A_PA_LINE_R_GAIN (0x35) 1521#define TIMPANI_PA_LINE_R_GAIN_RWC "RW" 1522#define TIMPANI_PA_LINE_R_GAIN_POR 0xac 1523#define TIMPANI_PA_LINE_R_GAIN_S 0 1524#define TIMPANI_PA_LINE_R_GAIN_M 0xFF 1525 1526 1527#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_S 2 1528#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_M 0xFC 1529#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_1_5 0x0 1530#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_POS_0_0 0x1 1531#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_1_5 0x2 1532#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_3_0 0x3 1533#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_4_5 0x4 1534#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_6_0 0x5 1535#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_7_5 0x6 1536#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_9_0 0x7 1537#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_10_5 0x8 1538#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_12_0 0x9 1539#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_13_5 0xA 1540#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_15_0 0xB 1541#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_16_5 0xC 1542#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_18_0 0xD 1543#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_19_5 0xE 1544#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_21_0 0xF 1545#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_22_5 0x10 1546#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_24_0 0x11 1547#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_25_5 0x12 1548#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_27_0 0x13 1549#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_28_5 0x14 1550#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_30_0 0x15 1551#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_31_5 0x16 1552#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_33_0 0x17 1553#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_34_5 0x18 1554#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_36_0 0x19 1555#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_37_5 0x1A 1556#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_39_0 0x1B 1557#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_40_5 0x1C 1558#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_42_0 0x1D 1559#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_43_5 0x1E 1560#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_45_0 0x1F 1561#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_46_5 0x20 1562#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_48_0 0x21 1563#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_49_5 0x22 1564#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_51_0 0x23 1565#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_52_5 0x24 1566#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_54_0 0x25 1567#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_55_5 0x26 1568#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_57_0 0x27 1569#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_58_5 0x28 1570#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_60_0 0x29 1571#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_61_5 0x2A 1572#define TIMPANI_PA_LINE_R_GAIN_LINE_R_GAIN_NEG_63_0 0x2B 1573 1574#define TIMPANI_PA_LINE_R_GAIN_RESERVED_S 0 1575#define TIMPANI_PA_LINE_R_GAIN_RESERVED_M 0x3 1576 1577 1578/* -- For PA_HPH_L_GAIN */ 1579#define TIMPANI_A_PA_HPH_L_GAIN (0x36) 1580#define TIMPANI_PA_HPH_L_GAIN_RWC "RW" 1581#define TIMPANI_PA_HPH_L_GAIN_POR 0xae 1582#define TIMPANI_PA_HPH_L_GAIN_S 0 1583#define TIMPANI_PA_HPH_L_GAIN_M 0xFF 1584 1585 1586#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_S 2 1587#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_M 0xFC 1588#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_1_5 0x0 1589#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_POS_0_0 0x1 1590#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_1_5 0x2 1591#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_3_0 0x3 1592#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_4_5 0x4 1593#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_6_0 0x5 1594#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_7_5 0x6 1595#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_9_0 0x7 1596#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_10_5 0x8 1597#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_12_0 0x9 1598#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_13_5 0xA 1599#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_15_0 0xB 1600#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_16_5 0xC 1601#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_18_0 0xD 1602#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_19_5 0xE 1603#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_21_0 0xF 1604#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_22_5 0x10 1605#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_24_0 0x11 1606#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_25_5 0x12 1607#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_27_0 0x13 1608#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_28_5 0x14 1609#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_30_0 0x15 1610#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_31_5 0x16 1611#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_33_0 0x17 1612#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_34_5 0x18 1613#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_36_0 0x19 1614#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_37_5 0x1A 1615#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_39_0 0x1B 1616#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_40_5 0x1C 1617#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_42_0 0x1D 1618#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_43_5 0x1E 1619#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_45_0 0x1F 1620#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_46_5 0x20 1621#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_48_0 0x21 1622#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_49_5 0x22 1623#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_51_0 0x23 1624#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_52_5 0x24 1625#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_54_0 0x25 1626#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_55_5 0x26 1627#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_57_0 0x27 1628#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_58_5 0x28 1629#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_60_0 0x29 1630#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_61_5 0x2A 1631#define TIMPANI_PA_HPH_L_GAIN_HPH_L_GAIN_NEG_63_0 0x2B 1632 1633#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_S 1 1634#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_M 0x2 1635#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_MUTE 0x1 1636#define TIMPANI_PA_HPH_L_GAIN_HPH_L_MUTE_UNMUTE 0x0 1637 1638#define TIMPANI_PA_HPH_L_GAIN_RESERVED_S 0 1639#define TIMPANI_PA_HPH_L_GAIN_RESERVED_M 0x1 1640 1641 1642/* -- For PA_HPH_R_GAIN */ 1643#define TIMPANI_A_PA_HPH_R_GAIN (0x37) 1644#define TIMPANI_PA_HPH_R_GAIN_RWC "RW" 1645#define TIMPANI_PA_HPH_R_GAIN_POR 0xae 1646#define TIMPANI_PA_HPH_R_GAIN_S 0 1647#define TIMPANI_PA_HPH_R_GAIN_M 0xFF 1648 1649 1650#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_S 2 1651#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_M 0xFC 1652#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_1_5 0x0 1653#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_POS_0_0 0x1 1654#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_1_5 0x2 1655#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_3_0 0x3 1656#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_4_5 0x4 1657#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_6_0 0x5 1658#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_7_5 0x6 1659#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_9_0 0x7 1660#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_10_5 0x8 1661#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_12_0 0x9 1662#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_13_5 0xA 1663#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_15_0 0xB 1664#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_16_5 0xC 1665#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_18_0 0xD 1666#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_19_5 0xE 1667#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_21_0 0xF 1668#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_22_5 0x10 1669#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_24_0 0x11 1670#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_25_5 0x12 1671#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_27_0 0x13 1672#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_28_5 0x14 1673#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_30_0 0x15 1674#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_31_5 0x16 1675#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_33_0 0x17 1676#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_34_5 0x18 1677#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_36_0 0x19 1678#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_37_5 0x1A 1679#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_39_0 0x1B 1680#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_40_5 0x1C 1681#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_42_0 0x1D 1682#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_43_5 0x1E 1683#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_45_0 0x1F 1684#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_46_5 0x20 1685#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_48_0 0x21 1686#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_49_5 0x22 1687#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_51_0 0x23 1688#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_52_5 0x24 1689#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_54_0 0x25 1690#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_55_5 0x26 1691#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_57_0 0x27 1692#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_58_5 0x28 1693#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_60_0 0x29 1694#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_61_5 0x2A 1695#define TIMPANI_PA_HPH_R_GAIN_HPH_R_GAIN_NEG_63_0 0x2B 1696 1697#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_S 1 1698#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_M 0x2 1699#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_MUTE 0x1 1700#define TIMPANI_PA_HPH_R_GAIN_HPH_R_MUTE_UNMUTE 0x0 1701 1702#define TIMPANI_PA_HPH_R_GAIN_RESERVED_S 0 1703#define TIMPANI_PA_HPH_R_GAIN_RESERVED_M 0x1 1704 1705 1706/* -- For AUXPGA_LR_GAIN */ 1707#define TIMPANI_A_AUXPGA_LR_GAIN (0x38) 1708#define TIMPANI_AUXPGA_LR_GAIN_RWC "RW" 1709#define TIMPANI_AUXPGA_LR_GAIN_POR 0xaa 1710#define TIMPANI_AUXPGA_LR_GAIN_S 0 1711#define TIMPANI_AUXPGA_LR_GAIN_M 0xFF 1712 1713 1714#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_S 4 1715#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_M 0xF0 1716#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_30DB 0x0 1717#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_27DB 0x1 1718#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_24DB 0x2 1719#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_21DB 0x3 1720#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_18DB 0x4 1721#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_15DB 0x5 1722#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_12DB 0x6 1723#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_9_0DB 0x7 1724#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_6_0DB 0x8 1725#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_NEG_3_0DB 0x9 1726#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_0_0DB 0xA 1727#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_3_0DB 0xB 1728#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_6_0DB 0xC 1729#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_9_0DB 0xD 1730#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_1 0xE 1731#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_L_GAIN_POS_12_0DB_2 0xF 1732 1733#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_S 0 1734#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_M 0xF 1735#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_30DB 0x0 1736#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_27DB 0x1 1737#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_24DB 0x2 1738#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_21DB 0x3 1739#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_18DB 0x4 1740#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_15DB 0x5 1741#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_12DB 0x6 1742#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_9_0DB 0x7 1743#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_6_0DB 0x8 1744#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_NEG_3_0DB 0x9 1745#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_0_0DB 0xA 1746#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_3_0DB 0xB 1747#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_6_0DB 0xC 1748#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_9_0DB 0xD 1749#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_1 0xE 1750#define TIMPANI_AUXPGA_LR_GAIN_AUXPGA_R_GAIN_POS_12_0DB_2 0xF 1751 1752 1753/* -- For PA_AUXO_EARPA_CONN */ 1754#define TIMPANI_A_PA_AUXO_EARPA_CONN (0x39) 1755#define TIMPANI_PA_AUXO_EARPA_CONN_RWC "RW" 1756#define TIMPANI_PA_AUXO_EARPA_CONN_POR 0 1757#define TIMPANI_PA_AUXO_EARPA_CONN_S 0 1758#define TIMPANI_PA_AUXO_EARPA_CONN_M 0xFF 1759 1760 1761#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_S 7 1762#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_M 0x80 1763#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_NO_CONNECT 0x0 1764#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_AUXPGA_L_CONN_CONNECT 0x1 1765 1766#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_S 6 1767#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_M 0x40 1768#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_NO_CONNECT 0x0 1769#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_IDAC_L_CONN_CONNECT 0x1 1770 1771#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_S 5 1772#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_M 0x20 1773#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_NO_CONNECT 0x0 1774#define TIMPANI_PA_AUXO_EARPA_CONN_AUXOUT_CDAC_L_CONN_CONNECT 0x1 1775 1776#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_S 4 1777#define TIMPANI_PA_AUXO_EARPA_CONN_RESERVED_M 0x10 1778 1779#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_S 3 1780#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_M 0x8 1781#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_3_52DB 0x1 1782#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_GAIN_V_2_02DB 0x0 1783 1784#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_S 2 1785#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_M 0x4 1786#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_NO_CONNECT 0x0 1787#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_AUXPGA_L_CONN_CONNECT 0x1 1788 1789#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_S 1 1790#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_M 0x2 1791#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_NO_CONNECT 0x0 1792#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_IDAC_L_CONN_CONNECT 0x1 1793 1794#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_S 0 1795#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_M 0x1 1796#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_NO_CONNECT 0x0 1797#define TIMPANI_PA_AUXO_EARPA_CONN_EARPA_CDAC_L_CONN_CONNECT 0x1 1798 1799 1800/* -- For PA_LINE_ST_CONN */ 1801#define TIMPANI_A_PA_LINE_ST_CONN (0x3A) 1802#define TIMPANI_PA_LINE_ST_CONN_RWC "RW" 1803#define TIMPANI_PA_LINE_ST_CONN_POR 0 1804#define TIMPANI_PA_LINE_ST_CONN_S 0 1805#define TIMPANI_PA_LINE_ST_CONN_M 0xFF 1806 1807 1808#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_S 7 1809#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_M 0x80 1810#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_NO_CONNECT 0x0 1811#define TIMPANI_PA_LINE_ST_CONN_LINE_L_AUXPGA_L_CONN_CONNECT 0x1 1812 1813#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_S 6 1814#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_M 0x40 1815#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_NO_CONNECT 0x0 1816#define TIMPANI_PA_LINE_ST_CONN_LINE_L_IDAC_L_CONN_CONNECT 0x1 1817 1818#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_S 5 1819#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_M 0x20 1820#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_NO_CONNECT 0x0 1821#define TIMPANI_PA_LINE_ST_CONN_LINE_L_CDAC_L_CONN_CONNECT 0x1 1822 1823#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_S 4 1824#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_M 0x10 1825#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_NO_CONNECT 0x0 1826#define TIMPANI_PA_LINE_ST_CONN_LINE_R_AUXPGA_R_CONN_CONNECT 0x1 1827 1828#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_S 3 1829#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_M 0x8 1830#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_NO_CONNECT 0x0 1831#define TIMPANI_PA_LINE_ST_CONN_LINE_R_IDAC_R_CONN_CONNECT 0x1 1832 1833#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_S 2 1834#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_M 0x4 1835#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_NO_CONNECT 0x0 1836#define TIMPANI_PA_LINE_ST_CONN_LINE_R_CDAC_R_CONN_CONNECT 0x1 1837 1838#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_S 0 1839#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_M 0x3 1840#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_NONE 0x0 1841#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_1_25UA 0x1 1842#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_2_5UA 0x2 1843#define TIMPANI_PA_LINE_ST_CONN_AUXPGA_L_VCM_ADD_CURR_V_3_75UA 0x3 1844 1845 1846/* -- For PA_LINE_MONO_CONN */ 1847#define TIMPANI_A_PA_LINE_MONO_CONN (0x3B) 1848#define TIMPANI_PA_LINE_MONO_CONN_RWC "RW" 1849#define TIMPANI_PA_LINE_MONO_CONN_POR 0 1850#define TIMPANI_PA_LINE_MONO_CONN_S 0 1851#define TIMPANI_PA_LINE_MONO_CONN_M 0xFF 1852 1853 1854#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_S 7 1855#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_M 0x80 1856#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_NO_CONNECT 0x0 1857#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_CONN_CONNECT 0x1 1858 1859#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_S 6 1860#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_M 0x40 1861#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_NO_CONNECT 0x0 1862#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_CONN_CONNECT 0x1 1863 1864#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_S 5 1865#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_M 0x20 1866#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_NO_CONNECT 0x0 1867#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_CONN_CONNECT 0x1 1868 1869#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_S 4 1870#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_M 0x10 1871#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0 1872#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_AUXPGA_L_INV_CONN_CONNECT 0x1 1873 1874#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_S 3 1875#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_M 0x8 1876#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_NO_CONNECT 0x0 1877#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_IDAC_L_INV_CONN_CONNECT 0x1 1878 1879#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_S 2 1880#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_M 0x4 1881#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_NO_CONNECT 0x0 1882#define TIMPANI_PA_LINE_MONO_CONN_LINE_R_CDAC_L_INV_CONN_CONNECT 0x1 1883 1884#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_S 0 1885#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_M 0x3 1886#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_NONE 0x0 1887#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_1_25UA 0x1 1888#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_2_5UA 0x2 1889#define TIMPANI_PA_LINE_MONO_CONN_AUXPGA_R_VCM_ADD_CURR_V_3_75UA 0x3 1890 1891 1892/* -- For PA_HPH_ST_CONN */ 1893#define TIMPANI_A_PA_HPH_ST_CONN (0x3C) 1894#define TIMPANI_PA_HPH_ST_CONN_RWC "RW" 1895#define TIMPANI_PA_HPH_ST_CONN_POR 0 1896#define TIMPANI_PA_HPH_ST_CONN_S 0 1897#define TIMPANI_PA_HPH_ST_CONN_M 0xFF 1898 1899 1900#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_S 7 1901#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_M 0x80 1902#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_NO_CONNECT 0x0 1903#define TIMPANI_PA_HPH_ST_CONN_HPH_L_AUXPGA_L_CONN_CONNECT 0x1 1904 1905#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_S 6 1906#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_M 0x40 1907#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_NO_CONNECT 0x0 1908#define TIMPANI_PA_HPH_ST_CONN_HPH_L_IDAC_L_CONN_CONNECT 0x1 1909 1910#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_S 5 1911#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_M 0x20 1912#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_NO_CONNECT 0x0 1913#define TIMPANI_PA_HPH_ST_CONN_HPH_L_CDAC_L_CONN_CONNECT 0x1 1914 1915#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_S 4 1916#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_M 0x10 1917#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_NO_CONNECT 0x0 1918#define TIMPANI_PA_HPH_ST_CONN_HPH_R_AUXPGA_R_CONN_CONNECT 0x1 1919 1920#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_S 3 1921#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_M 0x8 1922#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_NO_CONNECT 0x0 1923#define TIMPANI_PA_HPH_ST_CONN_HPH_R_IDAC_R_CONN_CONNECT 0x1 1924 1925#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_S 2 1926#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_M 0x4 1927#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_NO_CONNECT 0x0 1928#define TIMPANI_PA_HPH_ST_CONN_HPH_R_CDAC_R_CONN_CONNECT 0x1 1929 1930#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_S 1 1931#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_M 0x2 1932#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_DISABLE 0x1 1933#define TIMPANI_PA_HPH_ST_CONN_HPH_L_RAMP_GEN_EN_ENABLE 0x0 1934 1935#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_S 0 1936#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_M 0x1 1937#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_DISABLE 0x1 1938#define TIMPANI_PA_HPH_ST_CONN_HPH_R_RAMP_GEN_EN_ENABLE 0x0 1939 1940 1941/* -- For PA_HPH_MONO_CONN */ 1942#define TIMPANI_A_PA_HPH_MONO_CONN (0x3D) 1943#define TIMPANI_PA_HPH_MONO_CONN_RWC "RW" 1944#define TIMPANI_PA_HPH_MONO_CONN_POR 0 1945#define TIMPANI_PA_HPH_MONO_CONN_S 0 1946#define TIMPANI_PA_HPH_MONO_CONN_M 0xFF 1947 1948 1949#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_S 7 1950#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_M 0x80 1951#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_NO_CONNECT 0x0 1952#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_CONN_CONNECT 0x1 1953 1954#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_S 6 1955#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_M 0x40 1956#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_NO_CONNECT 0x0 1957#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_CONN_CONNECT 0x1 1958 1959#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_S 5 1960#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_M 0x20 1961#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_NO_CONNECT 0x0 1962#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_CONN_CONNECT 0x1 1963 1964#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_S 4 1965#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_M 0x10 1966#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_NO_CONNECT 0x0 1967#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_AUXPGA_L_INV_CONN_CONNECT 0x1 1968 1969#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_S 3 1970#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_M 0x8 1971#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_NO_CONNECT 0x0 1972#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_IDAC_L_INV_CONN_CONNECT 0x1 1973 1974#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_S 2 1975#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_M 0x4 1976#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_NO_CONNECT 0x0 1977#define TIMPANI_PA_HPH_MONO_CONN_HPH_R_CDAC_L_INV_CONN_CONNECT 0x1 1978 1979#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_S 0 1980#define TIMPANI_PA_HPH_MONO_CONN_RESERVED_M 0x3 1981 1982 1983/* -- For PA_CLASSD_CONN */ 1984#define TIMPANI_A_PA_CLASSD_CONN (0x3E) 1985#define TIMPANI_PA_CLASSD_CONN_RWC "RW" 1986#define TIMPANI_PA_CLASSD_CONN_POR 0 1987#define TIMPANI_PA_CLASSD_CONN_S 0 1988#define TIMPANI_PA_CLASSD_CONN_M 0xFF 1989 1990 1991#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_S 7 1992#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_M 0x80 1993#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_NO_CONNECT 0x0 1994#define TIMPANI_PA_CLASSD_CONN_CLASSD_CDAC_CONN_CONNECT 0x1 1995 1996#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_S 6 1997#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_M 0x40 1998#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_NO_CONNECT 0x0 1999#define TIMPANI_PA_CLASSD_CONN_CLASSD_IDAC_CONN_CONNECT 0x1 2000 2001#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_S 5 2002#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_M 0x20 2003#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_NO_CONNECT 0x0 2004#define TIMPANI_PA_CLASSD_CONN_CLASSD_AUXPGA_CONN_CONNECT 0x1 2005 2006#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_S 4 2007#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_M 0x10 2008#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_MONO_DIFF 0x1 2009#define TIMPANI_PA_CLASSD_CONN_CLASSD_PA_MODE_STEREO 0x0 2010 2011#define TIMPANI_PA_CLASSD_CONN_RESERVED_S 0 2012#define TIMPANI_PA_CLASSD_CONN_RESERVED_M 0xF 2013 2014 2015/* -- For PA_CNP_CTL */ 2016#define TIMPANI_A_PA_CNP_CTL (0x3F) 2017#define TIMPANI_PA_CNP_CTL_RWC "RW" 2018#define TIMPANI_PA_CNP_CTL_POR 0x07 2019#define TIMPANI_PA_CNP_CTL_S 0 2020#define TIMPANI_PA_CNP_CTL_M 0xFF 2021 2022 2023#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_S 6 2024#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_M 0xC0 2025#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_1_75_NA 0x0 2026#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_3_5_NA_NORMAL_OP 0x1 2027#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_5_25_NA 0x2 2028#define TIMPANI_PA_CNP_CTL_CNP_RAMP_GEN_CURRENT_V_10_NA 0x3 2029 2030#define TIMPANI_PA_CNP_CTL_RESERVED_S 4 2031#define TIMPANI_PA_CNP_CTL_RESERVED_M 0x30 2032 2033#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_S 3 2034#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_M 0x8 2035#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_DISABLE 0x0 2036#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_CIRCUIT_EN_ENABLE 0x1 2037 2038#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_S 0 2039#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_M 0x7 2040#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_220_V 0x0 2041#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_243_V 0x1 2042#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_266_V 0x2 2043#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_290_V 0x3 2044#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_341_V 0x4 2045#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_339_V 0x5 2046#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_365_V 0x6 2047#define TIMPANI_PA_CNP_CTL_CLASSD_SUPPLY_DUMP_THRESH_V_2_391_V 0x7 2048 2049 2050/* -- For PA_CLASSD_L_CTL */ 2051#define TIMPANI_A_PA_CLASSD_L_CTL (0x40) 2052#define TIMPANI_PA_CLASSD_L_CTL_RWC "RW" 2053#define TIMPANI_PA_CLASSD_L_CTL_POR 0x08 2054#define TIMPANI_PA_CLASSD_L_CTL_S 0 2055#define TIMPANI_PA_CLASSD_L_CTL_M 0xFF 2056 2057 2058#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_S 6 2059#define TIMPANI_PA_CLASSD_L_CTL_RESERVED_M 0xC0 2060 2061#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_S 5 2062#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_M 0x20 2063#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_NORMAL_OP 0x0 2064#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_LOGIC_RESET_RESET_PA_LOGIC 0x1 2065 2066#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_S 4 2067#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_M 0x10 2068#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_NORMAL_OP 0x0 2069#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_INT_RESET_DISCHARGE_CAPS 0x1 2070 2071#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_S 2 2072#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_M 0xC 2073#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_GND 0x0 2074#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_IBIAS_X_R_REF 0x1 2075#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_BG_VOLTAGE 0x2 2076#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_REF_SEL_VDD_BY_2 0x3 2077 2078#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_S 1 2079#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_M 0x2 2080#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_NORMAL_OP 0x0 2081#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_1_PA_OUT_TO_VDD 0x1 2082 2083#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_S 0 2084#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_M 0x1 2085#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_NORMAL_OP 0x0 2086#define TIMPANI_PA_CLASSD_L_CTL_CLASSD_L_PA_FORCE_0_PA_OUT_TO_GND 0x1 2087 2088 2089/* -- For PA_CLASSD_R_CTL */ 2090#define TIMPANI_A_PA_CLASSD_R_CTL (0x41) 2091#define TIMPANI_PA_CLASSD_R_CTL_RWC "RW" 2092#define TIMPANI_PA_CLASSD_R_CTL_POR 0x08 2093#define TIMPANI_PA_CLASSD_R_CTL_S 0 2094#define TIMPANI_PA_CLASSD_R_CTL_M 0xFF 2095 2096 2097#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_S 6 2098#define TIMPANI_PA_CLASSD_R_CTL_RESERVED_M 0xC0 2099 2100#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_S 5 2101#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_M 0x20 2102#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_NORMAL_OP 0x0 2103#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_LOGIC_RESET_RESET_PA_LOGIC 0x1 2104 2105#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_S 4 2106#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_M 0x10 2107#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_NORMAL_OP 0x0 2108#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_INT_RESET_DISCHARGE_CAPS 0x1 2109 2110#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_S 2 2111#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_M 0xC 2112#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_GND 0x0 2113#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_IBIAS_X_R_REF 0x1 2114#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_BG_VOLTAGE 0x2 2115#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_REF_SEL_VDD_BY_2 0x3 2116 2117#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_S 1 2118#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_M 0x2 2119#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_NORMAL_OP 0x0 2120#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_1_PA_OUT_TO_VDD 0x1 2121 2122#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_S 0 2123#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_M 0x1 2124#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_NORMAL_OP 0x0 2125#define TIMPANI_PA_CLASSD_R_CTL_CLASSD_R_PA_FORCE_0_PA_OUT_TO_GND 0x1 2126 2127 2128/* -- For PA_CLASSD_INT2_CTL */ 2129#define TIMPANI_A_PA_CLASSD_INT2_CTL (0x42) 2130#define TIMPANI_PA_CLASSD_INT2_CTL_RWC "RW" 2131#define TIMPANI_PA_CLASSD_INT2_CTL_POR 0xb0 2132#define TIMPANI_PA_CLASSD_INT2_CTL_S 0 2133#define TIMPANI_PA_CLASSD_INT2_CTL_M 0xFF 2134 2135 2136#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_S 6 2137#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_M 0xC0 2138#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_5_0PF 0x0 2139#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_7_5PF 0x1 2140#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_10PF 0x2 2141#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_CFB_V_15PF 0x3 2142 2143#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_S 4 2144#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_M 0x30 2145#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_100K 0x0 2146#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_150K 0x1 2147#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_175K 0x2 2148#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_L_INT2_RIN_V_200K 0x3 2149 2150#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_S 2 2151#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_M 0xC 2152#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_5_0PF 0x0 2153#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_7_5PF 0x1 2154#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_10PF 0x2 2155#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_CFB_V_15PF 0x3 2156 2157#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_S 0 2158#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_M 0x3 2159#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_100K 0x0 2160#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_150K 0x1 2161#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_175K 0x2 2162#define TIMPANI_PA_CLASSD_INT2_CTL_CLASSD_R_INT2_RIN_V_200K 0x3 2163 2164 2165/* -- For PA_HPH_L_OCP_CLK_CTL */ 2166#define TIMPANI_A_PA_HPH_L_OCP_CLK_CTL (0x43) 2167#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_RWC "RW" 2168#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_POR 0xf2 2169#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_S 0 2170#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_M 0xFF 2171 2172 2173#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_S 7 2174#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_M 0x80 2175#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_ENABLE 0x1 2176#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_DIV_2_EN_DISABLE 0x0 2177 2178#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_S 6 2179#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_M 0x40 2180#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1 2181#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0 2182 2183#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_S 4 2184#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_M 0x30 2185#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0 2186#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1 2187#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2 2188#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3 2189 2190#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_S 3 2191#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_M 0x8 2192#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_2 0x1 2193#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_CLK_SEL_LEFT_CLK_FROM_CH_1 0x0 2194 2195#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_S 2 2196#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_M 0x4 2197#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_ENABLE 0x1 2198#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_2_EN_DISABLE 0x0 2199 2200#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_S 0 2201#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_M 0x3 2202#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0 2203#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1 2204#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2 2205#define TIMPANI_PA_HPH_L_OCP_CLK_CTL_HPH_L_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3 2206 2207 2208/* -- For PA_CLASSD_L_SW_CTL */ 2209#define TIMPANI_A_PA_CLASSD_L_SW_CTL (0x44) 2210#define TIMPANI_PA_CLASSD_L_SW_CTL_RWC "RW" 2211#define TIMPANI_PA_CLASSD_L_SW_CTL_POR 0x37 2212#define TIMPANI_PA_CLASSD_L_SW_CTL_S 0 2213#define TIMPANI_PA_CLASSD_L_SW_CTL_M 0xFF 2214 2215 2216#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_S 6 2217#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_M 0xC0 2218#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_1 0x0 2219#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_2 0x1 2220#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_3 0x2 2221#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_BREAK_BEFORE_MAKE_DELAY_V_4 0x3 2222 2223#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_S 4 2224#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_M 0x30 2225#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0 2226#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1 2227#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2 2228#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3 2229 2230#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_S 3 2231#define TIMPANI_PA_CLASSD_L_SW_CTL_RESERVED_M 0x8 2232 2233#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_S 2 2234#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_M 0x4 2235#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_DISABLE 0x0 2236#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_BYPASS_CAP_EN_ENABLE 0x1 2237 2238#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_S 1 2239#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_M 0x2 2240#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_DISABLE 0x0 2241#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_NON_OVERLAP_EN_ENABLE 0x1 2242 2243#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_S 0 2244#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_M 0x1 2245#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_POWER_GROUND 0x0 2246#define TIMPANI_PA_CLASSD_L_SW_CTL_CLASSD_L_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1 2247 2248/* -- For PA_CLASSD_L_OCP1 */ 2249#define TIMPANI_A_PA_CLASSD_L_OCP1 (0x45) 2250#define TIMPANI_PA_CLASSD_L_OCP1_RWC "RW" 2251#define TIMPANI_PA_CLASSD_L_OCP1_POR 0xff 2252#define TIMPANI_PA_CLASSD_L_OCP1_S 0 2253#define TIMPANI_PA_CLASSD_L_OCP1_M 0xFF 2254 2255 2256#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_S 7 2257#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_M 0x80 2258#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_DISABLE 0x0 2259#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_EN_ENABLE 0x1 2260 2261#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_S 6 2262#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_M 0x40 2263#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_NEVER_LOCKS 0x0 2264#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_LOCK_LOCKS 0x1 2265 2266#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_S 4 2267#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_M 0x30 2268#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0 2269#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1 2270#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2 2271#define TIMPANI_PA_CLASSD_L_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3 2272 2273#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_S 0 2274#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_M 0xF 2275#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_1 0x1 2276#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_2 0x2 2277#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_3 0x3 2278#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_4 0x4 2279#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_5 0x5 2280#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_6 0x6 2281#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_7 0x7 2282#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_8 0x8 2283#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_9 0x9 2284#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_10 0xA 2285#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_11 0xB 2286#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_12 0xC 2287#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_13 0xD 2288#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_14 0xE 2289#define TIMPANI_PA_CLASSD_L_OCP1_CLASSD_L_OCP_NUM_CONN_ATTEMPTS_V_15 0xF 2290 2291/* -- For PA_CLASSD_L_OCP2 */ 2292#define TIMPANI_A_PA_CLASSD_L_OCP2 (0x46) 2293#define TIMPANI_PA_CLASSD_L_OCP2_RWC "RW" 2294#define TIMPANI_PA_CLASSD_L_OCP2_POR 0x77 2295#define TIMPANI_PA_CLASSD_L_OCP2_S 0 2296#define TIMPANI_PA_CLASSD_L_OCP2_M 0xFF 2297 2298 2299#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_S 4 2300#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_M 0xF0 2301#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_255 0x0 2302#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_511 0x1 2303#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_767 0x2 2304#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1023 0x3 2305#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1279 0x4 2306#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1535 0x5 2307#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_1791 0x6 2308#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2047 0x7 2309#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2303 0x8 2310#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2559 0x9 2311#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_2815 0xA 2312#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3071 0xB 2313#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3327 0xC 2314#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3583 0xD 2315#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_3839 0xE 2316#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_WAIT_CNT_V_4095 0xF 2317 2318#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_S 0 2319#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_M 0xF 2320#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_255 0x0 2321#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_511 0x1 2322#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_767 0x2 2323#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1023 0x3 2324#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1279 0x4 2325#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1535 0x5 2326#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_1791 0x6 2327#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2047 0x7 2328#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2303 0x8 2329#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2559 0x9 2330#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_2815 0xA 2331#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3071 0xB 2332#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3327 0xC 2333#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3583 0xD 2334#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_3839 0xE 2335#define TIMPANI_PA_CLASSD_L_OCP2_CLASSD_L_OCP_OCP_RUN_CNT_V_4095 0xF 2336 2337 2338/* -- For PA_HPH_R_OCP_CLK_CTL */ 2339#define TIMPANI_A_PA_HPH_R_OCP_CLK_CTL (0x47) 2340#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_RWC "RW" 2341#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_POR 0xf2 2342#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_S 0 2343#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_M 0xFF 2344 2345 2346#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_S 7 2347#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_M 0x80 2348#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_ENABLE 0x1 2349#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_DIV_2_EN_DISABLE 0x0 2350 2351#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_S 6 2352#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_M 0x40 2353#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_ENABLE 0x1 2354#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_EN_DISABLE 0x0 2355 2356#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_S 4 2357#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_M 0x30 2358#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV2 0x0 2359#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV4 0x1 2360#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV6 0x2 2361#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CARRIER_PROG_DIV_RATIO_DIV8 0x3 2362 2363#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_S 3 2364#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_M 0x8 2365#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_2 0x1 2366#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_CLK_SEL_RIGHT_CLK_FROM_CH_1 0x0 2367 2368#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_S 2 2369#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_M 0x4 2370#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_ENABLE 0x1 2371#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_2_EN_DISABLE 0x0 2372 2373#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_S 0 2374#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_M 0x3 2375#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_4 0x0 2376#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_8 0x1 2377#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_12 0x2 2378#define TIMPANI_PA_HPH_R_OCP_CLK_CTL_HPH_R_OCP_TIMER_DIV_RATIO_DIV_BY_16 0x3 2379 2380 2381/* -- For PA_CLASSD_R_SW_CTL */ 2382#define TIMPANI_A_PA_CLASSD_R_SW_CTL (0x48) 2383#define TIMPANI_PA_CLASSD_R_SW_CTL_RWC "RW" 2384#define TIMPANI_PA_CLASSD_R_SW_CTL_POR 0x37 2385#define TIMPANI_PA_CLASSD_R_SW_CTL_S 0 2386#define TIMPANI_PA_CLASSD_R_SW_CTL_M 0xFF 2387 2388 2389#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_S 6 2390#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_M 0xC0 2391#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_1 0x0 2392#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_2 0x1 2393#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_3 0x2 2394#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_BREAK_BEFORE_MAKE_DELAY_V_4 0x3 2395 2396#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_S 4 2397#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_M 0x30 2398#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_3_OF_6_UNITS 0x0 2399#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_4_OF_6_UNITS 0x1 2400#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_5_OF_6_UNITS 0x2 2401#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_OUT_DRIVE_STREN_V_6_OF_6_UNITS 0x3 2402 2403#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_S 3 2404#define TIMPANI_PA_CLASSD_R_SW_CTL_RESERVED_M 0x8 2405 2406#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_S 2 2407#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_M 0x4 2408#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_DISABLE 0x0 2409#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_BYPASS_CAP_EN_ENABLE 0x1 2410 2411#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_S 1 2412#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_M 0x2 2413#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_DISABLE 0x0 2414#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_NON_OVERLAP_EN_ENABLE 0x1 2415 2416#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_S 0 2417#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_M 0x1 2418#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_POWER_GROUND 0x0 2419#define TIMPANI_PA_CLASSD_R_SW_CTL_CLASSD_R_CDAC_SWITCH_MODE_RST_MIDPOINT 0x1 2420 2421 2422/* -- For PA_CLASSD_R_OCP1 */ 2423#define TIMPANI_A_PA_CLASSD_R_OCP1 (0x49) 2424#define TIMPANI_PA_CLASSD_R_OCP1_RWC "RW" 2425#define TIMPANI_PA_CLASSD_R_OCP1_POR 0xff 2426#define TIMPANI_PA_CLASSD_R_OCP1_S 0 2427#define TIMPANI_PA_CLASSD_R_OCP1_M 0xFF 2428 2429 2430#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_S 7 2431#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_M 0x80 2432#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_DISABLE 0x0 2433#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_EN_ENABLE 0x1 2434 2435#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_S 6 2436#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_M 0x40 2437#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_NEVER_LOCKS 0x0 2438#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_LOCK_LOCKS 0x1 2439 2440#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_S 4 2441#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_M 0x30 2442#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_100MA_83_3MA_66_7MA_50MA 0x0 2443#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_133MA_111MA_88_7MA_66_7MA 0x1 2444#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_166MA_138MA_111MA_83_3MA 0x2 2445#define TIMPANI_PA_CLASSD_R_OCP1_OCP_CUR_THRESH_V_200MA_166MA_133MA_100MA 0x3 2446 2447#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_S 0 2448#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_M 0xF 2449#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_1 0x1 2450#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_2 0x2 2451#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_3 0x3 2452#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_4 0x4 2453#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_5 0x5 2454#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_6 0x6 2455#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_7 0x7 2456#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_8 0x8 2457#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_9 0x9 2458#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_10 0xA 2459#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_11 0xB 2460#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_12 0xC 2461#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_13 0xD 2462#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_14 0xE 2463#define TIMPANI_PA_CLASSD_R_OCP1_CLASSD_R_OCP_NUM_CONN_ATTEMPTS_V_15 0xF 2464 2465 2466/* -- For PA_CLASSD_R_OCP2 */ 2467#define TIMPANI_A_PA_CLASSD_R_OCP2 (0x4A) 2468#define TIMPANI_PA_CLASSD_R_OCP2_RWC "RW" 2469#define TIMPANI_PA_CLASSD_R_OCP2_POR 0x77 2470#define TIMPANI_PA_CLASSD_R_OCP2_S 0 2471#define TIMPANI_PA_CLASSD_R_OCP2_M 0xFF 2472 2473 2474#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_S 4 2475#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_M 0xF0 2476#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_255 0x0 2477#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_511 0x1 2478#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_767 0x2 2479#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1023 0x3 2480#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1279 0x4 2481#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1535 0x5 2482#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_1791 0x6 2483#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2047 0x7 2484#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2303 0x8 2485#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2559 0x9 2486#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_2815 0xA 2487#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3071 0xB 2488#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3327 0xC 2489#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3583 0xD 2490#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_3839 0xE 2491#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_WAIT_CNT_V_4095 0xF 2492 2493#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_S 0 2494#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_M 0xF 2495#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_255 0x0 2496#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_511 0x1 2497#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_767 0x2 2498#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1023 0x3 2499#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1279 0x4 2500#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1535 0x5 2501#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_1791 0x6 2502#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2047 0x7 2503#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2303 0x8 2504#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2559 0x9 2505#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_2815 0xA 2506#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3071 0xB 2507#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3327 0xC 2508#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3583 0xD 2509#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_3839 0xE 2510#define TIMPANI_PA_CLASSD_R_OCP2_CLASSD_R_OCP_OCP_RUN_CNT_V_4095 0xF 2511 2512 2513/* -- For PA_HPH_CTL1 */ 2514#define TIMPANI_A_PA_HPH_CTL1 (0x4B) 2515#define TIMPANI_PA_HPH_CTL1_RWC "RW" 2516#define TIMPANI_PA_HPH_CTL1_POR 0x44 2517#define TIMPANI_PA_HPH_CTL1_S 0 2518#define TIMPANI_PA_HPH_CTL1_M 0xFF 2519 2520 2521#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_S 4 2522#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_M 0xF0 2523#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_400PER 0x1 2524#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_200PER 0x2 2525#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_133PER 0x3 2526#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_100PER 0x4 2527#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_66PER 0x6 2528#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_50PER 0x8 2529#define TIMPANI_PA_HPH_CTL1_HPH_GM3_BIAS_V_33PER 0xC 2530 2531#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_S 3 2532#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_M 0x8 2533#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_DISABLE 0x0 2534#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_DET_EN_ENABLE 0x1 2535 2536#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_S 0 2537#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_M 0x7 2538#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_300MA 0x0 2539#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_350MA 0x2 2540#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_365MA 0x3 2541#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_150MA 0x4 2542#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_190MA 0x6 2543#define TIMPANI_PA_HPH_CTL1_HPH_SHORT_CIRCUIT_CUR_LIMIT_V_220MA 0x7 2544 2545 2546/* -- For PA_HPH_CTL2 */ 2547#define TIMPANI_A_PA_HPH_CTL2 (0x4C) 2548#define TIMPANI_PA_HPH_CTL2_RWC "RW" 2549#define TIMPANI_PA_HPH_CTL2_POR 0xC8 2550#define TIMPANI_PA_HPH_CTL2_S 0 2551#define TIMPANI_PA_HPH_CTL2_M 0xFF 2552 2553 2554#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_S 7 2555#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_M 0x80 2556#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VNEG 0x1 2557#define TIMPANI_PA_HPH_CTL2_HPH_SW_VNEG_CTL_VSS 0x0 2558 2559#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_S 6 2560#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_M 0x40 2561#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_1_5 0x1 2562#define TIMPANI_PA_HPH_CTL2_HPH_VNEG_PS_GAIN_V_2_5 0x0 2563 2564#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_S 5 2565#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_M 0x20 2566#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_ENABLE 0x1 2567#define TIMPANI_PA_HPH_CTL2_HPH_PS_FILTER_EN_DISABLE 0x0 2568 2569#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_S 4 2570#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_M 0x10 2571#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_ENABLE 0x1 2572#define TIMPANI_PA_HPH_CTL2_HPH_OCP_EN_DISABLE 0x0 2573 2574#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_S 2 2575#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_M 0xC 2576#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_GROUND 0x0 2577#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_IBIAS_ON_RESISTOR 0x1 2578#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_BG 0x2 2579#define TIMPANI_PA_HPH_CTL2_HPH_VREF_SEL_AVDD_BY_2 0x3 2580 2581#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_S 1 2582#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_M 0x2 2583#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_DISABLE 0x0 2584#define TIMPANI_PA_HPH_CTL2_HPH_OUT_SHUNT_EN_ENABLE 0x1 2585 2586#define TIMPANI_PA_HPH_CTL2_RESERVED_S 0 2587#define TIMPANI_PA_HPH_CTL2_RESERVED_M 0x1 2588 2589 2590/* -- For PA_LINE_AUXO_CTL */ 2591#define TIMPANI_A_PA_LINE_AUXO_CTL (0x4D) 2592#define TIMPANI_PA_LINE_AUXO_CTL_RWC "RW" 2593#define TIMPANI_PA_LINE_AUXO_CTL_POR 0x2 2594#define TIMPANI_PA_LINE_AUXO_CTL_S 0 2595#define TIMPANI_PA_LINE_AUXO_CTL_M 0xFF 2596 2597 2598#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_S 6 2599#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_M 0xC0 2600#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_1_75NA 0x0 2601#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_3_5NA 0x1 2602#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_5_25NA 0x2 2603#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_RAMPGEN_CNT_V_10NA 0x3 2604 2605#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_S 4 2606#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_M 0x30 2607#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_60UA 0x0 2608#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_1 0x1 2609#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_30UA_2 0x2 2610#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_L_BIAS_CUR_V_15UA 0x3 2611 2612#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_S 2 2613#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_M 0xC 2614#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_60UA 0x0 2615#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_1 0x1 2616#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_30UA_2 0x2 2617#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_R_BIAS_CUR_V_15UA 0x3 2618 2619#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_S 0 2620#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_M 0x3 2621#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VSSA 0x0 2622#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_BG 0x2 2623#define TIMPANI_PA_LINE_AUXO_CTL_LINEO_AUXO_CM_REF_SEL_VDDA_BY_2 0x3 2624 2625 2626/* -- For PA_AUXO_EARPA_CTL */ 2627#define TIMPANI_A_PA_AUXO_EARPA_CTL (0x4E) 2628#define TIMPANI_PA_AUXO_EARPA_CTL_RWC "RW" 2629#define TIMPANI_PA_AUXO_EARPA_CTL_POR 0xe 2630#define TIMPANI_PA_AUXO_EARPA_CTL_S 0 2631#define TIMPANI_PA_AUXO_EARPA_CTL_M 0xFF 2632 2633 2634#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_S 6 2635#define TIMPANI_PA_AUXO_EARPA_CTL_RESERVED_M 0xC0 2636 2637#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_S 4 2638#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_M 0x30 2639#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_60UA 0x0 2640#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA 0x1 2641#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_30UA_SAME_AS_01 0x2 2642#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_BIAS_CUR_V_15UA 0x3 2643 2644#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_S 3 2645#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_M 0x8 2646#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_4_5DB 0x1 2647#define TIMPANI_PA_AUXO_EARPA_CTL_AUXO_GAIN_NEG_3_0DB 0x0 2648 2649#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_S 1 2650#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_M 0x6 2651#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_12_5UA 0x0 2652#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_10_0UA 0x1 2653#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_7_5UA 0x2 2654#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_MASTER_BIAS_CUR_V_5_0UA 0x3 2655 2656#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_S 0 2657#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_M 0x1 2658#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_BG 0x1 2659#define TIMPANI_PA_AUXO_EARPA_CTL_EARPA_VCM_SOURCE_LOCAL_VCM 0x0 2660 2661 2662/* -- For PA_EARO_CTL */ 2663#define TIMPANI_A_PA_EARO_CTL (0x4F) 2664#define TIMPANI_PA_EARO_CTL_RWC "RW" 2665#define TIMPANI_PA_EARO_CTL_POR 0x0 2666#define TIMPANI_PA_EARO_CTL_S 0 2667#define TIMPANI_PA_EARO_CTL_M 0xFF 2668 2669 2670#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_S 7 2671#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_M 0x80 2672#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_NORMAL_OP 0x0 2673#define TIMPANI_PA_EARO_CTL_EARPA_STARTUP_CONNECT_INPUTS_TO_GROUND 0x1 2674 2675#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_S 6 2676#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_M 0x40 2677#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_NO_BYPASS 0x0 2678#define TIMPANI_PA_EARO_CTL_EARPA_BYPASS_INPUT_CM_BYPASS 0x1 2679 2680#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_S 3 2681#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_M 0x38 2682#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_213UA 0x0 2683#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_280UA 0x1 2684#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_1 0x2 2685#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_1 0x3 2686#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_408UA_2 0x4 2687#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_530UA 0x5 2688#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_780UA_2 0x6 2689#define TIMPANI_PA_EARO_CTL_EARPA_NMOS_BIAS_CUR_V_1480UA 0x7 2690 2691#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_S 0 2692#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_M 0x7 2693#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_213UA 0x0 2694#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_280UA 0x1 2695#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_1 0x2 2696#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_1 0x3 2697#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_408UA_2 0x4 2698#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_530UA 0x5 2699#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_780UA_2 0x6 2700#define TIMPANI_PA_EARO_CTL_EARPA_PMOS_BIAS_CUR_V_1480UA 0x7 2701 2702 2703/* -- For PA_MASTER_BIAS_CUR */ 2704#define TIMPANI_A_PA_MASTER_BIAS_CUR (0x50) 2705#define TIMPANI_PA_MASTER_BIAS_CUR_RWC "RW" 2706#define TIMPANI_PA_MASTER_BIAS_CUR_POR 0xea 2707#define TIMPANI_PA_MASTER_BIAS_CUR_S 0 2708#define TIMPANI_PA_MASTER_BIAS_CUR_M 0xFF 2709 2710 2711#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_S 7 2712#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_M 0x80 2713#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_2_5UA 0x1 2714#define TIMPANI_PA_MASTER_BIAS_CUR_RAMPGEN_MASTER_BIAS_CUR_V_5UA 0x0 2715 2716#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_S 5 2717#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_M 0x60 2718#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_10UA 0x0 2719#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_7_5UA 0x1 2720#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_5_0UA 0x2 2721#define TIMPANI_PA_MASTER_BIAS_CUR_AUXPGA_BIAS_CUR_V_2_5UA 0x3 2722 2723#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_S 3 2724#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_M 0x18 2725#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0 2726#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1 2727#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2 2728#define TIMPANI_PA_MASTER_BIAS_CUR_HPH_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3 2729 2730#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_S 1 2731#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_M 0x6 2732#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_6_25UA 0x0 2733#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_5_0UA 0x1 2734#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_3_75UA 0x2 2735#define TIMPANI_PA_MASTER_BIAS_CUR_LINE_VCM_BUFF_BIAS_CURR_V_2_5UA 0x3 2736 2737#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_S 0 2738#define TIMPANI_PA_MASTER_BIAS_CUR_RESERVED_M 0x1 2739 2740 2741/* -- For PA_CLASSD_SC_STATUS */ 2742#define TIMPANI_A_PA_CLASSD_SC_STATUS (0x51) 2743#define TIMPANI_PA_CLASSD_SC_STATUS_RWC "R" 2744#define TIMPANI_PA_CLASSD_SC_STATUS_POR 0 2745#define TIMPANI_PA_CLASSD_SC_STATUS_S 0 2746#define TIMPANI_PA_CLASSD_SC_STATUS_M 0xFF 2747 2748 2749#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_S 7 2750#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_M 0x80 2751#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_NORMAL_OP 0x0 2752#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_SC_DET_SC_DET 0x1 2753 2754#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_S 6 2755#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_M 0x40 2756#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_NORMAL_OP 0x0 2757#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_L_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1 2758 2759#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_S 4 2760#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_1_M 0x30 2761 2762#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_S 3 2763#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_M 0x8 2764#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_NORMAL_OP 0x0 2765#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_SC_DET_SC_DET 0x1 2766 2767#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_S 2 2768#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_M 0x4 2769#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_NORMAL_OP 0x0 2770#define TIMPANI_PA_CLASSD_SC_STATUS_CLASSD_R_PWR_STAGE_HI_Z_POWER_STAGE_OFF 0x1 2771 2772#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_S 1 2773#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_2_M 0x2 2774 2775#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_S 0 2776#define TIMPANI_PA_CLASSD_SC_STATUS_RESERVED_M 0x1 2777 2778 2779/* -- For PA_HPH_SC_STATUS */ 2780#define TIMPANI_A_PA_HPH_SC_STATUS (0x52) 2781#define TIMPANI_PA_HPH_SC_STATUS_RWC "R" 2782#define TIMPANI_PA_HPH_SC_STATUS_POR 0 2783#define TIMPANI_PA_HPH_SC_STATUS_S 0 2784#define TIMPANI_PA_HPH_SC_STATUS_M 0xFF 2785 2786 2787#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_S 7 2788#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_M 0x80 2789#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_NORMAL_OP 0x0 2790#define TIMPANI_PA_HPH_SC_STATUS_HPH_L_SC_DET_SC_DET 0x1 2791 2792#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_S 4 2793#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_1_M 0x70 2794 2795#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_S 3 2796#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_M 0x8 2797#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_NORMAL_OP 0x0 2798#define TIMPANI_PA_HPH_SC_STATUS_HPH_R_SC_DET_SC_DET 0x1 2799 2800#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_S 2 2801#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_2_M 0x4 2802 2803#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_S 0 2804#define TIMPANI_PA_HPH_SC_STATUS_RESERVED_M 0x3 2805 2806 2807/* -- For ATEST_EN */ 2808#define TIMPANI_A_ATEST_EN (0x53) 2809#define TIMPANI_ATEST_EN_RWC "RW" 2810#define TIMPANI_ATEST_EN_POR 0 2811#define TIMPANI_ATEST_EN_S 0 2812#define TIMPANI_ATEST_EN_M 0xFF 2813 2814 2815#define TIMPANI_ATEST_EN_ATEST_EN_S 7 2816#define TIMPANI_ATEST_EN_ATEST_EN_M 0x80 2817#define TIMPANI_ATEST_EN_ATEST_EN_DISABLE 0x0 2818#define TIMPANI_ATEST_EN_ATEST_EN_ENABLE 0x1 2819 2820#define TIMPANI_ATEST_EN_RESERVED_S 0 2821#define TIMPANI_ATEST_EN_RESERVED_M 0x7F 2822 2823 2824/* -- For ATEST_TSHKADC */ 2825#define TIMPANI_A_ATEST_TSHKADC (0x54) 2826#define TIMPANI_ATEST_TSHKADC_RWC "RW" 2827#define TIMPANI_ATEST_TSHKADC_POR 0 2828#define TIMPANI_ATEST_TSHKADC_S 0 2829#define TIMPANI_ATEST_TSHKADC_M 0xFF 2830 2831 2832#define TIMPANI_ATEST_TSHKADC_RESERVED_S 4 2833#define TIMPANI_ATEST_TSHKADC_RESERVED_M 0xF0 2834 2835#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_S 2 2836#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_M 0xC 2837#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_NO_CONNECT 0x0 2838#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX1 0x1 2839#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX2 0x2 2840#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_AN_CONN_MUX3 0x3 2841 2842#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_S 0 2843#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_M 0x3 2844#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_NO_CONNECT 0x0 2845#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX1 0x1 2846#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX2 0x2 2847#define TIMPANI_ATEST_TSHKADC_ATEST_TSADC_DIG_CONN_MUX3 0x3 2848 2849 2850/* -- For ATEST_TXADC13 */ 2851#define TIMPANI_A_ATEST_TXADC13 (0x55) 2852#define TIMPANI_ATEST_TXADC13_RWC "RW" 2853#define TIMPANI_ATEST_TXADC13_POR 0 2854#define TIMPANI_ATEST_TXADC13_S 0 2855#define TIMPANI_ATEST_TXADC13_M 0xFF 2856 2857 2858#define TIMPANI_ATEST_TXADC13_RESERVED_S 7 2859#define TIMPANI_ATEST_TXADC13_RESERVED_M 0x80 2860 2861#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_S 6 2862#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_M 0x40 2863#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC1 0x0 2864#define TIMPANI_ATEST_TXADC13_ATEST_SEL_L_TXADC3 0x1 2865 2866#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_S 3 2867#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_M 0x38 2868#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_NO_CONNECT 0x0 2869#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_ICMP1_TO_ATEST1 0x1 2870#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA2_TO_ATEST1 0x2 2871#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_IOTA1_TO_ATEST1 0x3 2872#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VICM_TO_ATEST1 0x4 2873#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VTH_P_TO_ATEST1 0x5 2874#define TIMPANI_ATEST_TXADC13_ATEST1_TXADC13_CONN_VREFP_TO_ATEST1 0x6 2875 2876#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_S 0 2877#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_M 0x7 2878#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_NO_CONNECT 0x0 2879#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IDACREF_TO_ATEST2 0x1 2880#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_IB_10U_TO_ATEST2 0x2 2881#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFMID_TO_ATEST2 0x3 2882#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VOCM_TO_ATEST2 0x4 2883#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VTH_N_TO_ATEST2 0x5 2884#define TIMPANI_ATEST_TXADC13_ATEST2_TXADC13_CONN_VREFN_TO_ATEST2 0x6 2885 2886 2887/* -- For ATEST_TXADC24 */ 2888#define TIMPANI_A_ATEST_TXADC24 (0x56) 2889#define TIMPANI_ATEST_TXADC24_RWC "RW" 2890#define TIMPANI_ATEST_TXADC24_POR 0 2891#define TIMPANI_ATEST_TXADC24_S 0 2892#define TIMPANI_ATEST_TXADC24_M 0xFF 2893 2894 2895#define TIMPANI_ATEST_TXADC24_RESERVED_S 7 2896#define TIMPANI_ATEST_TXADC24_RESERVED_M 0x80 2897 2898#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_S 6 2899#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_M 0x40 2900#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC1 0x0 2901#define TIMPANI_ATEST_TXADC24_ATEST_SEL_R_TXADC3 0x1 2902 2903#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_S 3 2904#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_M 0x38 2905#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_NO_CONNECT 0x0 2906#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_ICMP1_TO_ATEST1 0x1 2907#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA2_TO_ATEST1 0x2 2908#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_IOTA1_TO_ATEST1 0x3 2909#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VICM_TO_ATEST1 0x4 2910#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VTH_P_TO_ATEST1 0x5 2911#define TIMPANI_ATEST_TXADC24_ATEST1_TXADC24_CONN_VREFP_TO_ATEST1 0x6 2912 2913#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_S 0 2914#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_M 0x7 2915#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_NO_CONNECT 0x0 2916#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IDACREF_TO_ATEST2 0x1 2917#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_IB_10U_TO_ATEST2 0x2 2918#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFMID_TO_ATEST2 0x3 2919#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VOCM_TO_ATEST2 0x4 2920#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VTH_N_TO_ATEST2 0x5 2921#define TIMPANI_ATEST_TXADC24_ATEST2_TXADC24_CONN_VREFN_TO_ATEST2 0x6 2922 2923 2924/* -- For ATEST_AUXPGA */ 2925#define TIMPANI_A_ATEST_AUXPGA (0x57) 2926#define TIMPANI_ATEST_AUXPGA_RWC "RW" 2927#define TIMPANI_ATEST_AUXPGA_POR 0 2928#define TIMPANI_ATEST_AUXPGA_S 0 2929#define TIMPANI_ATEST_AUXPGA_M 0xFF 2930 2931 2932#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_S 7 2933#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_M 0x80 2934#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_NO_CONNECT 0x0 2935#define TIMPANI_ATEST_AUXPGA_ATEST1_AUXPGA_INT_VCM_CONN_CONNECT 0x1 2936 2937#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_S 6 2938#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_M 0x40 2939#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_NO_CONNECT 0x0 2940#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMI_VDD_CONN_CONNECT 0x1 2941 2942#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_S 5 2943#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_M 0x20 2944#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_NO_CONNECT 0x0 2945#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_VCMO_R_L_CONN_CONNECT 0x1 2946 2947#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_S 4 2948#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_M 0x10 2949#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_NO_CONNECT 0x0 2950#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_R_CONN_CONNECT 0x1 2951 2952#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_S 3 2953#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_M 0x8 2954#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_NO_CONNECT 0x0 2955#define TIMPANI_ATEST_AUXPGA_ATEST_AUXPGA_L_CONN_CONNECT 0x1 2956 2957#define TIMPANI_ATEST_AUXPGA_RESERVED_S 0 2958#define TIMPANI_ATEST_AUXPGA_RESERVED_M 0x7 2959 2960 2961/* -- For ATEST_CDAC */ 2962#define TIMPANI_A_ATEST_CDAC (0x58) 2963#define TIMPANI_ATEST_CDAC_RWC "RW" 2964#define TIMPANI_ATEST_CDAC_POR 0 2965#define TIMPANI_ATEST_CDAC_S 0 2966#define TIMPANI_ATEST_CDAC_M 0xFF 2967 2968 2969#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_S 7 2970#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_M 0x80 2971#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_NO_CONNECT 0x0 2972#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_IN_CONN_CONNECT 0x1 2973 2974#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_S 6 2975#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_M 0x40 2976#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_NO_CONNECT 0x0 2977#define TIMPANI_ATEST_CDAC_ATEST_CDAC_DWA_OUT_CONN_CONNECT 0x1 2978 2979#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_S 5 2980#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_M 0x20 2981#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_NO_CONNECT 0x0 2982#define TIMPANI_ATEST_CDAC_ATEST_FILTER_L_OUT_CONN_CONNECT 0x1 2983 2984#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_S 4 2985#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_M 0x10 2986#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_NO_CONNECT 0x0 2987#define TIMPANI_ATEST_CDAC_ATEST_FILTER_R_OUT_CONN_CONNECT 0x1 2988 2989#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_S 2 2990#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_M 0xC 2991#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_NO_CONNECT 0x0 2992#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST1 0x1 2993#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST2 0x2 2994#define TIMPANI_ATEST_CDAC_ATEST_CDAC_L_CONN_TEST3 0x3 2995 2996#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_S 0 2997#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_M 0x3 2998#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_NO_CONNECT 0x0 2999#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST1 0x1 3000#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST2 0x2 3001#define TIMPANI_ATEST_CDAC_ATEST_CDAC_R_CONN_TEST3 0x3 3002 3003 3004/* -- For ATEST_IDAC */ 3005#define TIMPANI_A_ATEST_IDAC (0x59) 3006#define TIMPANI_ATEST_IDAC_RWC "RW" 3007#define TIMPANI_ATEST_IDAC_POR 0 3008#define TIMPANI_ATEST_IDAC_S 0 3009#define TIMPANI_ATEST_IDAC_M 0xFF 3010 3011 3012#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_S 7 3013#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_M 0x80 3014#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_RIGHT 0x1 3015#define TIMPANI_ATEST_IDAC_ATEST1_LR_CONN_LEFT 0x0 3016 3017#define TIMPANI_ATEST_IDAC_ATEST1_CONN_S 4 3018#define TIMPANI_ATEST_IDAC_ATEST1_CONN_M 0x70 3019#define TIMPANI_ATEST_IDAC_ATEST1_CONN_IDAC_NEG_OUT 0x7 3020#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_POS_OUT 0x6 3021#define TIMPANI_ATEST_IDAC_ATEST1_CONN_CT_FILTER_IBIAS 0x5 3022#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_1 0x4 3023#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_2 0x3 3024#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_3 0x2 3025#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_4 0x1 3026#define TIMPANI_ATEST_IDAC_ATEST1_CONN_NO_CONNECT_5 0x0 3027 3028#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_S 3 3029#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_M 0x8 3030#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_RIGHT 0x1 3031#define TIMPANI_ATEST_IDAC_ATEST2_LR_CONN_LEFT 0x0 3032 3033#define TIMPANI_ATEST_IDAC_ATEST2_CONN_S 0 3034#define TIMPANI_ATEST_IDAC_ATEST2_CONN_M 0x7 3035#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_POS_OUT 0x7 3036#define TIMPANI_ATEST_IDAC_ATEST2_CONN_CT_FILTER_NEG_OUT 0x6 3037#define TIMPANI_ATEST_IDAC_ATEST2_CONN_IDAC_IBIAS 0x5 3038#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_1 0x4 3039#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_2 0x3 3040#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_3 0x2 3041#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_4 0x1 3042#define TIMPANI_ATEST_IDAC_ATEST2_CONN_NO_CONNECT_5 0x0 3043 3044 3045/* -- For ATEST_PA1 */ 3046#define TIMPANI_A_ATEST_PA1 (0x5A) 3047#define TIMPANI_ATEST_PA1_RWC "RW" 3048#define TIMPANI_ATEST_PA1_POR 0 3049#define TIMPANI_ATEST_PA1_S 0 3050#define TIMPANI_ATEST_PA1_M 0xFF 3051 3052 3053#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_S 7 3054#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_M 0x80 3055#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_NO_CONNECT 0x0 3056#define TIMPANI_ATEST_PA1_ATEST_EARPA_FSV_NP_CONN_EN 0x1 3057 3058#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_S 6 3059#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_M 0x40 3060#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_NO_CONNECT 0x0 3061#define TIMPANI_ATEST_PA1_ATEST_EARPA_NCASC_NMIRR_CONN_EN 0x1 3062 3063#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_S 5 3064#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_M 0x20 3065#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_NO_CONNECT 0x0 3066#define TIMPANI_ATEST_PA1_ATEST_EARPA_NMIRR_PCASC_CONN_EN 0x1 3067 3068#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_S 4 3069#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_M 0x10 3070#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_NO_CONNECT 0x0 3071#define TIMPANI_ATEST_PA1_ATEST_EARPA_VCM_PTAIL1_CONN_EN 0x1 3072 3073#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_S 3 3074#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_M 0x8 3075#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_NO_CONNECT 0x0 3076#define TIMPANI_ATEST_PA1_ATEST_EARPA_IBTEST_VSS2P2_CONN_EN 0x1 3077 3078#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_S 2 3079#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_M 0x4 3080#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_NO_CONNECT 0x0 3081#define TIMPANI_ATEST_PA1_ATEST_EARPA_ITEST1_ITEST2_CONN_EN 0x1 3082 3083#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_S 1 3084#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_M 0x2 3085#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_PASS 0x0 3086#define TIMPANI_ATEST_PA1_ATEST_CLASSD_CLK_GATING_GATE 0x1 3087 3088#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_S 0 3089#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_M 0x1 3090#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_NO_CONNECT 0x0 3091#define TIMPANI_ATEST_PA1_ATEST2_HPH_VCM_CONN_CONNECT 0x1 3092 3093 3094/* -- For ATEST_CLASSD */ 3095#define TIMPANI_A_ATEST_CLASSD (0x5B) 3096#define TIMPANI_ATEST_CLASSD_RWC "RW" 3097#define TIMPANI_ATEST_CLASSD_POR 0 3098#define TIMPANI_ATEST_CLASSD_S 0 3099#define TIMPANI_ATEST_CLASSD_M 0xFF 3100 3101 3102#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_S 4 3103#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_M 0xF0 3104#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_1 0x0 3105#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_SC_OCP 0x1 3106#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_CDAC_CLK 0x2 3107#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_POS_CDAC 0x3 3108#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_BREAK_BEFORE_MAKE_OUT_CP 0x4 3109#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_COMP_OUT 0x5 3110#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT2_POS_OUT 0x6 3111#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_L_INT1_POS_OUT 0x7 3112#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_NO_CONNECT_2 0x8 3113#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_SC_OCP_SIGNAL 0x9 3114#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_CDAC_CLK 0xA 3115#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_POS_CDAC 0xB 3116#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_BREAK_BEFORE_MAKE_OUT_CP 0xC 3117#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_COMP_OUT 0xD 3118#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT2_POS_OUT 0xE 3119#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST1_CONN_R_INT1_POS_OUT 0xF 3120 3121#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_S 0 3122#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_M 0xF 3123#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_1 0x0 3124#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_HI_Z_OCP 0x1 3125#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_OCP_CLOCK 0x2 3126#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_NEG_CDAC 0x3 3127#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_BREAK_BEFORE_MAKE_OUT_CN 0x4 3128#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_CM_BUFF_OUT 0x5 3129#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT2_NEG_OUT 0x6 3130#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_L_INT1_NEG_OUT 0x7 3131#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_NO_CONNECT_2 0x8 3132#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_HI_Z_OCP 0x9 3133#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_OCP_CLOCK 0xA 3134#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_NEGATIVE_CDAC 0xB 3135#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_BREAK_BEFORE_MAKE_OUT_CN 0xC 3136#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_CM_BUFF_OUT 0xD 3137#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INTR2_NEG_OUT 0xE 3138#define TIMPANI_ATEST_CLASSD_CLASSD_ATEST2_CONN_R_INT1_NEG_OUT 0xF 3139 3140 3141/* -- For ATEST_LINEO_AUXO */ 3142#define TIMPANI_A_ATEST_LINEO_AUXO (0x5C) 3143#define TIMPANI_ATEST_LINEO_AUXO_RWC "RW" 3144#define TIMPANI_ATEST_LINEO_AUXO_POR 0 3145#define TIMPANI_ATEST_LINEO_AUXO_S 0 3146#define TIMPANI_ATEST_LINEO_AUXO_M 0xFF 3147 3148 3149#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_S 7 3150#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_M 0x80 3151#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_DISABLE 0x0 3152#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_EN_ENABLE 0x1 3153 3154#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_S 6 3155#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_M 0x40 3156#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_NO_CONNECT 0x0 3157#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_AUXO_VCM_CONN_CONNECT 0x1 3158 3159#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_S 5 3160#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_M 0x20 3161#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_NO_CONNECT 0x0 3162#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NREFIN_STG1OP_CONN_EN 0x1 3163 3164#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_S 4 3165#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_M 0x10 3166#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_NO_CONNECT 0x0 3167#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_L_NMOS_PMOS_CONN_EN 01 3168 3169#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_S 3 3170#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_M 0x8 3171#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_NO_CONNECT 0x0 3172#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NREFIN_STG1OP_CONN_EN 01 3173 3174#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_S 2 3175#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_M 0x4 3176#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_DISABLE 0x0 3177#define TIMPANI_ATEST_LINEO_AUXO_ATEST_LINEO_R_NMOS_PMOS_CONN_EN 0x1 3178 3179#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_S 1 3180#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_M 0x2 3181#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_DISABLE 0x0 3182#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NREFIN_STG1OP_CONN_EN 0x1 3183 3184#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_S 0 3185#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_M 0x1 3186#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_DISABLE 0x0 3187#define TIMPANI_ATEST_LINEO_AUXO_ATEST_AUXO_NMOS_PMOS_CONN_EN 0x1 3188 3189 3190/* -- For CDC_RESET_CTL */ 3191#define TIMPANI_A_CDC_RESET_CTL (0x80) 3192#define TIMPANI_CDC_RESET_CTL_RWC "RW" 3193#define TIMPANI_CDC_RESET_CTL_POR 0 3194#define TIMPANI_CDC_RESET_CTL_S 0 3195#define TIMPANI_CDC_RESET_CTL_M 0x7F 3196 3197 3198#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_S 6 3199#define TIMPANI_CDC_RESET_CTL_ARB_SOFT_RESET_M 0x40 3200 3201#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_S 5 3202#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_R_M 0x20 3203 3204#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_S 4 3205#define TIMPANI_CDC_RESET_CTL_TX2_SOFT_RESET_L_M 0x10 3206 3207#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_S 3 3208#define TIMPANI_CDC_RESET_CTL_RX2_SOFT_RESET_M 0x8 3209 3210#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_S 2 3211#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_R_M 0x4 3212 3213#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_S 1 3214#define TIMPANI_CDC_RESET_CTL_RX1_SOFT_RESET_M 0x2 3215 3216#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_S 0 3217#define TIMPANI_CDC_RESET_CTL_TX1_SOFT_RESET_L_M 0x1 3218 3219 3220/* -- For CDC_RX1_CTL */ 3221#define TIMPANI_A_CDC_RX1_CTL (0x81) 3222#define TIMPANI_CDC_RX1_CTL_RWC "RW" 3223#define TIMPANI_CDC_RX1_CTL_POR 0xc 3224#define TIMPANI_CDC_RX1_CTL_S 0 3225#define TIMPANI_CDC_RX1_CTL_M 0x3F 3226 3227 3228#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_S 5 3229#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_R_M 0x20 3230 3231#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_S 4 3232#define TIMPANI_CDC_RX1_CTL_SIDETONE_EN1_L_M 0x10 3233 3234#define TIMPANI_CDC_RX1_CTL_RX1_RATE_S 2 3235#define TIMPANI_CDC_RX1_CTL_RX1_RATE_M 0xC 3236#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_256 0x3 3237#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_128 0x1 3238#define TIMPANI_CDC_RX1_CTL_RX1_RATE_OSR_64 0x0 3239 3240#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_S 1 3241#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_M 0x2 3242#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_32 0x1 3243#define TIMPANI_CDC_RX1_CTL_RX1_I2S_RATE_BR_64 0x0 3244 3245#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_S 0 3246#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_M 0x1 3247#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_MASTER 0x1 3248#define TIMPANI_CDC_RX1_CTL_RX1_I2S_MODE_SLAVE 0x0 3249 3250 3251/* -- For CDC_TX_I2S_CTL */ 3252#define TIMPANI_A_CDC_TX_I2S_CTL (0x82) 3253#define TIMPANI_CDC_TX_I2S_CTL_RWC "RW" 3254#define TIMPANI_CDC_TX_I2S_CTL_POR 0xc 3255#define TIMPANI_CDC_TX_I2S_CTL_S 0 3256#define TIMPANI_CDC_TX_I2S_CTL_M 0x3F 3257 3258 3259#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_S 5 3260#define TIMPANI_CDC_TX_I2S_CTL_TX2_I2S_SD_OE_M 0x20 3261 3262#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_S 4 3263#define TIMPANI_CDC_TX_I2S_CTL_TX1_I2S_SD_OE_M 0x10 3264 3265#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_S 2 3266#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_M 0xC 3267#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_256 0x3 3268#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_128 0x1 3269#define TIMPANI_CDC_TX_I2S_CTL_TX_RATE_OSR_64 0x0 3270 3271#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_S 1 3272#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_M 0x2 3273#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_32 0x1 3274#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_RATE_BR_64 0x0 3275 3276#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_S 0 3277#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_M 0x1 3278#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_MASTER 0x1 3279#define TIMPANI_CDC_TX_I2S_CTL_TX_I2S_MODE_SLAVE 0x0 3280 3281 3282/* -- For CDC_CH_CTL */ 3283#define TIMPANI_A_CDC_CH_CTL (0x83) 3284#define TIMPANI_CDC_CH_CTL_RWC "RW" 3285#define TIMPANI_CDC_CH_CTL_POR 0 3286#define TIMPANI_CDC_CH_CTL_S 0 3287#define TIMPANI_CDC_CH_CTL_M 0xFF 3288 3289 3290#define TIMPANI_CDC_CH_CTL_TX2_EN_R_S 7 3291#define TIMPANI_CDC_CH_CTL_TX2_EN_R_M 0x80 3292 3293#define TIMPANI_CDC_CH_CTL_TX2_EN_L_S 6 3294#define TIMPANI_CDC_CH_CTL_TX2_EN_L_M 0x40 3295 3296#define TIMPANI_CDC_CH_CTL_RX2_EN_R_S 5 3297#define TIMPANI_CDC_CH_CTL_RX2_EN_R_M 0x20 3298 3299#define TIMPANI_CDC_CH_CTL_RX2_EN_L_S 4 3300#define TIMPANI_CDC_CH_CTL_RX2_EN_L_M 0x10 3301 3302#define TIMPANI_CDC_CH_CTL_TX1_EN_R_S 3 3303#define TIMPANI_CDC_CH_CTL_TX1_EN_R_M 0x8 3304 3305#define TIMPANI_CDC_CH_CTL_TX1_EN_L_S 2 3306#define TIMPANI_CDC_CH_CTL_TX1_EN_L_M 0x4 3307 3308#define TIMPANI_CDC_CH_CTL_RX1_EN_R_S 1 3309#define TIMPANI_CDC_CH_CTL_RX1_EN_R_M 0x2 3310 3311#define TIMPANI_CDC_CH_CTL_RX1_EN_L_S 0 3312#define TIMPANI_CDC_CH_CTL_RX1_EN_L_M 0x1 3313 3314 3315/* -- For CDC_RX1LG */ 3316#define TIMPANI_A_CDC_RX1LG (0x84) 3317#define TIMPANI_CDC_RX1LG_RWC "RW" 3318#define TIMPANI_CDC_RX1LG_POR 0xac 3319#define TIMPANI_CDC_RX1LG_S 0 3320#define TIMPANI_CDC_RX1LG_M 0xFF 3321 3322 3323#define TIMPANI_CDC_RX1LG_GAIN_S 0 3324#define TIMPANI_CDC_RX1LG_GAIN_M 0xFF 3325 3326 3327/* -- For CDC_RX1RG */ 3328#define TIMPANI_A_CDC_RX1RG (0x85) 3329#define TIMPANI_CDC_RX1RG_RWC "RW" 3330#define TIMPANI_CDC_RX1RG_POR 0xac 3331#define TIMPANI_CDC_RX1RG_S 0 3332#define TIMPANI_CDC_RX1RG_M 0xFF 3333 3334 3335#define TIMPANI_CDC_RX1RG_GAIN_S 0 3336#define TIMPANI_CDC_RX1RG_GAIN_M 0xFF 3337 3338 3339/* -- For CDC_TX1LG */ 3340#define TIMPANI_A_CDC_TX1LG (0x86) 3341#define TIMPANI_CDC_TX1LG_RWC "RW" 3342#define TIMPANI_CDC_TX1LG_POR 0xac 3343#define TIMPANI_CDC_TX1LG_S 0 3344#define TIMPANI_CDC_TX1LG_M 0xFF 3345 3346 3347#define TIMPANI_CDC_TX1LG_GAIN_S 0 3348#define TIMPANI_CDC_TX1LG_GAIN_M 0xFF 3349 3350 3351/* -- For CDC_TX1RG */ 3352#define TIMPANI_A_CDC_TX1RG (0x87) 3353#define TIMPANI_CDC_TX1RG_RWC "RW" 3354#define TIMPANI_CDC_TX1RG_POR 0xac 3355#define TIMPANI_CDC_TX1RG_S 0 3356#define TIMPANI_CDC_TX1RG_M 0xFF 3357 3358 3359#define TIMPANI_CDC_TX1RG_GAIN_S 0 3360#define TIMPANI_CDC_TX1RG_GAIN_M 0xFF 3361 3362 3363/* -- For CDC_RX_PGA_TIMER */ 3364#define TIMPANI_A_CDC_RX_PGA_TIMER (0x88) 3365#define TIMPANI_CDC_RX_PGA_TIMER_RWC "RW" 3366#define TIMPANI_CDC_RX_PGA_TIMER_POR 0xff 3367#define TIMPANI_CDC_RX_PGA_TIMER_S 0 3368#define TIMPANI_CDC_RX_PGA_TIMER_M 0xFF 3369 3370 3371#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_S 0 3372#define TIMPANI_CDC_RX_PGA_TIMER_TIMER_VAL_M 0xFF 3373 3374 3375/* -- For CDC_TX_PGA_TIMER */ 3376#define TIMPANI_A_CDC_TX_PGA_TIMER (0x89) 3377#define TIMPANI_CDC_TX_PGA_TIMER_RWC "RW" 3378#define TIMPANI_CDC_TX_PGA_TIMER_POR 0xff 3379#define TIMPANI_CDC_TX_PGA_TIMER_S 0 3380#define TIMPANI_CDC_TX_PGA_TIMER_M 0xFF 3381 3382 3383#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_S 0 3384#define TIMPANI_CDC_TX_PGA_TIMER_TIMER_VAL_M 0xFF 3385 3386 3387/* -- For CDC_GCTL1 */ 3388#define TIMPANI_A_CDC_GCTL1 (0x8A) 3389#define TIMPANI_CDC_GCTL1_RWC "RW" 3390#define TIMPANI_CDC_GCTL1_POR 0x33 3391#define TIMPANI_CDC_GCTL1_S 0 3392#define TIMPANI_CDC_GCTL1_M 0xFF 3393 3394 3395#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_S 7 3396#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_R_M 0x80 3397 3398#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_S 6 3399#define TIMPANI_CDC_GCTL1_TX1_PGA_UPDATE_L_M 0x40 3400 3401#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_S 5 3402#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_R_M 0x20 3403 3404#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_S 4 3405#define TIMPANI_CDC_GCTL1_TX1_PGA_MUTE_EN_L_M 0x10 3406 3407#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_S 3 3408#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_R_M 0x8 3409 3410#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_S 2 3411#define TIMPANI_CDC_GCTL1_RX1_PGA_UPDATE_L_M 0x4 3412 3413#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_S 1 3414#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_R_M 0x2 3415 3416#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_S 0 3417#define TIMPANI_CDC_GCTL1_RX1_PGA_MUTE_EN_L_M 0x1 3418 3419 3420/* -- For CDC_TX1L_STG */ 3421#define TIMPANI_A_CDC_TX1L_STG (0x8B) 3422#define TIMPANI_CDC_TX1L_STG_RWC "RW" 3423#define TIMPANI_CDC_TX1L_STG_POR 0xac 3424#define TIMPANI_CDC_TX1L_STG_S 0 3425#define TIMPANI_CDC_TX1L_STG_M 0xFF 3426 3427 3428#define TIMPANI_CDC_TX1L_STG_GAIN_S 0 3429#define TIMPANI_CDC_TX1L_STG_GAIN_M 0xFF 3430 3431 3432/* -- For CDC_ST_CTL */ 3433#define TIMPANI_A_CDC_ST_CTL (0x8C) 3434#define TIMPANI_CDC_ST_CTL_RWC "RW" 3435#define TIMPANI_CDC_ST_CTL_POR 0x55 3436#define TIMPANI_CDC_ST_CTL_S 0 3437#define TIMPANI_CDC_ST_CTL_M 0xFF 3438 3439 3440#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_S 7 3441#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_UPDATE_M 0x80 3442 3443#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_S 6 3444#define TIMPANI_CDC_ST_CTL_TX2_R_SIDETONE_MUTE_EN_M 0x40 3445 3446#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_S 5 3447#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_UPDATE_M 0x20 3448 3449#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_S 4 3450#define TIMPANI_CDC_ST_CTL_TX2_L_SIDETONE_MUTE_EN_M 0x10 3451 3452#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_S 3 3453#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_UPDATE_M 0x8 3454 3455#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_S 2 3456#define TIMPANI_CDC_ST_CTL_TX1_R_SIDETONE_MUTE_EN_M 0x4 3457 3458#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_S 1 3459#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_UPDATE_M 0x2 3460 3461#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_S 0 3462#define TIMPANI_CDC_ST_CTL_TX1_L_SIDETONE_MUTE_EN_M 0x1 3463 3464 3465/* -- For CDC_RX1L_DCOFFSET */ 3466#define TIMPANI_A_CDC_RX1L_DCOFFSET (0x8D) 3467#define TIMPANI_CDC_RX1L_DCOFFSET_RWC "RW" 3468#define TIMPANI_CDC_RX1L_DCOFFSET_POR 0 3469#define TIMPANI_CDC_RX1L_DCOFFSET_S 0 3470#define TIMPANI_CDC_RX1L_DCOFFSET_M 0xFF 3471 3472 3473#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_S 0 3474#define TIMPANI_CDC_RX1L_DCOFFSET_OFFSET_M 0xFF 3475 3476 3477/* -- For CDC_RX1R_DCOFFSET */ 3478#define TIMPANI_A_CDC_RX1R_DCOFFSET (0x8E) 3479#define TIMPANI_CDC_RX1R_DCOFFSET_RWC "RW" 3480#define TIMPANI_CDC_RX1R_DCOFFSET_POR 0 3481#define TIMPANI_CDC_RX1R_DCOFFSET_S 0 3482#define TIMPANI_CDC_RX1R_DCOFFSET_M 0xFF 3483 3484 3485#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_S 0 3486#define TIMPANI_CDC_RX1R_DCOFFSET_OFFSET_M 0xFF 3487 3488 3489/* -- For CDC_BYPASS_CTL1 */ 3490#define TIMPANI_A_CDC_BYPASS_CTL1 (0x8F) 3491#define TIMPANI_CDC_BYPASS_CTL1_RWC "RW" 3492#define TIMPANI_CDC_BYPASS_CTL1_POR 0x2 3493#define TIMPANI_CDC_BYPASS_CTL1_S 0 3494#define TIMPANI_CDC_BYPASS_CTL1_M 0xF 3495 3496 3497#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_S 3 3498#define TIMPANI_CDC_BYPASS_CTL1_DITHER_BP_M 0x8 3499 3500#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_S 2 3501#define TIMPANI_CDC_BYPASS_CTL1_DITHER_SHAPE_SEL_M 0x4 3502 3503#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_S 1 3504#define TIMPANI_CDC_BYPASS_CTL1_DITHER_DLY_SEL_M 0x2 3505 3506#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_S 0 3507#define TIMPANI_CDC_BYPASS_CTL1_RX1_HPF_BP_M 0x1 3508 3509 3510/* -- For CDC_PDM_CONFIG */ 3511#define TIMPANI_A_CDC_PDM_CONFIG (0x90) 3512#define TIMPANI_CDC_PDM_CONFIG_RWC "RW" 3513#define TIMPANI_CDC_PDM_CONFIG_POR 0 3514#define TIMPANI_CDC_PDM_CONFIG_S 0 3515#define TIMPANI_CDC_PDM_CONFIG_M 0xF 3516 3517 3518#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_S 0 3519#define TIMPANI_CDC_PDM_CONFIG_PDM_SEL_M 0xF 3520 3521 3522/* -- For CDC_TESTMODE1 */ 3523#define TIMPANI_A_CDC_TESTMODE1 (0x91) 3524#define TIMPANI_CDC_TESTMODE1_RWC "RW" 3525#define TIMPANI_CDC_TESTMODE1_POR 0 3526#define TIMPANI_CDC_TESTMODE1_S 0 3527#define TIMPANI_CDC_TESTMODE1_M 0x3F 3528 3529 3530#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_S 5 3531#define TIMPANI_CDC_TESTMODE1_COMP_I2C_TEST_EN_M 0x20 3532 3533#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_S 4 3534#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_R_M 0x10 3535 3536#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_S 3 3537#define TIMPANI_CDC_TESTMODE1_RX1_TEST_EN_L_M 0x8 3538 3539#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_S 2 3540#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_R_M 0x4 3541 3542#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_S 1 3543#define TIMPANI_CDC_TESTMODE1_TX1_TEST_EN_L_M 0x2 3544 3545#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_S 0 3546#define TIMPANI_CDC_TESTMODE1_A_LOOPBACK_EN1_M 0x1 3547 3548 3549/* -- For CDC_DMIC_CLK_CTL */ 3550#define TIMPANI_A_CDC_DMIC_CLK_CTL (0x92) 3551#define TIMPANI_CDC_DMIC_CLK_CTL_RWC "RW" 3552#define TIMPANI_CDC_DMIC_CLK_CTL_POR 0 3553#define TIMPANI_CDC_DMIC_CLK_CTL_S 0 3554#define TIMPANI_CDC_DMIC_CLK_CTL_M 0x3F 3555 3556 3557#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_S 3 3558#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_M 0x38 3559#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_6 0x4 3560#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_4 0x3 3561#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_3 0x2 3562#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_2 0x1 3563#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_DIV_SEL_DIV_1 0x0 3564 3565#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_S 1 3566#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_M 0x6 3567#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK2 0x2 3568#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_RX_MCLK1 0x1 3569#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_MCLK_SEL_TX_MCLK 0x0 3570 3571#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_S 0 3572#define TIMPANI_CDC_DMIC_CLK_CTL_DMIC_CLK_EN_M 0x1 3573 3574 3575/* -- For CDC_ADC12_CLK_CTL */ 3576#define TIMPANI_A_CDC_ADC12_CLK_CTL (0x93) 3577#define TIMPANI_CDC_ADC12_CLK_CTL_RWC "RW" 3578#define TIMPANI_CDC_ADC12_CLK_CTL_POR 0 3579#define TIMPANI_CDC_ADC12_CLK_CTL_S 0 3580#define TIMPANI_CDC_ADC12_CLK_CTL_M 0xFF 3581 3582 3583#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_S 6 3584#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_M 0xC0 3585#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK2 0x2 3586#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_RX_MCLK1 0x1 3587#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_SEL_TX_MCLK 0x0 3588 3589#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_S 3 3590#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_M 0x38 3591#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_6 0x4 3592#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_4 0x3 3593#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_3 0x2 3594#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_2 0x1 3595#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_R_DIV_1 0x0 3596 3597#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_S 0 3598#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_M 0x7 3599#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_6 0x4 3600#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_4 0x3 3601#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_3 0x2 3602#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_2 0x1 3603#define TIMPANI_CDC_ADC12_CLK_CTL_TX1_MCLK_DIV_SEL_L_DIV_1 0x0 3604 3605 3606/* -- For CDC_TX1_CTL */ 3607#define TIMPANI_A_CDC_TX1_CTL (0x94) 3608#define TIMPANI_CDC_TX1_CTL_RWC "RW" 3609#define TIMPANI_CDC_TX1_CTL_POR 0x1b 3610#define TIMPANI_CDC_TX1_CTL_S 0 3611#define TIMPANI_CDC_TX1_CTL_M 0x3F 3612 3613 3614#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_S 5 3615#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_R_M 0x20 3616 3617#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_S 3 3618#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_M 0x18 3619#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_256 0x3 3620#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_128 0x1 3621#define TIMPANI_CDC_TX1_CTL_TX1_RATE_R_OSR_64 0x0 3622 3623#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_S 2 3624#define TIMPANI_CDC_TX1_CTL_TX1_DMIC_SEL_L_M 0x4 3625 3626#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_S 0 3627#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_M 0x3 3628#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_256 0x3 3629#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_128 0x1 3630#define TIMPANI_CDC_TX1_CTL_TX1_RATE_L_OSR_64 0x0 3631 3632 3633/* -- For CDC_ADC34_CLK_CTL */ 3634#define TIMPANI_A_CDC_ADC34_CLK_CTL (0x95) 3635#define TIMPANI_CDC_ADC34_CLK_CTL_RWC "RW" 3636#define TIMPANI_CDC_ADC34_CLK_CTL_POR 0 3637#define TIMPANI_CDC_ADC34_CLK_CTL_S 0 3638#define TIMPANI_CDC_ADC34_CLK_CTL_M 0xFF 3639 3640 3641#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_S 6 3642#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_M 0xC0 3643#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK2 0x2 3644#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_RX_MCLK1 0x1 3645#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_SEL_TX_MCLK 0x0 3646 3647#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_S 3 3648#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_M 0x38 3649#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_6 0x4 3650#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_4 0x3 3651#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_3 0x2 3652#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_2 0x1 3653#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_R_DIV_1 0x0 3654 3655#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_S 0 3656#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_M 0x7 3657#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_6 0x4 3658#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_4 0x3 3659#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_3 0x2 3660#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_2 0x1 3661#define TIMPANI_CDC_ADC34_CLK_CTL_TX2_MCLK_DIV_SEL_L_DIV_1 0x0 3662 3663 3664/* -- For CDC_TX2_CTL */ 3665#define TIMPANI_A_CDC_TX2_CTL (0x96) 3666#define TIMPANI_CDC_TX2_CTL_RWC "RW" 3667#define TIMPANI_CDC_TX2_CTL_POR 0x1b 3668#define TIMPANI_CDC_TX2_CTL_S 0 3669#define TIMPANI_CDC_TX2_CTL_M 0x3F 3670 3671 3672#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_S 5 3673#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_R_M 0x20 3674 3675#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_S 3 3676#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_M 0x18 3677#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_256 0x3 3678#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_128 0x1 3679#define TIMPANI_CDC_TX2_CTL_TX2_RATE_R_OSR_64 0x0 3680 3681#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_S 2 3682#define TIMPANI_CDC_TX2_CTL_TX2_DMIC_SEL_L_M 0x4 3683 3684#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_S 0 3685#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_M 0x3 3686#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_256 0x3 3687#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_128 0x1 3688#define TIMPANI_CDC_TX2_CTL_TX2_RATE_L_OSR_64 0x0 3689 3690 3691/* -- For CDC_RX1_CLK_CTL */ 3692#define TIMPANI_A_CDC_RX1_CLK_CTL (0x97) 3693#define TIMPANI_CDC_RX1_CLK_CTL_RWC "RW" 3694#define TIMPANI_CDC_RX1_CLK_CTL_POR 0x1 3695#define TIMPANI_CDC_RX1_CLK_CTL_S 0 3696#define TIMPANI_CDC_RX1_CLK_CTL_M 0x1F 3697 3698 3699#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_S 2 3700#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_M 0x1C 3701#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_6 0x4 3702#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_4 0x3 3703#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_3 0x2 3704#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_2 0x1 3705#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_DIV_SEL_DIV_1 0x0 3706 3707#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_S 0 3708#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_M 0x3 3709#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK2 0x2 3710#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_RX_MCLK1 0x1 3711#define TIMPANI_CDC_RX1_CLK_CTL_RX1_MCLK_SEL_TX_MCLK 0x0 3712 3713 3714/* -- For CDC_RX2_CLK_CTL */ 3715#define TIMPANI_A_CDC_RX2_CLK_CTL (0x98) 3716#define TIMPANI_CDC_RX2_CLK_CTL_RWC "RW" 3717#define TIMPANI_CDC_RX2_CLK_CTL_POR 0x2 3718#define TIMPANI_CDC_RX2_CLK_CTL_S 0 3719#define TIMPANI_CDC_RX2_CLK_CTL_M 0x1F 3720 3721 3722#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_S 2 3723#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_M 0x1C 3724#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_6 0x4 3725#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_4 0x3 3726#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_3 0x2 3727#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_2 0x1 3728#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_DIV_SEL_DIV_1 0x0 3729 3730#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_S 0 3731#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_M 0x3 3732#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK2 0x2 3733#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_RX_MCLK1 0x1 3734#define TIMPANI_CDC_RX2_CLK_CTL_RX2_MCLK_SEL_TX_MCLK 0x0 3735 3736 3737/* -- For CDC_DEC_ADC_SEL */ 3738#define TIMPANI_A_CDC_DEC_ADC_SEL (0x99) 3739#define TIMPANI_CDC_DEC_ADC_SEL_RWC "RW" 3740#define TIMPANI_CDC_DEC_ADC_SEL_POR 0 3741#define TIMPANI_CDC_DEC_ADC_SEL_S 0 3742#define TIMPANI_CDC_DEC_ADC_SEL_M 0xFF 3743 3744 3745#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_S 6 3746#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_M 0xC0 3747#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC4 0x3 3748#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC3 0x2 3749#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC2 0x1 3750#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_R_ADC1 0x0 3751 3752#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_S 4 3753#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_M 0x30 3754#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC4 0x3 3755#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC3 0x2 3756#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC2 0x1 3757#define TIMPANI_CDC_DEC_ADC_SEL_TX2_ADC_SEL_L_ADC1 0x0 3758 3759#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_S 2 3760#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_M 0xC 3761#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC4 0x3 3762#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC3 0x2 3763#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC2 0x1 3764#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_R_ADC1 0x0 3765 3766#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_S 0 3767#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_M 0x3 3768#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC4 0x3 3769#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC3 0x2 3770#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC2 0x1 3771#define TIMPANI_CDC_DEC_ADC_SEL_TX1_ADC_SEL_L_ADC1 0x0 3772 3773 3774/* -- For CDC_ANC_INPUT_MUX */ 3775#define TIMPANI_A_CDC_ANC_INPUT_MUX (0x9A) 3776#define TIMPANI_CDC_ANC_INPUT_MUX_RWC "RW" 3777#define TIMPANI_CDC_ANC_INPUT_MUX_POR 0 3778#define TIMPANI_CDC_ANC_INPUT_MUX_S 0 3779#define TIMPANI_CDC_ANC_INPUT_MUX_M 0xFF 3780 3781 3782#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_S 6 3783#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_M 0xC0 3784#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOR 0x3 3785#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX2DOL 0x2 3786#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOR 0x1 3787#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_ADC_SEL_A_CDC_TX1DOL 0x0 3788 3789#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_S 4 3790#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_M 0x30 3791#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_R 0x3 3792#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC2_DIN_L 0x2 3793#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_R 0x1 3794#define TIMPANI_CDC_ANC_INPUT_MUX_ANC2_DMIC_SEL_MIC1_DIN_L 0x0 3795 3796#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_S 2 3797#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_M 0xC 3798#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOR 0x3 3799#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX2DOL 0x2 3800#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOR 0x1 3801#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_ADC_SEL_A_CDC_TX1DOL 0x0 3802 3803#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_S 0 3804#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_M 0x3 3805#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_R 0x3 3806#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC2_DIN_L 0x2 3807#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_R 0x1 3808#define TIMPANI_CDC_ANC_INPUT_MUX_ANC1_DMIC_SEL_MIC1_DIN_L 0x0 3809 3810 3811/* -- For CDC_ANC_RX_CLK_NS_SEL */ 3812#define TIMPANI_A_CDC_ANC_RX_CLK_NS_SEL (0x9B) 3813#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_RWC "RW" 3814#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_POR 0 3815#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_S 0 3816#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_M 0x1 3817 3818 3819#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_S 0 3820#define TIMPANI_CDC_ANC_RX_CLK_NS_SEL_ANC_RX_CLK_NS_SEL_M 0x1 3821 3822 3823/* -- For CDC_ANC_FB_TUNE_SEL */ 3824#define TIMPANI_A_CDC_ANC_FB_TUNE_SEL (0x9C) 3825#define TIMPANI_CDC_ANC_FB_TUNE_SEL_RWC "RW" 3826#define TIMPANI_CDC_ANC_FB_TUNE_SEL_POR 0 3827#define TIMPANI_CDC_ANC_FB_TUNE_SEL_S 0 3828#define TIMPANI_CDC_ANC_FB_TUNE_SEL_M 0x3 3829 3830 3831#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_S 1 3832#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_M 0x2 3833#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_EN 0x1 3834#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC2_FB_ADC_SEL_FB_TUNE_DIS 0x0 3835 3836#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_S 0 3837#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_M 0x1 3838#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_EN 0x1 3839#define TIMPANI_CDC_ANC_FB_TUNE_SEL_ANC1_FB_ADC_SEL_FB_TUNE_DIS 0x0 3840 3841 3842/* -- For CLK_DIV_SYNC_CTL */ 3843#define TIMPANI_A_CLK_DIV_SYNC_CTL (0x9E) 3844#define TIMPANI_CLK_DIV_SYNC_CTL_RWC "RW" 3845#define TIMPANI_CLK_DIV_SYNC_CTL_POR 0 3846#define TIMPANI_CLK_DIV_SYNC_CTL_S 0 3847#define TIMPANI_CLK_DIV_SYNC_CTL_M 0x3 3848 3849 3850#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_S 1 3851#define TIMPANI_CLK_DIV_SYNC_CTL_GLBL_DIV_SYNC_M 0x2 3852 3853#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_S 0 3854#define TIMPANI_CLK_DIV_SYNC_CTL_TX_DIV_SYNC_M 0x1 3855 3856 3857/* -- For CDC_ADC_CLK_EN */ 3858#define TIMPANI_A_CDC_ADC_CLK_EN (0x9F) 3859#define TIMPANI_CDC_ADC_CLK_EN_RWC "RW" 3860#define TIMPANI_CDC_ADC_CLK_EN_POR 0 3861#define TIMPANI_CDC_ADC_CLK_EN_S 0 3862#define TIMPANI_CDC_ADC_CLK_EN_M 0xF 3863 3864 3865#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_S 3 3866#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_R_EN_M 0x8 3867 3868#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_S 2 3869#define TIMPANI_CDC_ADC_CLK_EN_A_TX2_L_EN_M 0x4 3870 3871#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_S 1 3872#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_R_EN_M 0x2 3873 3874#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_S 0 3875#define TIMPANI_CDC_ADC_CLK_EN_A_TX1_L_EN_M 0x1 3876 3877 3878/* -- For CDC_ST_MIXING */ 3879#define TIMPANI_A_CDC_ST_MIXING (0xA0) 3880#define TIMPANI_CDC_ST_MIXING_RWC "RW" 3881#define TIMPANI_CDC_ST_MIXING_POR 0 3882#define TIMPANI_CDC_ST_MIXING_S 0 3883#define TIMPANI_CDC_ST_MIXING_M 0xF 3884 3885 3886#define TIMPANI_CDC_ST_MIXING_TX2_R_S 3 3887#define TIMPANI_CDC_ST_MIXING_TX2_R_M 0x8 3888 3889#define TIMPANI_CDC_ST_MIXING_TX2_L_S 2 3890#define TIMPANI_CDC_ST_MIXING_TX2_L_M 0x4 3891 3892#define TIMPANI_CDC_ST_MIXING_TX1_R_S 1 3893#define TIMPANI_CDC_ST_MIXING_TX1_R_M 0x2 3894 3895#define TIMPANI_CDC_ST_MIXING_TX1_L_S 0 3896#define TIMPANI_CDC_ST_MIXING_TX1_L_M 0x1 3897 3898 3899/* -- For CDC_RX2_CTL */ 3900#define TIMPANI_A_CDC_RX2_CTL (0xA1) 3901#define TIMPANI_CDC_RX2_CTL_RWC "RW" 3902#define TIMPANI_CDC_RX2_CTL_POR 0xc 3903#define TIMPANI_CDC_RX2_CTL_S 0 3904#define TIMPANI_CDC_RX2_CTL_M 0x3F 3905 3906 3907#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_S 5 3908#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_R_M 0x20 3909 3910#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_S 4 3911#define TIMPANI_CDC_RX2_CTL_SIDETONE_EN2_L_M 0x10 3912 3913#define TIMPANI_CDC_RX2_CTL_RX2_RATE_S 2 3914#define TIMPANI_CDC_RX2_CTL_RX2_RATE_M 0xC 3915#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_256 0x3 3916#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_128 0x1 3917#define TIMPANI_CDC_RX2_CTL_RX2_RATE_OSR_64 0x0 3918 3919#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_S 1 3920#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_M 0x2 3921#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_32 0x1 3922#define TIMPANI_CDC_RX2_CTL_RX2_I2S_RATE_BR_64 0x0 3923 3924#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_S 0 3925#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_M 0x1 3926#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_MASTER 0x1 3927#define TIMPANI_CDC_RX2_CTL_RX2_I2S_MODE_SLAVE 0x0 3928 3929 3930/* -- For CDC_ARB_CLK_EN */ 3931#define TIMPANI_A_CDC_ARB_CLK_EN (0xA2) 3932#define TIMPANI_CDC_ARB_CLK_EN_RWC "RW" 3933#define TIMPANI_CDC_ARB_CLK_EN_POR 0 3934#define TIMPANI_CDC_ARB_CLK_EN_S 0 3935#define TIMPANI_CDC_ARB_CLK_EN_M 0x1 3936 3937 3938#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_S 0 3939#define TIMPANI_CDC_ARB_CLK_EN_ARB_CLK_EN_M 0x1 3940 3941 3942/* -- For CDC_I2S_CTL2 */ 3943#define TIMPANI_A_CDC_I2S_CTL2 (0xA3) 3944#define TIMPANI_CDC_I2S_CTL2_RWC "RW" 3945#define TIMPANI_CDC_I2S_CTL2_POR 0 3946#define TIMPANI_CDC_I2S_CTL2_S 0 3947#define TIMPANI_CDC_I2S_CTL2_M 0x3F 3948 3949 3950#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_S 3 3951#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_M 0x38 3952#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_DMIC 0x4 3953#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_R 0x3 3954#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX2_L 0x2 3955#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_R 0x1 3956#define TIMPANI_CDC_I2S_CTL2_TX_I2S_CLK_SEL_CLK_TX1_L 0x0 3957 3958#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_S 2 3959#define TIMPANI_CDC_I2S_CTL2_RX2_I2SCLK_EN_M 0x4 3960 3961#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_S 1 3962#define TIMPANI_CDC_I2S_CTL2_RX1_I2SCLK_EN_M 0x2 3963 3964#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_S 0 3965#define TIMPANI_CDC_I2S_CTL2_TX_I2SCLK_EN_M 0x1 3966 3967 3968/* -- For CDC_RX2LG */ 3969#define TIMPANI_A_CDC_RX2LG (0xA4) 3970#define TIMPANI_CDC_RX2LG_RWC "RW" 3971#define TIMPANI_CDC_RX2LG_POR 0xac 3972#define TIMPANI_CDC_RX2LG_S 0 3973#define TIMPANI_CDC_RX2LG_M 0xFF 3974 3975 3976#define TIMPANI_CDC_RX2LG_GAIN_S 0 3977#define TIMPANI_CDC_RX2LG_GAIN_M 0xFF 3978 3979 3980/* -- For CDC_RX2RG */ 3981#define TIMPANI_A_CDC_RX2RG (0xA5) 3982#define TIMPANI_CDC_RX2RG_RWC "RW" 3983#define TIMPANI_CDC_RX2RG_POR 0xac 3984#define TIMPANI_CDC_RX2RG_S 0 3985#define TIMPANI_CDC_RX2RG_M 0xFF 3986 3987 3988#define TIMPANI_CDC_RX2RG_GAIN_S 0 3989#define TIMPANI_CDC_RX2RG_GAIN_M 0xFF 3990 3991 3992/* -- For CDC_TX2LG */ 3993#define TIMPANI_A_CDC_TX2LG (0xA6) 3994#define TIMPANI_CDC_TX2LG_RWC "RW" 3995#define TIMPANI_CDC_TX2LG_POR 0xac 3996#define TIMPANI_CDC_TX2LG_S 0 3997#define TIMPANI_CDC_TX2LG_M 0xFF 3998 3999 4000#define TIMPANI_CDC_TX2LG_GAIN_S 0 4001#define TIMPANI_CDC_TX2LG_GAIN_M 0xFF 4002 4003 4004/* -- For CDC_TX2RG */ 4005#define TIMPANI_A_CDC_TX2RG (0xA7) 4006#define TIMPANI_CDC_TX2RG_RWC "RW" 4007#define TIMPANI_CDC_TX2RG_POR 0xac 4008#define TIMPANI_CDC_TX2RG_S 0 4009#define TIMPANI_CDC_TX2RG_M 0xFF 4010 4011 4012#define TIMPANI_CDC_TX2RG_GAIN_S 0 4013#define TIMPANI_CDC_TX2RG_GAIN_M 0xFF 4014 4015 4016/* -- For CDC_DMIC_MUX */ 4017#define TIMPANI_A_CDC_DMIC_MUX (0xA8) 4018#define TIMPANI_CDC_DMIC_MUX_RWC "RW" 4019#define TIMPANI_CDC_DMIC_MUX_POR 0 4020#define TIMPANI_CDC_DMIC_MUX_S 0 4021#define TIMPANI_CDC_DMIC_MUX_M 0xFF 4022 4023 4024#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_S 6 4025#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_M 0xC0 4026#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3 4027#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2 4028#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1 4029#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0 4030 4031#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_S 4 4032#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_M 0x30 4033#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3 4034#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2 4035#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1 4036#define TIMPANI_CDC_DMIC_MUX_TX2_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0 4037 4038#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_S 2 4039#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_M 0xC 4040#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_R 0x3 4041#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC2_DIN_L 0x2 4042#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_R 0x1 4043#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_R_MIC1_DIN_L 0x0 4044 4045#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_S 0 4046#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_M 0x3 4047#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_R 0x3 4048#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC2_DIN_L 0x2 4049#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_R 0x1 4050#define TIMPANI_CDC_DMIC_MUX_TX1_DMIC_MUX_SEL_L_MIC1_DIN_L 0x0 4051 4052 4053/* -- For CDC_ARB_CLK_CTL */ 4054#define TIMPANI_A_CDC_ARB_CLK_CTL (0xA9) 4055#define TIMPANI_CDC_ARB_CLK_CTL_RWC "RW" 4056#define TIMPANI_CDC_ARB_CLK_CTL_POR 0 4057#define TIMPANI_CDC_ARB_CLK_CTL_S 0 4058#define TIMPANI_CDC_ARB_CLK_CTL_M 0x3 4059 4060 4061#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_S 0 4062#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_M 0x3 4063#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TX_MCLK 0x0 4064#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK1 0x1 4065#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_RX_MCLK2 0x2 4066#define TIMPANI_CDC_ARB_CLK_CTL_ARB_CLK_SEL_TCXO 0x3 4067 4068 4069/* -- For CDC_GCTL2 */ 4070#define TIMPANI_A_CDC_GCTL2 (0xAA) 4071#define TIMPANI_CDC_GCTL2_RWC "RW" 4072#define TIMPANI_CDC_GCTL2_POR 0x33 4073#define TIMPANI_CDC_GCTL2_S 0 4074#define TIMPANI_CDC_GCTL2_M 0xFF 4075 4076 4077#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_S 7 4078#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_R_M 0x80 4079 4080#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_S 6 4081#define TIMPANI_CDC_GCTL2_TX2_PGA_UPDATE_L_M 0x40 4082 4083#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_S 5 4084#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_R_M 0x20 4085 4086#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_S 4 4087#define TIMPANI_CDC_GCTL2_TX2_PGA_MUTE_EN_L_M 0x10 4088 4089#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_S 3 4090#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_R_M 0x8 4091 4092#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_S 2 4093#define TIMPANI_CDC_GCTL2_RX2_PGA_UPDATE_L_M 0x4 4094 4095#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_S 1 4096#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_R_M 0x2 4097 4098#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_S 0 4099#define TIMPANI_CDC_GCTL2_RX2_PGA_MUTE_EN_L_M 0x1 4100 4101 4102/* -- For CDC_BYPASS_CTL2 */ 4103#define TIMPANI_A_CDC_BYPASS_CTL2 (0xAB) 4104#define TIMPANI_CDC_BYPASS_CTL2_RWC "RW" 4105#define TIMPANI_CDC_BYPASS_CTL2_POR 0x2D 4106#define TIMPANI_CDC_BYPASS_CTL2_S 0 4107#define TIMPANI_CDC_BYPASS_CTL2_M 0x3F 4108 4109 4110#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_S 5 4111#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_R_M 0x20 4112 4113#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_S 4 4114#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_R_M 0x10 4115 4116#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_S 3 4117#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_R_M 0x8 4118 4119#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_S 2 4120#define TIMPANI_CDC_BYPASS_CTL2_TX1_DMIC_GAIN_BP_L_M 0x4 4121 4122#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_S 1 4123#define TIMPANI_CDC_BYPASS_CTL2_TX1_ADC_GAIN_BP_L_M 0x2 4124 4125#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_S 0 4126#define TIMPANI_CDC_BYPASS_CTL2_TX1_HPF_BP_L_M 0x1 4127 4128 4129/* -- For CDC_BYPASS_CTL3 */ 4130#define TIMPANI_A_CDC_BYPASS_CTL3 (0xAC) 4131#define TIMPANI_CDC_BYPASS_CTL3_RWC "RW" 4132#define TIMPANI_CDC_BYPASS_CTL3_POR 0x2D 4133#define TIMPANI_CDC_BYPASS_CTL3_S 0 4134#define TIMPANI_CDC_BYPASS_CTL3_M 0x3F 4135 4136 4137#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_S 5 4138#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_R_M 0x20 4139 4140#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_S 4 4141#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_R_M 0x10 4142 4143#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_S 3 4144#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_R_M 0x8 4145 4146#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_S 2 4147#define TIMPANI_CDC_BYPASS_CTL3_TX2_DMIC_GAIN_BP_L_M 0x4 4148 4149#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_S 1 4150#define TIMPANI_CDC_BYPASS_CTL3_TX2_ADC_GAIN_BP_L_M 0x2 4151 4152#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_S 0 4153#define TIMPANI_CDC_BYPASS_CTL3_TX2_HPF_BP_L_M 0x1 4154 4155 4156/* -- For CDC_BYPASS_CTL4 */ 4157#define TIMPANI_A_CDC_BYPASS_CTL4 (0xAD) 4158#define TIMPANI_CDC_BYPASS_CTL4_RWC "RW" 4159#define TIMPANI_CDC_BYPASS_CTL4_POR 0x2 4160#define TIMPANI_CDC_BYPASS_CTL4_S 0 4161#define TIMPANI_CDC_BYPASS_CTL4_M 0xF 4162 4163 4164#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_S 3 4165#define TIMPANI_CDC_BYPASS_CTL4_DITHER_BP_M 0x8 4166 4167#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_S 2 4168#define TIMPANI_CDC_BYPASS_CTL4_DITHER_SHAPE_SEL_M 0x4 4169 4170#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_S 1 4171#define TIMPANI_CDC_BYPASS_CTL4_DITHER_DLY_SEL_M 0x2 4172 4173#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_S 0 4174#define TIMPANI_CDC_BYPASS_CTL4_RX2_HPF_BP_M 0x1 4175 4176 4177/* -- For CDC_RX2L_DCOFFSET */ 4178#define TIMPANI_A_CDC_RX2L_DCOFFSET (0xAE) 4179#define TIMPANI_CDC_RX2L_DCOFFSET_RWC "RW" 4180#define TIMPANI_CDC_RX2L_DCOFFSET_POR 0 4181#define TIMPANI_CDC_RX2L_DCOFFSET_S 0 4182#define TIMPANI_CDC_RX2L_DCOFFSET_M 0xFF 4183 4184 4185#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_S 0 4186#define TIMPANI_CDC_RX2L_DCOFFSET_OFFSET_M 0xFF 4187 4188 4189/* -- For CDC_RX2R_DCOFFSET */ 4190#define TIMPANI_A_CDC_RX2R_DCOFFSET (0xAF) 4191#define TIMPANI_CDC_RX2R_DCOFFSET_RWC "RW" 4192#define TIMPANI_CDC_RX2R_DCOFFSET_POR 0 4193#define TIMPANI_CDC_RX2R_DCOFFSET_S 0 4194#define TIMPANI_CDC_RX2R_DCOFFSET_M 0xFF 4195 4196 4197#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_S 0 4198#define TIMPANI_CDC_RX2R_DCOFFSET_OFFSET_M 0xFF 4199 4200 4201/* -- For CDC_RX_MIX_CTL */ 4202#define TIMPANI_A_CDC_RX_MIX_CTL (0xB0) 4203#define TIMPANI_CDC_RX_MIX_CTL_RWC "RW" 4204#define TIMPANI_CDC_RX_MIX_CTL_POR 0 4205#define TIMPANI_CDC_RX_MIX_CTL_S 0 4206#define TIMPANI_CDC_RX_MIX_CTL_M 0x3 4207 4208 4209#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_S 1 4210#define TIMPANI_CDC_RX_MIX_CTL_RX2TO1_EN_M 0x2 4211 4212#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_S 0 4213#define TIMPANI_CDC_RX_MIX_CTL_RX1TO2_EN_M 0x1 4214 4215 4216/* -- For CDC_SPARE_CTL */ 4217#define TIMPANI_A_CDC_SPARE_CTL (0xB1) 4218#define TIMPANI_CDC_SPARE_CTL_RWC "RW" 4219#define TIMPANI_CDC_SPARE_CTL_POR 0 4220#define TIMPANI_CDC_SPARE_CTL_S 0 4221#define TIMPANI_CDC_SPARE_CTL_M 0xFF 4222 4223 4224#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_S 0 4225#define TIMPANI_CDC_SPARE_CTL_CDC_SPARE_M 0xFF 4226 4227 4228/* -- For CDC_TESTMODE2 */ 4229#define TIMPANI_A_CDC_TESTMODE2 (0xB2) 4230#define TIMPANI_CDC_TESTMODE2_RWC "RW" 4231#define TIMPANI_CDC_TESTMODE2_POR 0 4232#define TIMPANI_CDC_TESTMODE2_S 0 4233#define TIMPANI_CDC_TESTMODE2_M 0x1F 4234 4235 4236#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_S 4 4237#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_R_M 0x10 4238 4239#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_S 3 4240#define TIMPANI_CDC_TESTMODE2_RX2_TEST_EN_L_M 0x8 4241 4242#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_S 2 4243#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_R_M 0x4 4244 4245#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_S 1 4246#define TIMPANI_CDC_TESTMODE2_TX2_TEST_EN_L_M 0x2 4247 4248#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_S 0 4249#define TIMPANI_CDC_TESTMODE2_A_LOOPBACK_EN2_M 0x1 4250 4251 4252/* -- For CDC_PDM_OE */ 4253#define TIMPANI_A_CDC_PDM_OE (0xB3) 4254#define TIMPANI_CDC_PDM_OE_RWC "RW" 4255#define TIMPANI_CDC_PDM_OE_POR 0 4256#define TIMPANI_CDC_PDM_OE_S 0 4257#define TIMPANI_CDC_PDM_OE_M 0x3F 4258 4259 4260#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_S 5 4261#define TIMPANI_CDC_PDM_OE_PDM_23_20_OE_M 0x20 4262 4263#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_S 4 4264#define TIMPANI_CDC_PDM_OE_PDM_19_16_OE_M 0x10 4265 4266#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_S 3 4267#define TIMPANI_CDC_PDM_OE_PDM_15_12_OE_M 0x8 4268 4269#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_S 2 4270#define TIMPANI_CDC_PDM_OE_PDM_11_8_OE_M 0x4 4271 4272#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_S 1 4273#define TIMPANI_CDC_PDM_OE_PDM_7_4_OE_M 0x2 4274 4275#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_S 0 4276#define TIMPANI_CDC_PDM_OE_PDM_3_0_OE_M 0x1 4277 4278 4279/* -- For CDC_TX1R_STG */ 4280#define TIMPANI_A_CDC_TX1R_STG (0xB4) 4281#define TIMPANI_CDC_TX1R_STG_RWC "RW" 4282#define TIMPANI_CDC_TX1R_STG_POR 0xac 4283#define TIMPANI_CDC_TX1R_STG_S 0 4284#define TIMPANI_CDC_TX1R_STG_M 0xFF 4285 4286 4287#define TIMPANI_CDC_TX1R_STG_GAIN_S 0 4288#define TIMPANI_CDC_TX1R_STG_GAIN_M 0xFF 4289 4290 4291/* -- For CDC_TX2L_STG */ 4292#define TIMPANI_A_CDC_TX2L_STG (0xB5) 4293#define TIMPANI_CDC_TX2L_STG_RWC "RW" 4294#define TIMPANI_CDC_TX2L_STG_POR 0xac 4295#define TIMPANI_CDC_TX2L_STG_S 0 4296#define TIMPANI_CDC_TX2L_STG_M 0xFF 4297 4298 4299#define TIMPANI_CDC_TX2L_STG_GAIN_S 0 4300#define TIMPANI_CDC_TX2L_STG_GAIN_M 0xFF 4301 4302 4303/* -- For CDC_TX2R_STG */ 4304#define TIMPANI_A_CDC_TX2R_STG (0xB6) 4305#define TIMPANI_CDC_TX2R_STG_RWC "RW" 4306#define TIMPANI_CDC_TX2R_STG_POR 0xac 4307#define TIMPANI_CDC_TX2R_STG_S 0 4308#define TIMPANI_CDC_TX2R_STG_M 0xFF 4309 4310 4311#define TIMPANI_CDC_TX2R_STG_GAIN_S 0 4312#define TIMPANI_CDC_TX2R_STG_GAIN_M 0xFF 4313 4314 4315/* -- For CDC_ARB_BYPASS_CTL */ 4316#define TIMPANI_A_CDC_ARB_BYPASS_CTL (0xB7) 4317#define TIMPANI_CDC_ARB_BYPASS_CTL_RWC "RW" 4318#define TIMPANI_CDC_ARB_BYPASS_CTL_POR 0 4319#define TIMPANI_CDC_ARB_BYPASS_CTL_S 0 4320#define TIMPANI_CDC_ARB_BYPASS_CTL_M 0x1 4321 4322 4323#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_S 0 4324#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_M 0x1 4325#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_BYPASS 0x1 4326#define TIMPANI_CDC_ARB_BYPASS_CTL_ARB_BYPASS_EN_NO_BYPASS 0x0 4327 4328 4329/* -- For CDC_ANC1_CTL1 */ 4330#define TIMPANI_A_CDC_ANC1_CTL1 (0xC0) 4331#define TIMPANI_CDC_ANC1_CTL1_RWC "RW" 4332#define TIMPANI_CDC_ANC1_CTL1_POR 0 4333#define TIMPANI_CDC_ANC1_CTL1_S 0 4334#define TIMPANI_CDC_ANC1_CTL1_M 0x3F 4335 4336 4337#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_S 5 4338#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_M 0x20 4339#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_DIS 0x1 4340#define TIMPANI_CDC_ANC1_CTL1_ANC1_FF_OUT_DIS_FF_OUT_EN 0x0 4341 4342#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_S 4 4343#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_M 0x10 4344#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_DMIC 0x1 4345#define TIMPANI_CDC_ANC1_CTL1_ANC1_ADC_DMIC_SEL_ADC 0x0 4346 4347#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_S 3 4348#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_M 0x8 4349#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_EN 0x1 4350#define TIMPANI_CDC_ANC1_CTL1_ANC1_LR_EN_LR_MIX_DIS 0x0 4351 4352#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_S 2 4353#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_M 0x4 4354#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_EN 0x1 4355#define TIMPANI_CDC_ANC1_CTL1_ANC1_FB_EN_FB_MIX_DIS 0x0 4356 4357#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_S 1 4358#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_M 0x2 4359#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_EN 0x1 4360#define TIMPANI_CDC_ANC1_CTL1_ANC1_EN_ANC_DIS 0x0 4361 4362#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_S 0 4363#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_M 0x1 4364#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_RESET 0x1 4365#define TIMPANI_CDC_ANC1_CTL1_ANC1_SOFT_RESET_ANC_ACTIVE 0x0 4366 4367 4368/* -- For CDC_ANC1_CTL2 */ 4369#define TIMPANI_A_CDC_ANC1_CTL2 (0xC1) 4370#define TIMPANI_CDC_ANC1_CTL2_RWC "RW" 4371#define TIMPANI_CDC_ANC1_CTL2_POR 0 4372#define TIMPANI_CDC_ANC1_CTL2_S 0 4373#define TIMPANI_CDC_ANC1_CTL2_M 0x1F 4374 4375 4376#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_S 0 4377#define TIMPANI_CDC_ANC1_CTL2_ANC1_FREQ_SEL_M 0x1F 4378 4379 4380/* -- For CDC_ANC1_FF_FB_SHIFT */ 4381#define TIMPANI_A_CDC_ANC1_FF_FB_SHIFT (0xC2) 4382#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_RWC "RW" 4383#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_POR 0 4384#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_S 0 4385#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_M 0xFF 4386 4387 4388#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_S 4 4389#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FB_LPF_SHIFT_M 0xF0 4390 4391#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_S 0 4392#define TIMPANI_CDC_ANC1_FF_FB_SHIFT_ANC1_FF_LPF_SHIFT_M 0xF 4393 4394 4395/* -- For CDC_ANC1_RX_NS */ 4396#define TIMPANI_A_CDC_ANC1_RX_NS (0xC3) 4397#define TIMPANI_CDC_ANC1_RX_NS_RWC "RW" 4398#define TIMPANI_CDC_ANC1_RX_NS_POR 0x1 4399#define TIMPANI_CDC_ANC1_RX_NS_S 0 4400#define TIMPANI_CDC_ANC1_RX_NS_M 0x7 4401 4402 4403#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_S 2 4404#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_BP_M 0x4 4405 4406#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_S 1 4407#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_SHAPE_SEL_M 0x2 4408 4409#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_S 0 4410#define TIMPANI_CDC_ANC1_RX_NS_ANC1_DITHER_DLY_SEL_M 0x1 4411 4412 4413/* -- For CDC_ANC1_SPARE */ 4414#define TIMPANI_A_CDC_ANC1_SPARE (0xC4) 4415#define TIMPANI_CDC_ANC1_SPARE_RWC "RW" 4416#define TIMPANI_CDC_ANC1_SPARE_POR 0 4417#define TIMPANI_CDC_ANC1_SPARE_S 0 4418#define TIMPANI_CDC_ANC1_SPARE_M 0xFF 4419 4420 4421#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_S 0 4422#define TIMPANI_CDC_ANC1_SPARE_ANC1_SPARE_M 0xFF 4423 4424 4425/* -- For CDC_ANC1_IIR_COEFF_PTR */ 4426#define TIMPANI_A_CDC_ANC1_IIR_COEFF_PTR (0xC5) 4427#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_RWC "RW" 4428#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_POR 0 4429#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_S 0 4430#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_M 0x1F 4431 4432 4433#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_S 0 4434#define TIMPANI_CDC_ANC1_IIR_COEFF_PTR_ANC1_IIR_COEFF_PTR_M 0x1F 4435 4436 4437/* -- For CDC_ANC1_IIR_COEFF_MSB */ 4438#define TIMPANI_A_CDC_ANC1_IIR_COEFF_MSB (0xC6) 4439#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_RWC "RW" 4440#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_POR 0 4441#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_S 0 4442#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_M 0x1 4443 4444 4445#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_S 0 4446#define TIMPANI_CDC_ANC1_IIR_COEFF_MSB_ANC1_IIR_COEFF_MSB_M 0x1 4447 4448 4449/* -- For CDC_ANC1_IIR_COEFF_LSB */ 4450#define TIMPANI_A_CDC_ANC1_IIR_COEFF_LSB (0xC7) 4451#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_RWC "RW" 4452#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_POR 0 4453#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_S 0 4454#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_M 0xFF 4455 4456 4457#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_S 0 4458#define TIMPANI_CDC_ANC1_IIR_COEFF_LSB_ANC1_IIR_COEFF_LSB_M 0xFF 4459 4460 4461/* -- For CDC_ANC1_IIR_COEFF_CTL */ 4462#define TIMPANI_A_CDC_ANC1_IIR_COEFF_CTL (0xC8) 4463#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_RWC "RW" 4464#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_POR 0 4465#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_S 0 4466#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_M 0x3 4467 4468 4469#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_S 1 4470#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_M 0x2 4471#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1 4472#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0 4473 4474#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_S 0 4475#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_M 0x1 4476#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_UPDATE 0x1 4477#define TIMPANI_CDC_ANC1_IIR_COEFF_CTL_ANC1_IIR_COEFF_EN_NO_UPDATE 0x0 4478 4479 4480/* -- For CDC_ANC1_LPF_COEFF_PTR */ 4481#define TIMPANI_A_CDC_ANC1_LPF_COEFF_PTR (0xC9) 4482#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_RWC "RW" 4483#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_POR 0 4484#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_S 0 4485#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_M 0xF 4486 4487 4488#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_S 0 4489#define TIMPANI_CDC_ANC1_LPF_COEFF_PTR_ANC1_LPF_COEFF_PTR_M 0xF 4490 4491 4492/* -- For CDC_ANC1_LPF_COEFF_MSB */ 4493#define TIMPANI_A_CDC_ANC1_LPF_COEFF_MSB (0xCA) 4494#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_RWC "RW" 4495#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_POR 0 4496#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_S 0 4497#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_M 0xF 4498 4499 4500#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_S 0 4501#define TIMPANI_CDC_ANC1_LPF_COEFF_MSB_ANC1_LPF_COEFF_MSB_M 0xF 4502 4503 4504/* -- For CDC_ANC1_LPF_COEFF_LSB */ 4505#define TIMPANI_A_CDC_ANC1_LPF_COEFF_LSB (0xCB) 4506#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_RWC "RW" 4507#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_POR 0 4508#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_S 0 4509#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_M 0xFF 4510 4511 4512#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_S 0 4513#define TIMPANI_CDC_ANC1_LPF_COEFF_LSB_ANC1_LPF_COEFF_LSB_M 0xFF 4514 4515 4516/* -- For CDC_ANC1_SCALE_PTR */ 4517#define TIMPANI_A_CDC_ANC1_SCALE_PTR (0xCC) 4518#define TIMPANI_CDC_ANC1_SCALE_PTR_RWC "RW" 4519#define TIMPANI_CDC_ANC1_SCALE_PTR_POR 0 4520#define TIMPANI_CDC_ANC1_SCALE_PTR_S 0 4521#define TIMPANI_CDC_ANC1_SCALE_PTR_M 0x7 4522 4523 4524#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_S 0 4525#define TIMPANI_CDC_ANC1_SCALE_PTR_ANC1_SCALE_PTR_M 0x7 4526 4527 4528/* -- For CDC_ANC1_SCALE */ 4529#define TIMPANI_A_CDC_ANC1_SCALE (0xCD) 4530#define TIMPANI_CDC_ANC1_SCALE_RWC "RW" 4531#define TIMPANI_CDC_ANC1_SCALE_POR 0 4532#define TIMPANI_CDC_ANC1_SCALE_S 0 4533#define TIMPANI_CDC_ANC1_SCALE_M 0xFF 4534 4535 4536#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_S 0 4537#define TIMPANI_CDC_ANC1_SCALE_ANC1_SCALE_M 0xFF 4538 4539 4540/* -- For CDC_ANC1_DEBUG */ 4541#define TIMPANI_A_CDC_ANC1_DEBUG (0xCE) 4542#define TIMPANI_CDC_ANC1_DEBUG_RWC "RW" 4543#define TIMPANI_CDC_ANC1_DEBUG_POR 0 4544#define TIMPANI_CDC_ANC1_DEBUG_S 0 4545#define TIMPANI_CDC_ANC1_DEBUG_M 0xF 4546 4547 4548#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_S 0 4549#define TIMPANI_CDC_ANC1_DEBUG_ANC1_DEBUG_SEL_M 0xF 4550 4551 4552/* -- For CDC_ANC2_CTL1 */ 4553#define TIMPANI_A_CDC_ANC2_CTL1 (0xD0) 4554#define TIMPANI_CDC_ANC2_CTL1_RWC "RW" 4555#define TIMPANI_CDC_ANC2_CTL1_POR 0 4556#define TIMPANI_CDC_ANC2_CTL1_S 0 4557#define TIMPANI_CDC_ANC2_CTL1_M 0x3F 4558 4559 4560#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_S 5 4561#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_M 0x20 4562#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_DIS 0x1 4563#define TIMPANI_CDC_ANC2_CTL1_ANC2_FF_OUT_DIS_FF_OUT_EN 0x0 4564 4565#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_S 4 4566#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_M 0x10 4567#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_DMIC 0x1 4568#define TIMPANI_CDC_ANC2_CTL1_ANC2_ADC_DMIC_SEL_ADC 0x0 4569 4570#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_S 3 4571#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_M 0x8 4572#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_EN 0x1 4573#define TIMPANI_CDC_ANC2_CTL1_ANC2_LR_EN_LR_MIX_DIS 0x0 4574 4575#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_S 2 4576#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_M 0x4 4577#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_EN 0x1 4578#define TIMPANI_CDC_ANC2_CTL1_ANC2_FB_EN_FB_MIX_DIS 0x0 4579 4580#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_S 1 4581#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_M 0x2 4582#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_EN 0x1 4583#define TIMPANI_CDC_ANC2_CTL1_ANC2_EN_ANC_DIS 0x0 4584 4585#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_S 0 4586#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_M 0x1 4587#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_RESET 0x1 4588#define TIMPANI_CDC_ANC2_CTL1_ANC2_SOFT_RESET_ANC_ACTIVE 0x0 4589 4590 4591/* -- For CDC_ANC2_CTL2 */ 4592#define TIMPANI_A_CDC_ANC2_CTL2 (0xD1) 4593#define TIMPANI_CDC_ANC2_CTL2_RWC "RW" 4594#define TIMPANI_CDC_ANC2_CTL2_POR 0 4595#define TIMPANI_CDC_ANC2_CTL2_S 0 4596#define TIMPANI_CDC_ANC2_CTL2_M 0x1F 4597 4598 4599#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_S 0 4600#define TIMPANI_CDC_ANC2_CTL2_ANC2_FREQ_SEL_M 0x1F 4601 4602 4603/* -- For CDC_ANC2_FF_FB_SHIFT */ 4604#define TIMPANI_A_CDC_ANC2_FF_FB_SHIFT (0xD2) 4605#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_RWC "RW" 4606#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_POR 0 4607#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_S 0 4608#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_M 0xFF 4609 4610 4611#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_S 4 4612#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FB_LPF_SHIFT_M 0xF0 4613 4614#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_S 0 4615#define TIMPANI_CDC_ANC2_FF_FB_SHIFT_ANC2_FF_LPF_SHIFT_M 0xF 4616 4617 4618/* -- For CDC_ANC2_RX_NS */ 4619#define TIMPANI_A_CDC_ANC2_RX_NS (0xD3) 4620#define TIMPANI_CDC_ANC2_RX_NS_RWC "RW" 4621#define TIMPANI_CDC_ANC2_RX_NS_POR 0x1 4622#define TIMPANI_CDC_ANC2_RX_NS_S 0 4623#define TIMPANI_CDC_ANC2_RX_NS_M 0x7 4624 4625 4626#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_S 2 4627#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_BP_M 0x4 4628 4629#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_S 1 4630#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_SHAPE_SEL_M 0x2 4631 4632#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_S 0 4633#define TIMPANI_CDC_ANC2_RX_NS_ANC2_DITHER_DLY_SEL_M 0x1 4634 4635 4636/* -- For CDC_ANC2_SPARE */ 4637#define TIMPANI_A_CDC_ANC2_SPARE (0xD4) 4638#define TIMPANI_CDC_ANC2_SPARE_RWC "RW" 4639#define TIMPANI_CDC_ANC2_SPARE_POR 0 4640#define TIMPANI_CDC_ANC2_SPARE_S 0 4641#define TIMPANI_CDC_ANC2_SPARE_M 0xFF 4642 4643 4644#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_S 0 4645#define TIMPANI_CDC_ANC2_SPARE_ANC2_SPARE_M 0xFF 4646 4647 4648/* -- For CDC_ANC2_IIR_COEFF_PTR */ 4649#define TIMPANI_A_CDC_ANC2_IIR_COEFF_PTR (0xD5) 4650#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_RWC "RW" 4651#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_POR 0 4652#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_S 0 4653#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_M 0x1F 4654 4655 4656#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_S 0 4657#define TIMPANI_CDC_ANC2_IIR_COEFF_PTR_ANC2_IIR_COEFF_PTR_M 0x1F 4658 4659 4660/* -- For CDC_ANC2_IIR_COEFF_MSB */ 4661#define TIMPANI_A_CDC_ANC2_IIR_COEFF_MSB (0xD6) 4662#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_RWC "RW" 4663#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_POR 0 4664#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_S 0 4665#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_M 0x1 4666 4667 4668#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_S 0 4669#define TIMPANI_CDC_ANC2_IIR_COEFF_MSB_ANC2_IIR_COEFF_MSB_M 0x1 4670 4671 4672/* -- For CDC_ANC2_IIR_COEFF_LSB */ 4673#define TIMPANI_A_CDC_ANC2_IIR_COEFF_LSB (0xD7) 4674#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_RWC "RW" 4675#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_POR 0 4676#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_S 0 4677#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_M 0xFF 4678 4679 4680#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_S 0 4681#define TIMPANI_CDC_ANC2_IIR_COEFF_LSB_ANC2_IIR_COEFF_LSB_M 0xFF 4682 4683 4684/* -- For CDC_ANC2_IIR_COEFF_CTL */ 4685#define TIMPANI_A_CDC_ANC2_IIR_COEFF_CTL (0xD8) 4686#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_RWC "RW" 4687#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_POR 0 4688#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_S 0 4689#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_M 0x3 4690 4691 4692#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_S 1 4693#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_M 0x2 4694#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_ADAPTIVE 0x1 4695#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_ADAPTIVE_NON_ADAPTIVE 0x0 4696 4697#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_S 0 4698#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_M 0x1 4699#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_UPDATE 0x1 4700#define TIMPANI_CDC_ANC2_IIR_COEFF_CTL_ANC2_IIR_COEFF_EN_NO_UPDATE 0x0 4701 4702 4703/* -- For CDC_ANC2_LPF_COEFF_PTR */ 4704#define TIMPANI_A_CDC_ANC2_LPF_COEFF_PTR (0xD9) 4705#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_RWC "RW" 4706#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_POR 0 4707#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_S 0 4708#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_M 0xF 4709 4710 4711#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_S 0 4712#define TIMPANI_CDC_ANC2_LPF_COEFF_PTR_ANC2_LPF_COEFF_PTR_M 0xF 4713 4714 4715/* -- For CDC_ANC2_LPF_COEFF_MSB */ 4716#define TIMPANI_A_CDC_ANC2_LPF_COEFF_MSB (0xDA) 4717#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_RWC "RW" 4718#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_POR 0 4719#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_S 0 4720#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_M 0xF 4721 4722 4723#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_S 0 4724#define TIMPANI_CDC_ANC2_LPF_COEFF_MSB_ANC2_LPF_COEFF_MSB_M 0xF 4725 4726 4727/* -- For CDC_ANC2_LPF_COEFF_LSB */ 4728#define TIMPANI_A_CDC_ANC2_LPF_COEFF_LSB (0xDB) 4729#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_RWC "RW" 4730#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_POR 0 4731#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_S 0 4732#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_M 0xFF 4733 4734 4735#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_S 0 4736#define TIMPANI_CDC_ANC2_LPF_COEFF_LSB_ANC2_LPF_COEFF_LSB_M 0xFF 4737 4738 4739/* -- For CDC_ANC2_SCALE_PTR */ 4740#define TIMPANI_A_CDC_ANC2_SCALE_PTR (0xDC) 4741#define TIMPANI_CDC_ANC2_SCALE_PTR_RWC "RW" 4742#define TIMPANI_CDC_ANC2_SCALE_PTR_POR 0 4743#define TIMPANI_CDC_ANC2_SCALE_PTR_S 0 4744#define TIMPANI_CDC_ANC2_SCALE_PTR_M 0x7 4745 4746 4747#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_S 0 4748#define TIMPANI_CDC_ANC2_SCALE_PTR_ANC2_SCALE_PTR_M 0x7 4749 4750 4751/* -- For CDC_ANC2_SCALE */ 4752#define TIMPANI_A_CDC_ANC2_SCALE (0xDD) 4753#define TIMPANI_CDC_ANC2_SCALE_RWC "RW" 4754#define TIMPANI_CDC_ANC2_SCALE_POR 0 4755#define TIMPANI_CDC_ANC2_SCALE_S 0 4756#define TIMPANI_CDC_ANC2_SCALE_M 0xFF 4757 4758 4759#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_S 0 4760#define TIMPANI_CDC_ANC2_SCALE_ANC2_SCALE_M 0xFF 4761 4762 4763/* -- For CDC_ANC2_DEBUG */ 4764#define TIMPANI_A_CDC_ANC2_DEBUG (0xDE) 4765#define TIMPANI_CDC_ANC2_DEBUG_RWC "RW" 4766#define TIMPANI_CDC_ANC2_DEBUG_POR 0 4767#define TIMPANI_CDC_ANC2_DEBUG_S 0 4768#define TIMPANI_CDC_ANC2_DEBUG_M 0xF 4769 4770 4771#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_S 0 4772#define TIMPANI_CDC_ANC2_DEBUG_ANC2_DEBUG_SEL_M 0xF 4773 4774 4775/* -- For CDC_LINE_L_AVOL */ 4776#define TIMPANI_A_CDC_LINE_L_AVOL (0xE0) 4777#define TIMPANI_CDC_LINE_L_AVOL_RWC "RW" 4778#define TIMPANI_CDC_LINE_L_AVOL_POR 0xac 4779#define TIMPANI_CDC_LINE_L_AVOL_S 0 4780#define TIMPANI_CDC_LINE_L_AVOL_M 0xFF 4781 4782 4783#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_S 2 4784#define TIMPANI_CDC_LINE_L_AVOL_USER_GAIN_M 0xFC 4785 4786#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_S 0 4787#define TIMPANI_CDC_LINE_L_AVOL_DUMMY_M 0x3 4788 4789 4790/* -- For CDC_LINE_R_AVOL */ 4791#define TIMPANI_A_CDC_LINE_R_AVOL (0xE1) 4792#define TIMPANI_CDC_LINE_R_AVOL_RWC "RW" 4793#define TIMPANI_CDC_LINE_R_AVOL_POR 0xac 4794#define TIMPANI_CDC_LINE_R_AVOL_S 0 4795#define TIMPANI_CDC_LINE_R_AVOL_M 0xFF 4796 4797 4798#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_S 2 4799#define TIMPANI_CDC_LINE_R_AVOL_USER_GAIN_M 0xFC 4800 4801#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_S 0 4802#define TIMPANI_CDC_LINE_R_AVOL_DUMMY_M 0x3 4803 4804 4805/* -- For CDC_HPH_L_AVOL */ 4806#define TIMPANI_A_CDC_HPH_L_AVOL (0xE2) 4807#define TIMPANI_CDC_HPH_L_AVOL_RWC "RW" 4808#define TIMPANI_CDC_HPH_L_AVOL_POR 0xae 4809#define TIMPANI_CDC_HPH_L_AVOL_S 0 4810#define TIMPANI_CDC_HPH_L_AVOL_M 0xFF 4811 4812 4813#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_S 2 4814#define TIMPANI_CDC_HPH_L_AVOL_USER_GAIN_M 0xFC 4815 4816#define TIMPANI_CDC_HPH_L_AVOL_MUTE_S 1 4817#define TIMPANI_CDC_HPH_L_AVOL_MUTE_M 0x2 4818#define TIMPANI_CDC_HPH_L_AVOL_MUTE_MUTE 0x1 4819#define TIMPANI_CDC_HPH_L_AVOL_MUTE_UNMUTE 0x0 4820 4821#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_S 0 4822#define TIMPANI_CDC_HPH_L_AVOL_DUMMY_M 0x1 4823 4824 4825/* -- For CDC_HPH_R_AVOL */ 4826#define TIMPANI_A_CDC_HPH_R_AVOL (0xE3) 4827#define TIMPANI_CDC_HPH_R_AVOL_RWC "RW" 4828#define TIMPANI_CDC_HPH_R_AVOL_POR 0xae 4829#define TIMPANI_CDC_HPH_R_AVOL_S 0 4830#define TIMPANI_CDC_HPH_R_AVOL_M 0xFF 4831 4832 4833#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_S 2 4834#define TIMPANI_CDC_HPH_R_AVOL_USER_GAIN_M 0xFC 4835 4836#define TIMPANI_CDC_HPH_R_AVOL_MUTE_S 1 4837#define TIMPANI_CDC_HPH_R_AVOL_MUTE_M 0x2 4838#define TIMPANI_CDC_HPH_R_AVOL_MUTE_MUTE 0x1 4839#define TIMPANI_CDC_HPH_R_AVOL_MUTE_UNMUTE 0x0 4840 4841#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_S 0 4842#define TIMPANI_CDC_HPH_R_AVOL_DUMMY_M 0x1 4843 4844 4845/* -- For CDC_COMP_CTL1 */ 4846#define TIMPANI_A_CDC_COMP_CTL1 (0xE4) 4847#define TIMPANI_CDC_COMP_CTL1_RWC "RW" 4848#define TIMPANI_CDC_COMP_CTL1_POR 0 4849#define TIMPANI_CDC_COMP_CTL1_S 0 4850#define TIMPANI_CDC_COMP_CTL1_M 0xFF 4851 4852 4853#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_S 7 4854#define TIMPANI_CDC_COMP_CTL1_LO_CLK_EN_M 0x80 4855 4856#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_S 6 4857#define TIMPANI_CDC_COMP_CTL1_HPH_CLK_EN_M 0x40 4858 4859#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_S 5 4860#define TIMPANI_CDC_COMP_CTL1_LO_SOFT_RESET_M 0x20 4861 4862#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_S 4 4863#define TIMPANI_CDC_COMP_CTL1_HPH_SOFT_RESET_M 0x10 4864 4865#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_S 3 4866#define TIMPANI_CDC_COMP_CTL1_LO_R_EN_M 0x8 4867 4868#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_S 2 4869#define TIMPANI_CDC_COMP_CTL1_LO_L_EN_M 0x4 4870 4871#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_S 1 4872#define TIMPANI_CDC_COMP_CTL1_HPH_R_EN_M 0x2 4873 4874#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_S 0 4875#define TIMPANI_CDC_COMP_CTL1_HPH_L_EN_M 0x1 4876 4877 4878/* -- For CDC_COMP_CTL2 */ 4879#define TIMPANI_A_CDC_COMP_CTL2 (0xE5) 4880#define TIMPANI_CDC_COMP_CTL2_RWC "RW" 4881#define TIMPANI_CDC_COMP_CTL2_POR 0xe 4882#define TIMPANI_CDC_COMP_CTL2_S 0 4883#define TIMPANI_CDC_COMP_CTL2_M 0xF 4884 4885 4886#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_S 2 4887#define TIMPANI_CDC_COMP_CTL2_LINEOUT_IN_MUX_M 0xC 4888 4889#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_S 0 4890#define TIMPANI_CDC_COMP_CTL2_HPH_IN_MUX_M 0x3 4891 4892 4893/* -- For CDC_COMP_PEAK_METER */ 4894#define TIMPANI_A_CDC_COMP_PEAK_METER (0xE6) 4895#define TIMPANI_CDC_COMP_PEAK_METER_RWC "RW" 4896#define TIMPANI_CDC_COMP_PEAK_METER_POR 0x9 4897#define TIMPANI_CDC_COMP_PEAK_METER_S 0 4898#define TIMPANI_CDC_COMP_PEAK_METER_M 0xF 4899 4900 4901#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_S 0 4902#define TIMPANI_CDC_COMP_PEAK_METER_TIME_OUT_M 0xF 4903 4904 4905/* -- For CDC_COMP_LEVEL_METER_CTL1 */ 4906#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL1 (0xE7) 4907#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_RWC "RW" 4908#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_POR 0x7 4909#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_S 0 4910#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_M 0xF 4911 4912 4913#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_S 0 4914#define TIMPANI_CDC_COMP_LEVEL_METER_CTL1_DIV_FACTOR_M 0xF 4915 4916 4917/* -- For CDC_COMP_LEVEL_METER_CTL2 */ 4918#define TIMPANI_A_CDC_COMP_LEVEL_METER_CTL2 (0xE8) 4919#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RWC "RW" 4920#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_POR 0x28 4921#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_S 0 4922#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_M 0xFF 4923 4924 4925#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_S 0 4926#define TIMPANI_CDC_COMP_LEVEL_METER_CTL2_RESAMPLE_RATE_M 0xFF 4927 4928 4929/* -- For CDC_COMP_ZONE_SELECT */ 4930#define TIMPANI_A_CDC_COMP_ZONE_SELECT (0xE9) 4931#define TIMPANI_CDC_COMP_ZONE_SELECT_RWC "RW" 4932#define TIMPANI_CDC_COMP_ZONE_SELECT_POR 0x3b 4933#define TIMPANI_CDC_COMP_ZONE_SELECT_S 0 4934#define TIMPANI_CDC_COMP_ZONE_SELECT_M 0x7F 4935 4936 4937#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_S 3 4938#define TIMPANI_CDC_COMP_ZONE_SELECT_ENTRY_M 0x78 4939 4940#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_S 0 4941#define TIMPANI_CDC_COMP_ZONE_SELECT_SHIFT_M 0x7 4942 4943 4944/* -- For CDC_COMP_ZC_MSB */ 4945#define TIMPANI_A_CDC_COMP_ZC_MSB (0xEA) 4946#define TIMPANI_CDC_COMP_ZC_MSB_RWC "RW" 4947#define TIMPANI_CDC_COMP_ZC_MSB_POR 0 4948#define TIMPANI_CDC_COMP_ZC_MSB_S 0 4949#define TIMPANI_CDC_COMP_ZC_MSB_M 0x7 4950 4951 4952#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_S 0 4953#define TIMPANI_CDC_COMP_ZC_MSB_DET_WINDOW_M 0x7 4954 4955 4956/* -- For CDC_COMP_ZC_LSB */ 4957#define TIMPANI_A_CDC_COMP_ZC_LSB (0xEB) 4958#define TIMPANI_CDC_COMP_ZC_LSB_RWC "RW" 4959#define TIMPANI_CDC_COMP_ZC_LSB_POR 0x1f 4960#define TIMPANI_CDC_COMP_ZC_LSB_S 0 4961#define TIMPANI_CDC_COMP_ZC_LSB_M 0xFF 4962 4963 4964#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_S 0 4965#define TIMPANI_CDC_COMP_ZC_LSB_DET_WINDOW_M 0xFF 4966 4967 4968/* -- For CDC_COMP_SHUT_DOWN */ 4969#define TIMPANI_A_CDC_COMP_SHUT_DOWN (0xEC) 4970#define TIMPANI_CDC_COMP_SHUT_DOWN_RWC "RW" 4971#define TIMPANI_CDC_COMP_SHUT_DOWN_POR 0x1b 4972#define TIMPANI_CDC_COMP_SHUT_DOWN_S 0 4973#define TIMPANI_CDC_COMP_SHUT_DOWN_M 0x3F 4974 4975 4976#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_S 3 4977#define TIMPANI_CDC_COMP_SHUT_DOWN_HPH_TIMEOUT_M 0x38 4978 4979#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_S 0 4980#define TIMPANI_CDC_COMP_SHUT_DOWN_LO_TIMEOUT_M 0x7 4981 4982 4983/* -- For CDC_COMP_SHUT_DOWN_STATUS */ 4984#define TIMPANI_A_CDC_COMP_SHUT_DOWN_STATUS (0xED) 4985#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_RWC "RW" 4986#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_POR 0 4987#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_S 0 4988#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_M 0xF 4989 4990 4991#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_S 3 4992#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_R_M 0x8 4993 4994#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_S 2 4995#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_LO_L_M 0x4 4996 4997#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_S 1 4998#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_R_M 0x2 4999 5000#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_S 0 5001#define TIMPANI_CDC_COMP_SHUT_DOWN_STATUS_HPH_L_M 0x1 5002 5003 5004/* -- For CDC_COMP_HALT */ 5005#define TIMPANI_A_CDC_COMP_HALT (0xEE) 5006#define TIMPANI_CDC_COMP_HALT_RWC "RW" 5007#define TIMPANI_CDC_COMP_HALT_POR 0 5008#define TIMPANI_CDC_COMP_HALT_S 0 5009#define TIMPANI_CDC_COMP_HALT_M 0x1 5010 5011 5012#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_S 0 5013#define TIMPANI_CDC_COMP_HALT_COMPANDER_HALT_M 0x1 5014 5015 5016#endif 5017