1; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG-CHECK 2; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=EG-CHECK 3; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK 4 5; EG-CHECK: @u32_mad24 6; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]\.[XYZW]}}, KC0[2].Z, KC0[2].W, KC0[3].X 7; SI-CHECK: @u32_mad24 8; SI-CHECK: V_MAD_U32_U24 9 10define void @u32_mad24(i32 addrspace(1)* %out, i32 %a, i32 %b, i32 %c) { 11entry: 12 %0 = shl i32 %a, 8 13 %a_24 = lshr i32 %0, 8 14 %1 = shl i32 %b, 8 15 %b_24 = lshr i32 %1, 8 16 %2 = mul i32 %a_24, %b_24 17 %3 = add i32 %2, %c 18 store i32 %3, i32 addrspace(1)* %out 19 ret void 20} 21 22; EG-CHECK: @i16_mad24 23; EG-CHECK-DAG: VTX_READ_16 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40 24; EG-CHECK-DAG: VTX_READ_16 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44 25; EG-CHECK-DAG: VTX_READ_16 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48 26; The order of A and B does not matter. 27; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]] 28; The result must be sign-extended 29; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x 30; EG-CHECK: 16 31; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x 32; EG-CHECK: 16 33; SI-CHECK: @i16_mad24 34; SI-CHECK: V_MAD_U32_U24 [[MAD:VGPR[0-9]]], {{[SV]GPR[0-9], [SV]GPR[0-9]}} 35; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:VGPR[0-9]]], 16, [[MAD]] 36; SI-CHECK: V_ASHRREV_I32_e32 VGPR{{[0-9]}}, 16, [[LSHL]] 37 38define void @i16_mad24(i32 addrspace(1)* %out, i16 %a, i16 %b, i16 %c) { 39entry: 40 %0 = mul i16 %a, %b 41 %1 = add i16 %0, %c 42 %2 = sext i16 %1 to i32 43 store i32 %2, i32 addrspace(1)* %out 44 ret void 45} 46 47; EG-CHECK: @i8_mad24 48; EG-CHECK-DAG: VTX_READ_8 [[A:T[0-9]\.X]], T{{[0-9]}}.X, 40 49; EG-CHECK-DAG: VTX_READ_8 [[B:T[0-9]\.X]], T{{[0-9]}}.X, 44 50; EG-CHECK-DAG: VTX_READ_8 [[C:T[0-9]\.X]], T{{[0-9]}}.X, 48 51; The order of A and B does not matter. 52; EG-CHECK: MULADD_UINT24 {{[* ]*}}T{{[0-9]}}.[[MAD_CHAN:[XYZW]]], [[A]], [[B]], [[C]] 53; The result must be sign-extended 54; EG-CHECK: LSHL {{[* ]*}}T{{[0-9]}}.[[LSHL_CHAN:[XYZW]]], PV.[[MAD_CHAN]], literal.x 55; EG-CHECK: 24 56; EG-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, PV.[[LSHL_CHAN]], literal.x 57; EG-CHECK: 24 58; SI-CHECK: @i8_mad24 59; SI-CHECK: V_MAD_U32_U24 [[MUL:VGPR[0-9]]], {{[SV]GPR[0-9], [SV]GPR[0-9]}} 60; SI-CHECK: V_LSHLREV_B32_e32 [[LSHL:VGPR[0-9]]], 24, [[MUL]] 61; SI-CHECK: V_ASHRREV_I32_e32 VGPR{{[0-9]}}, 24, [[LSHL]] 62 63define void @i8_mad24(i32 addrspace(1)* %out, i8 %a, i8 %b, i8 %c) { 64entry: 65 %0 = mul i8 %a, %b 66 %1 = add i8 %0, %c 67 %2 = sext i8 %1 to i32 68 store i32 %2, i32 addrspace(1)* %out 69 ret void 70} 71