1//===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file is part of the X86 Disassembler Emitter.
11// It contains the implementation of a single recognizable instruction.
12// Documentation for the disassembler emitter in general can be found in
13//  X86DisasemblerEmitter.h.
14//
15//===----------------------------------------------------------------------===//
16
17#include "X86RecognizableInstr.h"
18#include "X86DisassemblerShared.h"
19#include "X86ModRMFilters.h"
20#include "llvm/Support/ErrorHandling.h"
21#include <string>
22
23using namespace llvm;
24
25#define MRM_MAPPING     \
26  MAP(C1, 33)           \
27  MAP(C2, 34)           \
28  MAP(C3, 35)           \
29  MAP(C4, 36)           \
30  MAP(C8, 37)           \
31  MAP(C9, 38)           \
32  MAP(CA, 39)           \
33  MAP(CB, 40)           \
34  MAP(E8, 41)           \
35  MAP(F0, 42)           \
36  MAP(F8, 45)           \
37  MAP(F9, 46)           \
38  MAP(D0, 47)           \
39  MAP(D1, 48)           \
40  MAP(D4, 49)           \
41  MAP(D5, 50)           \
42  MAP(D6, 51)           \
43  MAP(D8, 52)           \
44  MAP(D9, 53)           \
45  MAP(DA, 54)           \
46  MAP(DB, 55)           \
47  MAP(DC, 56)           \
48  MAP(DD, 57)           \
49  MAP(DE, 58)           \
50  MAP(DF, 59)
51
52// A clone of X86 since we can't depend on something that is generated.
53namespace X86Local {
54  enum {
55    Pseudo      = 0,
56    RawFrm      = 1,
57    AddRegFrm   = 2,
58    MRMDestReg  = 3,
59    MRMDestMem  = 4,
60    MRMSrcReg   = 5,
61    MRMSrcMem   = 6,
62    MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19,
63    MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23,
64    MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27,
65    MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31,
66    MRMInitReg  = 32,
67    RawFrmImm8  = 43,
68    RawFrmImm16 = 44,
69#define MAP(from, to) MRM_##from = to,
70    MRM_MAPPING
71#undef MAP
72    lastMRM
73  };
74
75  enum {
76    TB  = 1,
77    REP = 2,
78    D8 = 3, D9 = 4, DA = 5, DB = 6,
79    DC = 7, DD = 8, DE = 9, DF = 10,
80    XD = 11,  XS = 12,
81    T8 = 13,  P_TA = 14,
82    A6 = 15,  A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19
83  };
84}
85
86// If rows are added to the opcode extension tables, then corresponding entries
87// must be added here.
88//
89// If the row corresponds to a single byte (i.e., 8f), then add an entry for
90// that byte to ONE_BYTE_EXTENSION_TABLES.
91//
92// If the row corresponds to two bytes where the first is 0f, add an entry for
93// the second byte to TWO_BYTE_EXTENSION_TABLES.
94//
95// If the row corresponds to some other set of bytes, you will need to modify
96// the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes
97// to the X86 TD files, except in two cases: if the first two bytes of such a
98// new combination are 0f 38 or 0f 3a, you just have to add maps called
99// THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a
100// switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line
101// in RecognizableInstr::emitDecodePath().
102
103#define ONE_BYTE_EXTENSION_TABLES \
104  EXTENSION_TABLE(80)             \
105  EXTENSION_TABLE(81)             \
106  EXTENSION_TABLE(82)             \
107  EXTENSION_TABLE(83)             \
108  EXTENSION_TABLE(8f)             \
109  EXTENSION_TABLE(c0)             \
110  EXTENSION_TABLE(c1)             \
111  EXTENSION_TABLE(c6)             \
112  EXTENSION_TABLE(c7)             \
113  EXTENSION_TABLE(d0)             \
114  EXTENSION_TABLE(d1)             \
115  EXTENSION_TABLE(d2)             \
116  EXTENSION_TABLE(d3)             \
117  EXTENSION_TABLE(f6)             \
118  EXTENSION_TABLE(f7)             \
119  EXTENSION_TABLE(fe)             \
120  EXTENSION_TABLE(ff)
121
122#define TWO_BYTE_EXTENSION_TABLES \
123  EXTENSION_TABLE(00)             \
124  EXTENSION_TABLE(01)             \
125  EXTENSION_TABLE(0d)             \
126  EXTENSION_TABLE(18)             \
127  EXTENSION_TABLE(71)             \
128  EXTENSION_TABLE(72)             \
129  EXTENSION_TABLE(73)             \
130  EXTENSION_TABLE(ae)             \
131  EXTENSION_TABLE(ba)             \
132  EXTENSION_TABLE(c7)
133
134#define THREE_BYTE_38_EXTENSION_TABLES \
135  EXTENSION_TABLE(F3)
136
137using namespace X86Disassembler;
138
139/// needsModRMForDecode - Indicates whether a particular instruction requires a
140///   ModR/M byte for the instruction to be properly decoded.  For example, a
141///   MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to
142///   0b11.
143///
144/// @param form - The form of the instruction.
145/// @return     - true if the form implies that a ModR/M byte is required, false
146///               otherwise.
147static bool needsModRMForDecode(uint8_t form) {
148  if (form == X86Local::MRMDestReg    ||
149     form == X86Local::MRMDestMem    ||
150     form == X86Local::MRMSrcReg     ||
151     form == X86Local::MRMSrcMem     ||
152     (form >= X86Local::MRM0r && form <= X86Local::MRM7r) ||
153     (form >= X86Local::MRM0m && form <= X86Local::MRM7m))
154    return true;
155  else
156    return false;
157}
158
159/// isRegFormat - Indicates whether a particular form requires the Mod field of
160///   the ModR/M byte to be 0b11.
161///
162/// @param form - The form of the instruction.
163/// @return     - true if the form implies that Mod must be 0b11, false
164///               otherwise.
165static bool isRegFormat(uint8_t form) {
166  if (form == X86Local::MRMDestReg ||
167     form == X86Local::MRMSrcReg  ||
168     (form >= X86Local::MRM0r && form <= X86Local::MRM7r))
169    return true;
170  else
171    return false;
172}
173
174/// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit.
175///   Useful for switch statements and the like.
176///
177/// @param init - A reference to the BitsInit to be decoded.
178/// @return     - The field, with the first bit in the BitsInit as the lowest
179///               order bit.
180static uint8_t byteFromBitsInit(BitsInit &init) {
181  int width = init.getNumBits();
182
183  assert(width <= 8 && "Field is too large for uint8_t!");
184
185  int     index;
186  uint8_t mask = 0x01;
187
188  uint8_t ret = 0;
189
190  for (index = 0; index < width; index++) {
191    if (static_cast<BitInit*>(init.getBit(index))->getValue())
192      ret |= mask;
193
194    mask <<= 1;
195  }
196
197  return ret;
198}
199
200/// byteFromRec - Extract a value at most 8 bits in with from a Record given the
201///   name of the field.
202///
203/// @param rec  - The record from which to extract the value.
204/// @param name - The name of the field in the record.
205/// @return     - The field, as translated by byteFromBitsInit().
206static uint8_t byteFromRec(const Record* rec, const std::string &name) {
207  BitsInit* bits = rec->getValueAsBitsInit(name);
208  return byteFromBitsInit(*bits);
209}
210
211RecognizableInstr::RecognizableInstr(DisassemblerTables &tables,
212                                     const CodeGenInstruction &insn,
213                                     InstrUID uid) {
214  UID = uid;
215
216  Rec = insn.TheDef;
217  Name = Rec->getName();
218  Spec = &tables.specForUID(UID);
219
220  if (!Rec->isSubClassOf("X86Inst")) {
221    ShouldBeEmitted = false;
222    return;
223  }
224
225  Prefix   = byteFromRec(Rec, "Prefix");
226  Opcode   = byteFromRec(Rec, "Opcode");
227  Form     = byteFromRec(Rec, "FormBits");
228  SegOvr   = byteFromRec(Rec, "SegOvrBits");
229
230  HasOpSizePrefix  = Rec->getValueAsBit("hasOpSizePrefix");
231  HasAdSizePrefix  = Rec->getValueAsBit("hasAdSizePrefix");
232  HasREX_WPrefix   = Rec->getValueAsBit("hasREX_WPrefix");
233  HasVEXPrefix     = Rec->getValueAsBit("hasVEXPrefix");
234  HasVEX_4VPrefix  = Rec->getValueAsBit("hasVEX_4VPrefix");
235  HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix");
236  HasVEX_WPrefix   = Rec->getValueAsBit("hasVEX_WPrefix");
237  HasMemOp4Prefix  = Rec->getValueAsBit("hasMemOp4Prefix");
238  IgnoresVEX_L     = Rec->getValueAsBit("ignoresVEX_L");
239  HasEVEXPrefix    = Rec->getValueAsBit("hasEVEXPrefix");
240  HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2");
241  HasEVEX_K        = Rec->getValueAsBit("hasEVEX_K");
242  HasEVEX_B        = Rec->getValueAsBit("hasEVEX_B");
243  HasLockPrefix    = Rec->getValueAsBit("hasLockPrefix");
244  IsCodeGenOnly    = Rec->getValueAsBit("isCodeGenOnly");
245
246  Name      = Rec->getName();
247  AsmString = Rec->getValueAsString("AsmString");
248
249  Operands = &insn.Operands.OperandList;
250
251  IsSSE            = (HasOpSizePrefix && (Name.find("16") == Name.npos)) ||
252                     (Name.find("CRC32") != Name.npos);
253  HasFROperands    = hasFROperands();
254  HasVEX_LPrefix   = Rec->getValueAsBit("hasVEX_L");
255
256  // Check for 64-bit inst which does not require REX
257  Is32Bit = false;
258  Is64Bit = false;
259  // FIXME: Is there some better way to check for In64BitMode?
260  std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates");
261  for (unsigned i = 0, e = Predicates.size(); i != e; ++i) {
262    if (Predicates[i]->getName().find("32Bit") != Name.npos) {
263      Is32Bit = true;
264      break;
265    }
266    if (Predicates[i]->getName().find("64Bit") != Name.npos) {
267      Is64Bit = true;
268      break;
269    }
270  }
271  // FIXME: These instructions aren't marked as 64-bit in any way
272  Is64Bit |= Rec->getName() == "JMP64pcrel32" ||
273             Rec->getName() == "MASKMOVDQU64" ||
274             Rec->getName() == "POPFS64" ||
275             Rec->getName() == "POPGS64" ||
276             Rec->getName() == "PUSHFS64" ||
277             Rec->getName() == "PUSHGS64" ||
278             Rec->getName() == "REX64_PREFIX" ||
279             Rec->getName().find("MOV64") != Name.npos ||
280             Rec->getName().find("PUSH64") != Name.npos ||
281             Rec->getName().find("POP64") != Name.npos;
282
283  ShouldBeEmitted  = true;
284}
285
286void RecognizableInstr::processInstr(DisassemblerTables &tables,
287                                     const CodeGenInstruction &insn,
288                                     InstrUID uid)
289{
290  // Ignore "asm parser only" instructions.
291  if (insn.TheDef->getValueAsBit("isAsmParserOnly"))
292    return;
293
294  RecognizableInstr recogInstr(tables, insn, uid);
295
296  recogInstr.emitInstructionSpecifier(tables);
297
298  if (recogInstr.shouldBeEmitted())
299    recogInstr.emitDecodePath(tables);
300}
301
302#define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \
303                    (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n)))
304
305InstructionContext RecognizableInstr::insnContext() const {
306  InstructionContext insnContext;
307
308  if (HasEVEXPrefix) {
309    if (HasVEX_LPrefix && HasEVEX_L2Prefix) {
310      errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n";
311      llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled");
312    }
313    // VEX_L & VEX_W
314    if (HasVEX_LPrefix && HasVEX_WPrefix) {
315      if (HasOpSizePrefix)
316        insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE);
317      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
318        insnContext = EVEX_KB(IC_EVEX_L_W_XS);
319      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
320               Prefix == X86Local::TAXD)
321        insnContext = EVEX_KB(IC_EVEX_L_W_XD);
322      else
323        insnContext = EVEX_KB(IC_EVEX_L_W);
324    } else if (HasVEX_LPrefix) {
325      // VEX_L
326      if (HasOpSizePrefix)
327        insnContext = EVEX_KB(IC_EVEX_L_OPSIZE);
328      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
329        insnContext = EVEX_KB(IC_EVEX_L_XS);
330      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
331               Prefix == X86Local::TAXD)
332        insnContext = EVEX_KB(IC_EVEX_L_XD);
333      else
334        insnContext = EVEX_KB(IC_EVEX_L);
335    }
336    else if (HasEVEX_L2Prefix && HasVEX_WPrefix) {
337      // EVEX_L2 & VEX_W
338      if (HasOpSizePrefix)
339        insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE);
340      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
341        insnContext = EVEX_KB(IC_EVEX_L2_W_XS);
342      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
343               Prefix == X86Local::TAXD)
344        insnContext = EVEX_KB(IC_EVEX_L2_W_XD);
345      else
346        insnContext = EVEX_KB(IC_EVEX_L2_W);
347    } else if (HasEVEX_L2Prefix) {
348      // EVEX_L2
349      if (HasOpSizePrefix)
350        insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE);
351      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
352          Prefix == X86Local::TAXD)
353        insnContext = EVEX_KB(IC_EVEX_L2_XD);
354      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
355        insnContext = EVEX_KB(IC_EVEX_L2_XS);
356      else
357        insnContext = EVEX_KB(IC_EVEX_L2);
358    }
359    else if (HasVEX_WPrefix) {
360      // VEX_W
361      if (HasOpSizePrefix)
362        insnContext = EVEX_KB(IC_EVEX_W_OPSIZE);
363      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
364        insnContext = EVEX_KB(IC_EVEX_W_XS);
365      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
366               Prefix == X86Local::TAXD)
367        insnContext = EVEX_KB(IC_EVEX_W_XD);
368      else
369        insnContext = EVEX_KB(IC_EVEX_W);
370    }
371    // No L, no W
372    else if (HasOpSizePrefix)
373      insnContext = EVEX_KB(IC_EVEX_OPSIZE);
374    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
375             Prefix == X86Local::TAXD)
376      insnContext = EVEX_KB(IC_EVEX_XD);
377    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
378      insnContext = EVEX_KB(IC_EVEX_XS);
379    else
380      insnContext = EVEX_KB(IC_EVEX);
381    /// eof EVEX
382  } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) {
383    if (HasVEX_LPrefix && HasVEX_WPrefix) {
384      if (HasOpSizePrefix)
385        insnContext = IC_VEX_L_W_OPSIZE;
386      else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
387        insnContext = IC_VEX_L_W_XS;
388      else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
389               Prefix == X86Local::TAXD)
390        insnContext = IC_VEX_L_W_XD;
391      else
392        insnContext = IC_VEX_L_W;
393    } else if (HasOpSizePrefix && HasVEX_LPrefix)
394      insnContext = IC_VEX_L_OPSIZE;
395    else if (HasOpSizePrefix && HasVEX_WPrefix)
396      insnContext = IC_VEX_W_OPSIZE;
397    else if (HasOpSizePrefix)
398      insnContext = IC_VEX_OPSIZE;
399    else if (HasVEX_LPrefix &&
400             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
401      insnContext = IC_VEX_L_XS;
402    else if (HasVEX_LPrefix && (Prefix == X86Local::XD ||
403                                Prefix == X86Local::T8XD ||
404                                Prefix == X86Local::TAXD))
405      insnContext = IC_VEX_L_XD;
406    else if (HasVEX_WPrefix &&
407             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
408      insnContext = IC_VEX_W_XS;
409    else if (HasVEX_WPrefix && (Prefix == X86Local::XD ||
410                                Prefix == X86Local::T8XD ||
411                                Prefix == X86Local::TAXD))
412      insnContext = IC_VEX_W_XD;
413    else if (HasVEX_WPrefix)
414      insnContext = IC_VEX_W;
415    else if (HasVEX_LPrefix)
416      insnContext = IC_VEX_L;
417    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
418             Prefix == X86Local::TAXD)
419      insnContext = IC_VEX_XD;
420    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
421      insnContext = IC_VEX_XS;
422    else
423      insnContext = IC_VEX;
424  } else if (Is64Bit || HasREX_WPrefix) {
425    if (HasREX_WPrefix && HasOpSizePrefix)
426      insnContext = IC_64BIT_REXW_OPSIZE;
427    else if (HasOpSizePrefix && (Prefix == X86Local::XD ||
428                                 Prefix == X86Local::T8XD ||
429                                 Prefix == X86Local::TAXD))
430      insnContext = IC_64BIT_XD_OPSIZE;
431    else if (HasOpSizePrefix &&
432             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
433      insnContext = IC_64BIT_XS_OPSIZE;
434    else if (HasOpSizePrefix)
435      insnContext = IC_64BIT_OPSIZE;
436    else if (HasAdSizePrefix)
437      insnContext = IC_64BIT_ADSIZE;
438    else if (HasREX_WPrefix &&
439             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
440      insnContext = IC_64BIT_REXW_XS;
441    else if (HasREX_WPrefix && (Prefix == X86Local::XD ||
442                                Prefix == X86Local::T8XD ||
443                                Prefix == X86Local::TAXD))
444      insnContext = IC_64BIT_REXW_XD;
445    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
446             Prefix == X86Local::TAXD)
447      insnContext = IC_64BIT_XD;
448    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS)
449      insnContext = IC_64BIT_XS;
450    else if (HasREX_WPrefix)
451      insnContext = IC_64BIT_REXW;
452    else
453      insnContext = IC_64BIT;
454  } else {
455    if (HasOpSizePrefix && (Prefix == X86Local::XD ||
456                            Prefix == X86Local::T8XD ||
457                            Prefix == X86Local::TAXD))
458      insnContext = IC_XD_OPSIZE;
459    else if (HasOpSizePrefix &&
460             (Prefix == X86Local::XS || Prefix == X86Local::T8XS))
461      insnContext = IC_XS_OPSIZE;
462    else if (HasOpSizePrefix)
463      insnContext = IC_OPSIZE;
464    else if (HasAdSizePrefix)
465      insnContext = IC_ADSIZE;
466    else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD ||
467             Prefix == X86Local::TAXD)
468      insnContext = IC_XD;
469    else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS ||
470             Prefix == X86Local::REP)
471      insnContext = IC_XS;
472    else
473      insnContext = IC;
474  }
475
476  return insnContext;
477}
478
479RecognizableInstr::filter_ret RecognizableInstr::filter() const {
480  ///////////////////
481  // FILTER_STRONG
482  //
483
484  // Filter out intrinsics
485
486  assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions");
487
488  if (Form == X86Local::Pseudo ||
489      (IsCodeGenOnly && Name.find("_REV") == Name.npos))
490    return FILTER_STRONG;
491
492
493  // Filter out artificial instructions but leave in the LOCK_PREFIX so it is
494  // printed as a separate "instruction".
495
496  if (Name.find("_Int") != Name.npos       ||
497      Name.find("Int_") != Name.npos)
498    return FILTER_STRONG;
499
500  // Filter out instructions with segment override prefixes.
501  // They're too messy to handle now and we'll special case them if needed.
502
503  if (SegOvr)
504    return FILTER_STRONG;
505
506
507  /////////////////
508  // FILTER_WEAK
509  //
510
511
512  // Filter out instructions with a LOCK prefix;
513  //   prefer forms that do not have the prefix
514  if (HasLockPrefix)
515    return FILTER_WEAK;
516
517  // Filter out alternate forms of AVX instructions
518  if (Name.find("_alt") != Name.npos ||
519      Name.find("XrYr") != Name.npos ||
520      (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) ||
521      Name.find("_64mr") != Name.npos ||
522      Name.find("Xrr") != Name.npos ||
523      Name.find("rr64") != Name.npos)
524    return FILTER_WEAK;
525
526  // Special cases.
527
528  if (Name.find("PCMPISTRI") != Name.npos && Name != "PCMPISTRI")
529    return FILTER_WEAK;
530  if (Name.find("PCMPESTRI") != Name.npos && Name != "PCMPESTRI")
531    return FILTER_WEAK;
532
533  if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos)
534    return FILTER_WEAK;
535  if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos)
536    return FILTER_WEAK;
537  if (Name.find("Fs") != Name.npos)
538    return FILTER_WEAK;
539  if (Name == "PUSH64i16"         ||
540      Name == "MOVPQI2QImr"       ||
541      Name == "VMOVPQI2QImr"      ||
542      Name == "MMX_MOVD64rrv164"  ||
543      Name == "MOV64ri64i32"      ||
544      Name == "VMASKMOVDQU64"     ||
545      Name == "VEXTRACTPSrr64"    ||
546      Name == "VMOVQd64rr"        ||
547      Name == "VMOVQs64rr")
548    return FILTER_WEAK;
549
550  // XACQUIRE and XRELEASE reuse REPNE and REP respectively.
551  // For now, just prefer the REP versions.
552  if (Name == "XACQUIRE_PREFIX" ||
553      Name == "XRELEASE_PREFIX")
554    return FILTER_WEAK;
555
556  if (HasFROperands && Name.find("MOV") != Name.npos &&
557     ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) ||
558      (Name.find("to") != Name.npos)))
559    return FILTER_STRONG;
560
561  return FILTER_NORMAL;
562}
563
564bool RecognizableInstr::hasFROperands() const {
565  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
566  unsigned numOperands = OperandList.size();
567
568  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
569    const std::string &recName = OperandList[operandIndex].Rec->getName();
570
571    if (recName.find("FR") != recName.npos)
572      return true;
573  }
574  return false;
575}
576
577void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex,
578                                      unsigned &physicalOperandIndex,
579                                      unsigned &numPhysicalOperands,
580                                      const unsigned *operandMapping,
581                                      OperandEncoding (*encodingFromString)
582                                        (const std::string&,
583                                         bool hasOpSizePrefix)) {
584  if (optional) {
585    if (physicalOperandIndex >= numPhysicalOperands)
586      return;
587  } else {
588    assert(physicalOperandIndex < numPhysicalOperands);
589  }
590
591  while (operandMapping[operandIndex] != operandIndex) {
592    Spec->operands[operandIndex].encoding = ENCODING_DUP;
593    Spec->operands[operandIndex].type =
594      (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]);
595    ++operandIndex;
596  }
597
598  const std::string &typeName = (*Operands)[operandIndex].Rec->getName();
599
600  Spec->operands[operandIndex].encoding = encodingFromString(typeName,
601                                                              HasOpSizePrefix);
602  Spec->operands[operandIndex].type = typeFromString(typeName,
603                                                     IsSSE,
604                                                     HasREX_WPrefix,
605                                                     HasOpSizePrefix);
606
607  ++operandIndex;
608  ++physicalOperandIndex;
609}
610
611void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) {
612  Spec->name       = Name;
613
614  if (!ShouldBeEmitted)
615    return;
616
617  switch (filter()) {
618  case FILTER_WEAK:
619    Spec->filtered = true;
620    break;
621  case FILTER_STRONG:
622    ShouldBeEmitted = false;
623    return;
624  case FILTER_NORMAL:
625    break;
626  }
627
628  Spec->insnContext = insnContext();
629
630  const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands;
631
632  unsigned numOperands = OperandList.size();
633  unsigned numPhysicalOperands = 0;
634
635  // operandMapping maps from operands in OperandList to their originals.
636  // If operandMapping[i] != i, then the entry is a duplicate.
637  unsigned operandMapping[X86_MAX_OPERANDS];
638  assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough");
639
640  for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) {
641    if (OperandList[operandIndex].Constraints.size()) {
642      const CGIOperandList::ConstraintInfo &Constraint =
643        OperandList[operandIndex].Constraints[0];
644      if (Constraint.isTied()) {
645        operandMapping[operandIndex] = operandIndex;
646        operandMapping[Constraint.getTiedOperand()] = operandIndex;
647      } else {
648        ++numPhysicalOperands;
649        operandMapping[operandIndex] = operandIndex;
650      }
651    } else {
652      ++numPhysicalOperands;
653      operandMapping[operandIndex] = operandIndex;
654    }
655  }
656
657#define HANDLE_OPERAND(class)               \
658  handleOperand(false,                      \
659                operandIndex,               \
660                physicalOperandIndex,       \
661                numPhysicalOperands,        \
662                operandMapping,             \
663                class##EncodingFromString);
664
665#define HANDLE_OPTIONAL(class)              \
666  handleOperand(true,                       \
667                operandIndex,               \
668                physicalOperandIndex,       \
669                numPhysicalOperands,        \
670                operandMapping,             \
671                class##EncodingFromString);
672
673  // operandIndex should always be < numOperands
674  unsigned operandIndex = 0;
675  // physicalOperandIndex should always be < numPhysicalOperands
676  unsigned physicalOperandIndex = 0;
677
678  switch (Form) {
679  case X86Local::RawFrm:
680    // Operand 1 (optional) is an address or immediate.
681    // Operand 2 (optional) is an immediate.
682    assert(numPhysicalOperands <= 2 &&
683           "Unexpected number of operands for RawFrm");
684    HANDLE_OPTIONAL(relocation)
685    HANDLE_OPTIONAL(immediate)
686    break;
687  case X86Local::AddRegFrm:
688    // Operand 1 is added to the opcode.
689    // Operand 2 (optional) is an address.
690    assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
691           "Unexpected number of operands for AddRegFrm");
692    HANDLE_OPERAND(opcodeModifier)
693    HANDLE_OPTIONAL(relocation)
694    break;
695  case X86Local::MRMDestReg:
696    // Operand 1 is a register operand in the R/M field.
697    // Operand 2 is a register operand in the Reg/Opcode field.
698    // - In AVX, there is a register operand in the VEX.vvvv field here -
699    // Operand 3 (optional) is an immediate.
700    if (HasVEX_4VPrefix)
701      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
702             "Unexpected number of operands for MRMDestRegFrm with VEX_4V");
703    else
704      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
705             "Unexpected number of operands for MRMDestRegFrm");
706
707    HANDLE_OPERAND(rmRegister)
708
709    if (HasVEX_4VPrefix)
710      // FIXME: In AVX, the register below becomes the one encoded
711      // in ModRMVEX and the one above the one in the VEX.VVVV field
712      HANDLE_OPERAND(vvvvRegister)
713
714    HANDLE_OPERAND(roRegister)
715    HANDLE_OPTIONAL(immediate)
716    break;
717  case X86Local::MRMDestMem:
718    // Operand 1 is a memory operand (possibly SIB-extended)
719    // Operand 2 is a register operand in the Reg/Opcode field.
720    // - In AVX, there is a register operand in the VEX.vvvv field here -
721    // Operand 3 (optional) is an immediate.
722    if (HasVEX_4VPrefix)
723      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 &&
724             "Unexpected number of operands for MRMDestMemFrm with VEX_4V");
725    else
726      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
727             "Unexpected number of operands for MRMDestMemFrm");
728    HANDLE_OPERAND(memory)
729
730    if (HasEVEX_K)
731      HANDLE_OPERAND(writemaskRegister)
732
733    if (HasVEX_4VPrefix)
734      // FIXME: In AVX, the register below becomes the one encoded
735      // in ModRMVEX and the one above the one in the VEX.VVVV field
736      HANDLE_OPERAND(vvvvRegister)
737
738    HANDLE_OPERAND(roRegister)
739    HANDLE_OPTIONAL(immediate)
740    break;
741  case X86Local::MRMSrcReg:
742    // Operand 1 is a register operand in the Reg/Opcode field.
743    // Operand 2 is a register operand in the R/M field.
744    // - In AVX, there is a register operand in the VEX.vvvv field here -
745    // Operand 3 (optional) is an immediate.
746    // Operand 4 (optional) is an immediate.
747
748    if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
749      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
750             "Unexpected number of operands for MRMSrcRegFrm with VEX_4V");
751    else
752      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 &&
753             "Unexpected number of operands for MRMSrcRegFrm");
754
755    HANDLE_OPERAND(roRegister)
756
757    if (HasEVEX_K)
758      HANDLE_OPERAND(writemaskRegister)
759
760    if (HasVEX_4VPrefix)
761      // FIXME: In AVX, the register below becomes the one encoded
762      // in ModRMVEX and the one above the one in the VEX.VVVV field
763      HANDLE_OPERAND(vvvvRegister)
764
765    if (HasMemOp4Prefix)
766      HANDLE_OPERAND(immediate)
767
768    HANDLE_OPERAND(rmRegister)
769
770    if (HasVEX_4VOp3Prefix)
771      HANDLE_OPERAND(vvvvRegister)
772
773    if (!HasMemOp4Prefix)
774      HANDLE_OPTIONAL(immediate)
775    HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
776    HANDLE_OPTIONAL(immediate)
777    break;
778  case X86Local::MRMSrcMem:
779    // Operand 1 is a register operand in the Reg/Opcode field.
780    // Operand 2 is a memory operand (possibly SIB-extended)
781    // - In AVX, there is a register operand in the VEX.vvvv field here -
782    // Operand 3 (optional) is an immediate.
783
784    if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix)
785      assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 &&
786             "Unexpected number of operands for MRMSrcMemFrm with VEX_4V");
787    else
788      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
789             "Unexpected number of operands for MRMSrcMemFrm");
790
791    HANDLE_OPERAND(roRegister)
792
793    if (HasEVEX_K)
794      HANDLE_OPERAND(writemaskRegister)
795
796    if (HasVEX_4VPrefix)
797      // FIXME: In AVX, the register below becomes the one encoded
798      // in ModRMVEX and the one above the one in the VEX.VVVV field
799      HANDLE_OPERAND(vvvvRegister)
800
801    if (HasMemOp4Prefix)
802      HANDLE_OPERAND(immediate)
803
804    HANDLE_OPERAND(memory)
805
806    if (HasVEX_4VOp3Prefix)
807      HANDLE_OPERAND(vvvvRegister)
808
809    if (!HasMemOp4Prefix)
810      HANDLE_OPTIONAL(immediate)
811    HANDLE_OPTIONAL(immediate) // above might be a register in 7:4
812    break;
813  case X86Local::MRM0r:
814  case X86Local::MRM1r:
815  case X86Local::MRM2r:
816  case X86Local::MRM3r:
817  case X86Local::MRM4r:
818  case X86Local::MRM5r:
819  case X86Local::MRM6r:
820  case X86Local::MRM7r:
821    // Operand 1 is a register operand in the R/M field.
822    // Operand 2 (optional) is an immediate or relocation.
823    // Operand 3 (optional) is an immediate.
824    if (HasVEX_4VPrefix)
825      assert(numPhysicalOperands <= 3 &&
826             "Unexpected number of operands for MRMnRFrm with VEX_4V");
827    else
828      assert(numPhysicalOperands <= 3 &&
829             "Unexpected number of operands for MRMnRFrm");
830    if (HasVEX_4VPrefix)
831      HANDLE_OPERAND(vvvvRegister)
832    HANDLE_OPTIONAL(rmRegister)
833    HANDLE_OPTIONAL(relocation)
834    HANDLE_OPTIONAL(immediate)
835    break;
836  case X86Local::MRM0m:
837  case X86Local::MRM1m:
838  case X86Local::MRM2m:
839  case X86Local::MRM3m:
840  case X86Local::MRM4m:
841  case X86Local::MRM5m:
842  case X86Local::MRM6m:
843  case X86Local::MRM7m:
844    // Operand 1 is a memory operand (possibly SIB-extended)
845    // Operand 2 (optional) is an immediate or relocation.
846    if (HasVEX_4VPrefix)
847      assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 &&
848             "Unexpected number of operands for MRMnMFrm");
849    else
850      assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 &&
851             "Unexpected number of operands for MRMnMFrm");
852    if (HasVEX_4VPrefix)
853      HANDLE_OPERAND(vvvvRegister)
854    HANDLE_OPERAND(memory)
855    HANDLE_OPTIONAL(relocation)
856    break;
857  case X86Local::RawFrmImm8:
858    // operand 1 is a 16-bit immediate
859    // operand 2 is an 8-bit immediate
860    assert(numPhysicalOperands == 2 &&
861           "Unexpected number of operands for X86Local::RawFrmImm8");
862    HANDLE_OPERAND(immediate)
863    HANDLE_OPERAND(immediate)
864    break;
865  case X86Local::RawFrmImm16:
866    // operand 1 is a 16-bit immediate
867    // operand 2 is a 16-bit immediate
868    HANDLE_OPERAND(immediate)
869    HANDLE_OPERAND(immediate)
870    break;
871  case X86Local::MRM_F8:
872    if (Opcode == 0xc6) {
873      assert(numPhysicalOperands == 1 &&
874             "Unexpected number of operands for X86Local::MRM_F8");
875      HANDLE_OPERAND(immediate)
876    } else if (Opcode == 0xc7) {
877      assert(numPhysicalOperands == 1 &&
878             "Unexpected number of operands for X86Local::MRM_F8");
879      HANDLE_OPERAND(relocation)
880    }
881    break;
882  case X86Local::MRMInitReg:
883    // Ignored.
884    break;
885  }
886
887  #undef HANDLE_OPERAND
888  #undef HANDLE_OPTIONAL
889}
890
891void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const {
892  // Special cases where the LLVM tables are not complete
893
894#define MAP(from, to)                     \
895  case X86Local::MRM_##from:              \
896    filter = new ExactFilter(0x##from);   \
897    break;
898
899  OpcodeType    opcodeType  = (OpcodeType)-1;
900
901  ModRMFilter*  filter      = NULL;
902  uint8_t       opcodeToSet = 0;
903
904  switch (Prefix) {
905  // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f
906  case X86Local::XD:
907  case X86Local::XS:
908  case X86Local::TB:
909    opcodeType = TWOBYTE;
910
911    switch (Opcode) {
912    default:
913      if (needsModRMForDecode(Form))
914        filter = new ModFilter(isRegFormat(Form));
915      else
916        filter = new DumbFilter();
917      break;
918#define EXTENSION_TABLE(n) case 0x##n:
919    TWO_BYTE_EXTENSION_TABLES
920#undef EXTENSION_TABLE
921      switch (Form) {
922      default:
923        llvm_unreachable("Unhandled two-byte extended opcode");
924      case X86Local::MRM0r:
925      case X86Local::MRM1r:
926      case X86Local::MRM2r:
927      case X86Local::MRM3r:
928      case X86Local::MRM4r:
929      case X86Local::MRM5r:
930      case X86Local::MRM6r:
931      case X86Local::MRM7r:
932        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
933        break;
934      case X86Local::MRM0m:
935      case X86Local::MRM1m:
936      case X86Local::MRM2m:
937      case X86Local::MRM3m:
938      case X86Local::MRM4m:
939      case X86Local::MRM5m:
940      case X86Local::MRM6m:
941      case X86Local::MRM7m:
942        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
943        break;
944      MRM_MAPPING
945      } // switch (Form)
946      break;
947    } // switch (Opcode)
948    opcodeToSet = Opcode;
949    break;
950  case X86Local::T8:
951  case X86Local::T8XD:
952  case X86Local::T8XS:
953    opcodeType = THREEBYTE_38;
954    switch (Opcode) {
955    default:
956      if (needsModRMForDecode(Form))
957        filter = new ModFilter(isRegFormat(Form));
958      else
959        filter = new DumbFilter();
960      break;
961#define EXTENSION_TABLE(n) case 0x##n:
962    THREE_BYTE_38_EXTENSION_TABLES
963#undef EXTENSION_TABLE
964      switch (Form) {
965      default:
966        llvm_unreachable("Unhandled two-byte extended opcode");
967      case X86Local::MRM0r:
968      case X86Local::MRM1r:
969      case X86Local::MRM2r:
970      case X86Local::MRM3r:
971      case X86Local::MRM4r:
972      case X86Local::MRM5r:
973      case X86Local::MRM6r:
974      case X86Local::MRM7r:
975        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
976        break;
977      case X86Local::MRM0m:
978      case X86Local::MRM1m:
979      case X86Local::MRM2m:
980      case X86Local::MRM3m:
981      case X86Local::MRM4m:
982      case X86Local::MRM5m:
983      case X86Local::MRM6m:
984      case X86Local::MRM7m:
985        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
986        break;
987      MRM_MAPPING
988      } // switch (Form)
989      break;
990    } // switch (Opcode)
991    opcodeToSet = Opcode;
992    break;
993  case X86Local::P_TA:
994  case X86Local::TAXD:
995    opcodeType = THREEBYTE_3A;
996    if (needsModRMForDecode(Form))
997      filter = new ModFilter(isRegFormat(Form));
998    else
999      filter = new DumbFilter();
1000    opcodeToSet = Opcode;
1001    break;
1002  case X86Local::A6:
1003    opcodeType = THREEBYTE_A6;
1004    if (needsModRMForDecode(Form))
1005      filter = new ModFilter(isRegFormat(Form));
1006    else
1007      filter = new DumbFilter();
1008    opcodeToSet = Opcode;
1009    break;
1010  case X86Local::A7:
1011    opcodeType = THREEBYTE_A7;
1012    if (needsModRMForDecode(Form))
1013      filter = new ModFilter(isRegFormat(Form));
1014    else
1015      filter = new DumbFilter();
1016    opcodeToSet = Opcode;
1017    break;
1018  case X86Local::D8:
1019  case X86Local::D9:
1020  case X86Local::DA:
1021  case X86Local::DB:
1022  case X86Local::DC:
1023  case X86Local::DD:
1024  case X86Local::DE:
1025  case X86Local::DF:
1026    assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
1027    opcodeType = ONEBYTE;
1028    if (Form == X86Local::AddRegFrm) {
1029      Spec->modifierType = MODIFIER_MODRM;
1030      Spec->modifierBase = Opcode;
1031      filter = new AddRegEscapeFilter(Opcode);
1032    } else {
1033      filter = new EscapeFilter(true, Opcode);
1034    }
1035    opcodeToSet = 0xd8 + (Prefix - X86Local::D8);
1036    break;
1037  case X86Local::REP:
1038  default:
1039    opcodeType = ONEBYTE;
1040    switch (Opcode) {
1041#define EXTENSION_TABLE(n) case 0x##n:
1042    ONE_BYTE_EXTENSION_TABLES
1043#undef EXTENSION_TABLE
1044      switch (Form) {
1045      default:
1046        llvm_unreachable("Fell through the cracks of a single-byte "
1047                         "extended opcode");
1048      case X86Local::MRM0r:
1049      case X86Local::MRM1r:
1050      case X86Local::MRM2r:
1051      case X86Local::MRM3r:
1052      case X86Local::MRM4r:
1053      case X86Local::MRM5r:
1054      case X86Local::MRM6r:
1055      case X86Local::MRM7r:
1056        filter = new ExtendedFilter(true, Form - X86Local::MRM0r);
1057        break;
1058      case X86Local::MRM0m:
1059      case X86Local::MRM1m:
1060      case X86Local::MRM2m:
1061      case X86Local::MRM3m:
1062      case X86Local::MRM4m:
1063      case X86Local::MRM5m:
1064      case X86Local::MRM6m:
1065      case X86Local::MRM7m:
1066        filter = new ExtendedFilter(false, Form - X86Local::MRM0m);
1067        break;
1068      MRM_MAPPING
1069      } // switch (Form)
1070      break;
1071    case 0xd8:
1072    case 0xd9:
1073    case 0xda:
1074    case 0xdb:
1075    case 0xdc:
1076    case 0xdd:
1077    case 0xde:
1078    case 0xdf:
1079      filter = new EscapeFilter(false, Form - X86Local::MRM0m);
1080      break;
1081    default:
1082      if (needsModRMForDecode(Form))
1083        filter = new ModFilter(isRegFormat(Form));
1084      else
1085        filter = new DumbFilter();
1086      break;
1087    } // switch (Opcode)
1088    opcodeToSet = Opcode;
1089  } // switch (Prefix)
1090
1091  assert(opcodeType != (OpcodeType)-1 &&
1092         "Opcode type not set");
1093  assert(filter && "Filter not set");
1094
1095  if (Form == X86Local::AddRegFrm) {
1096    if(Spec->modifierType != MODIFIER_MODRM) {
1097      assert(opcodeToSet < 0xf9 &&
1098             "Not enough room for all ADDREG_FRM operands");
1099
1100      uint8_t currentOpcode;
1101
1102      for (currentOpcode = opcodeToSet;
1103           currentOpcode < opcodeToSet + 8;
1104           ++currentOpcode)
1105        tables.setTableFields(opcodeType,
1106                              insnContext(),
1107                              currentOpcode,
1108                              *filter,
1109                              UID, Is32Bit, IgnoresVEX_L);
1110
1111      Spec->modifierType = MODIFIER_OPCODE;
1112      Spec->modifierBase = opcodeToSet;
1113    } else {
1114      // modifierBase was set where MODIFIER_MODRM was set
1115      tables.setTableFields(opcodeType,
1116                            insnContext(),
1117                            opcodeToSet,
1118                            *filter,
1119                            UID, Is32Bit, IgnoresVEX_L);
1120    }
1121  } else {
1122    tables.setTableFields(opcodeType,
1123                          insnContext(),
1124                          opcodeToSet,
1125                          *filter,
1126                          UID, Is32Bit, IgnoresVEX_L);
1127
1128    Spec->modifierType = MODIFIER_NONE;
1129    Spec->modifierBase = opcodeToSet;
1130  }
1131
1132  delete filter;
1133
1134#undef MAP
1135}
1136
1137#define TYPE(str, type) if (s == str) return type;
1138OperandType RecognizableInstr::typeFromString(const std::string &s,
1139                                              bool isSSE,
1140                                              bool hasREX_WPrefix,
1141                                              bool hasOpSizePrefix) {
1142  if (isSSE) {
1143    // For SSE instructions, we ignore the OpSize prefix and force operand
1144    // sizes.
1145    TYPE("GR16",              TYPE_R16)
1146    TYPE("GR32",              TYPE_R32)
1147    TYPE("GR64",              TYPE_R64)
1148  }
1149  if(hasREX_WPrefix) {
1150    // For instructions with a REX_W prefix, a declared 32-bit register encoding
1151    // is special.
1152    TYPE("GR32",              TYPE_R32)
1153  }
1154  if(!hasOpSizePrefix) {
1155    // For instructions without an OpSize prefix, a declared 16-bit register or
1156    // immediate encoding is special.
1157    TYPE("GR16",              TYPE_R16)
1158    TYPE("i16imm",            TYPE_IMM16)
1159  }
1160  TYPE("i16mem",              TYPE_Mv)
1161  TYPE("i16imm",              TYPE_IMMv)
1162  TYPE("i16i8imm",            TYPE_IMMv)
1163  TYPE("GR16",                TYPE_Rv)
1164  TYPE("i32mem",              TYPE_Mv)
1165  TYPE("i32imm",              TYPE_IMMv)
1166  TYPE("i32i8imm",            TYPE_IMM32)
1167  TYPE("u32u8imm",            TYPE_IMM32)
1168  TYPE("GR32",                TYPE_Rv)
1169  TYPE("i64mem",              TYPE_Mv)
1170  TYPE("i64i32imm",           TYPE_IMM64)
1171  TYPE("i64i8imm",            TYPE_IMM64)
1172  TYPE("GR64",                TYPE_R64)
1173  TYPE("i8mem",               TYPE_M8)
1174  TYPE("i8imm",               TYPE_IMM8)
1175  TYPE("GR8",                 TYPE_R8)
1176  TYPE("VR128",               TYPE_XMM128)
1177  TYPE("VR128X",              TYPE_XMM128)
1178  TYPE("f128mem",             TYPE_M128)
1179  TYPE("f256mem",             TYPE_M256)
1180  TYPE("f512mem",             TYPE_M512)
1181  TYPE("FR64",                TYPE_XMM64)
1182  TYPE("FR64X",               TYPE_XMM64)
1183  TYPE("f64mem",              TYPE_M64FP)
1184  TYPE("sdmem",               TYPE_M64FP)
1185  TYPE("FR32",                TYPE_XMM32)
1186  TYPE("FR32X",               TYPE_XMM32)
1187  TYPE("f32mem",              TYPE_M32FP)
1188  TYPE("ssmem",               TYPE_M32FP)
1189  TYPE("RST",                 TYPE_ST)
1190  TYPE("i128mem",             TYPE_M128)
1191  TYPE("i256mem",             TYPE_M256)
1192  TYPE("i512mem",             TYPE_M512)
1193  TYPE("i64i32imm_pcrel",     TYPE_REL64)
1194  TYPE("i16imm_pcrel",        TYPE_REL16)
1195  TYPE("i32imm_pcrel",        TYPE_REL32)
1196  TYPE("SSECC",               TYPE_IMM3)
1197  TYPE("AVXCC",               TYPE_IMM5)
1198  TYPE("brtarget",            TYPE_RELv)
1199  TYPE("uncondbrtarget",      TYPE_RELv)
1200  TYPE("brtarget8",           TYPE_REL8)
1201  TYPE("f80mem",              TYPE_M80FP)
1202  TYPE("lea32mem",            TYPE_LEA)
1203  TYPE("lea64_32mem",         TYPE_LEA)
1204  TYPE("lea64mem",            TYPE_LEA)
1205  TYPE("VR64",                TYPE_MM64)
1206  TYPE("i64imm",              TYPE_IMMv)
1207  TYPE("opaque32mem",         TYPE_M1616)
1208  TYPE("opaque48mem",         TYPE_M1632)
1209  TYPE("opaque80mem",         TYPE_M1664)
1210  TYPE("opaque512mem",        TYPE_M512)
1211  TYPE("SEGMENT_REG",         TYPE_SEGMENTREG)
1212  TYPE("DEBUG_REG",           TYPE_DEBUGREG)
1213  TYPE("CONTROL_REG",         TYPE_CONTROLREG)
1214  TYPE("offset8",             TYPE_MOFFS8)
1215  TYPE("offset16",            TYPE_MOFFS16)
1216  TYPE("offset32",            TYPE_MOFFS32)
1217  TYPE("offset64",            TYPE_MOFFS64)
1218  TYPE("VR256",               TYPE_XMM256)
1219  TYPE("VR256X",              TYPE_XMM256)
1220  TYPE("VR512",               TYPE_XMM512)
1221  TYPE("VK8",                 TYPE_VK8)
1222  TYPE("VK8WM",               TYPE_VK8)
1223  TYPE("VK16",                TYPE_VK16)
1224  TYPE("VK16WM",              TYPE_VK16)
1225  TYPE("GR16_NOAX",           TYPE_Rv)
1226  TYPE("GR32_NOAX",           TYPE_Rv)
1227  TYPE("GR64_NOAX",           TYPE_R64)
1228  TYPE("vx32mem",             TYPE_M32)
1229  TYPE("vy32mem",             TYPE_M32)
1230  TYPE("vz32mem",             TYPE_M32)
1231  TYPE("vx64mem",             TYPE_M64)
1232  TYPE("vy64mem",             TYPE_M64)
1233  TYPE("vy64xmem",            TYPE_M64)
1234  TYPE("vz64mem",             TYPE_M64)
1235  errs() << "Unhandled type string " << s << "\n";
1236  llvm_unreachable("Unhandled type string");
1237}
1238#undef TYPE
1239
1240#define ENCODING(str, encoding) if (s == str) return encoding;
1241OperandEncoding RecognizableInstr::immediateEncodingFromString
1242  (const std::string &s,
1243   bool hasOpSizePrefix) {
1244  if(!hasOpSizePrefix) {
1245    // For instructions without an OpSize prefix, a declared 16-bit register or
1246    // immediate encoding is special.
1247    ENCODING("i16imm",        ENCODING_IW)
1248  }
1249  ENCODING("i32i8imm",        ENCODING_IB)
1250  ENCODING("u32u8imm",        ENCODING_IB)
1251  ENCODING("SSECC",           ENCODING_IB)
1252  ENCODING("AVXCC",           ENCODING_IB)
1253  ENCODING("i16imm",          ENCODING_Iv)
1254  ENCODING("i16i8imm",        ENCODING_IB)
1255  ENCODING("i32imm",          ENCODING_Iv)
1256  ENCODING("i64i32imm",       ENCODING_ID)
1257  ENCODING("i64i8imm",        ENCODING_IB)
1258  ENCODING("i8imm",           ENCODING_IB)
1259  // This is not a typo.  Instructions like BLENDVPD put
1260  // register IDs in 8-bit immediates nowadays.
1261  ENCODING("FR32",            ENCODING_IB)
1262  ENCODING("FR64",            ENCODING_IB)
1263  ENCODING("VR128",           ENCODING_IB)
1264  ENCODING("VR256",           ENCODING_IB)
1265  ENCODING("FR32X",           ENCODING_IB)
1266  ENCODING("FR64X",           ENCODING_IB)
1267  ENCODING("VR128X",          ENCODING_IB)
1268  ENCODING("VR256X",          ENCODING_IB)
1269  ENCODING("VR512",           ENCODING_IB)
1270  errs() << "Unhandled immediate encoding " << s << "\n";
1271  llvm_unreachable("Unhandled immediate encoding");
1272}
1273
1274OperandEncoding RecognizableInstr::rmRegisterEncodingFromString
1275  (const std::string &s,
1276   bool hasOpSizePrefix) {
1277  ENCODING("GR16",            ENCODING_RM)
1278  ENCODING("GR32",            ENCODING_RM)
1279  ENCODING("GR64",            ENCODING_RM)
1280  ENCODING("GR8",             ENCODING_RM)
1281  ENCODING("VR128",           ENCODING_RM)
1282  ENCODING("VR128X",          ENCODING_RM)
1283  ENCODING("FR64",            ENCODING_RM)
1284  ENCODING("FR32",            ENCODING_RM)
1285  ENCODING("FR64X",           ENCODING_RM)
1286  ENCODING("FR32X",           ENCODING_RM)
1287  ENCODING("VR64",            ENCODING_RM)
1288  ENCODING("VR256",           ENCODING_RM)
1289  ENCODING("VR256X",          ENCODING_RM)
1290  ENCODING("VR512",           ENCODING_RM)
1291  ENCODING("VK8",             ENCODING_RM)
1292  ENCODING("VK16",            ENCODING_RM)
1293  errs() << "Unhandled R/M register encoding " << s << "\n";
1294  llvm_unreachable("Unhandled R/M register encoding");
1295}
1296
1297OperandEncoding RecognizableInstr::roRegisterEncodingFromString
1298  (const std::string &s,
1299   bool hasOpSizePrefix) {
1300  ENCODING("GR16",            ENCODING_REG)
1301  ENCODING("GR32",            ENCODING_REG)
1302  ENCODING("GR64",            ENCODING_REG)
1303  ENCODING("GR8",             ENCODING_REG)
1304  ENCODING("VR128",           ENCODING_REG)
1305  ENCODING("FR64",            ENCODING_REG)
1306  ENCODING("FR32",            ENCODING_REG)
1307  ENCODING("VR64",            ENCODING_REG)
1308  ENCODING("SEGMENT_REG",     ENCODING_REG)
1309  ENCODING("DEBUG_REG",       ENCODING_REG)
1310  ENCODING("CONTROL_REG",     ENCODING_REG)
1311  ENCODING("VR256",           ENCODING_REG)
1312  ENCODING("VR256X",          ENCODING_REG)
1313  ENCODING("VR128X",          ENCODING_REG)
1314  ENCODING("FR64X",           ENCODING_REG)
1315  ENCODING("FR32X",           ENCODING_REG)
1316  ENCODING("VR512",           ENCODING_REG)
1317  ENCODING("VK8",             ENCODING_REG)
1318  ENCODING("VK16",            ENCODING_REG)
1319  ENCODING("VK8WM",           ENCODING_REG)
1320  ENCODING("VK16WM",          ENCODING_REG)
1321  errs() << "Unhandled reg/opcode register encoding " << s << "\n";
1322  llvm_unreachable("Unhandled reg/opcode register encoding");
1323}
1324
1325OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString
1326  (const std::string &s,
1327   bool hasOpSizePrefix) {
1328  ENCODING("GR32",            ENCODING_VVVV)
1329  ENCODING("GR64",            ENCODING_VVVV)
1330  ENCODING("FR32",            ENCODING_VVVV)
1331  ENCODING("FR64",            ENCODING_VVVV)
1332  ENCODING("VR128",           ENCODING_VVVV)
1333  ENCODING("VR256",           ENCODING_VVVV)
1334  ENCODING("FR32X",           ENCODING_VVVV)
1335  ENCODING("FR64X",           ENCODING_VVVV)
1336  ENCODING("VR128X",          ENCODING_VVVV)
1337  ENCODING("VR256X",          ENCODING_VVVV)
1338  ENCODING("VR512",           ENCODING_VVVV)
1339  ENCODING("VK8",             ENCODING_VVVV)
1340  ENCODING("VK16",            ENCODING_VVVV)
1341  errs() << "Unhandled VEX.vvvv register encoding " << s << "\n";
1342  llvm_unreachable("Unhandled VEX.vvvv register encoding");
1343}
1344
1345OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString
1346  (const std::string &s,
1347   bool hasOpSizePrefix) {
1348  ENCODING("VK8WM",           ENCODING_WRITEMASK)
1349  ENCODING("VK16WM",          ENCODING_WRITEMASK)
1350  errs() << "Unhandled mask register encoding " << s << "\n";
1351  llvm_unreachable("Unhandled mask register encoding");
1352}
1353
1354OperandEncoding RecognizableInstr::memoryEncodingFromString
1355  (const std::string &s,
1356   bool hasOpSizePrefix) {
1357  ENCODING("i16mem",          ENCODING_RM)
1358  ENCODING("i32mem",          ENCODING_RM)
1359  ENCODING("i64mem",          ENCODING_RM)
1360  ENCODING("i8mem",           ENCODING_RM)
1361  ENCODING("ssmem",           ENCODING_RM)
1362  ENCODING("sdmem",           ENCODING_RM)
1363  ENCODING("f128mem",         ENCODING_RM)
1364  ENCODING("f256mem",         ENCODING_RM)
1365  ENCODING("f512mem",         ENCODING_RM)
1366  ENCODING("f64mem",          ENCODING_RM)
1367  ENCODING("f32mem",          ENCODING_RM)
1368  ENCODING("i128mem",         ENCODING_RM)
1369  ENCODING("i256mem",         ENCODING_RM)
1370  ENCODING("i512mem",         ENCODING_RM)
1371  ENCODING("f80mem",          ENCODING_RM)
1372  ENCODING("lea32mem",        ENCODING_RM)
1373  ENCODING("lea64_32mem",     ENCODING_RM)
1374  ENCODING("lea64mem",        ENCODING_RM)
1375  ENCODING("opaque32mem",     ENCODING_RM)
1376  ENCODING("opaque48mem",     ENCODING_RM)
1377  ENCODING("opaque80mem",     ENCODING_RM)
1378  ENCODING("opaque512mem",    ENCODING_RM)
1379  ENCODING("vx32mem",         ENCODING_RM)
1380  ENCODING("vy32mem",         ENCODING_RM)
1381  ENCODING("vz32mem",         ENCODING_RM)
1382  ENCODING("vx64mem",         ENCODING_RM)
1383  ENCODING("vy64mem",         ENCODING_RM)
1384  ENCODING("vy64xmem",        ENCODING_RM)
1385  ENCODING("vz64mem",         ENCODING_RM)
1386  errs() << "Unhandled memory encoding " << s << "\n";
1387  llvm_unreachable("Unhandled memory encoding");
1388}
1389
1390OperandEncoding RecognizableInstr::relocationEncodingFromString
1391  (const std::string &s,
1392   bool hasOpSizePrefix) {
1393  if(!hasOpSizePrefix) {
1394    // For instructions without an OpSize prefix, a declared 16-bit register or
1395    // immediate encoding is special.
1396    ENCODING("i16imm",        ENCODING_IW)
1397  }
1398  ENCODING("i16imm",          ENCODING_Iv)
1399  ENCODING("i16i8imm",        ENCODING_IB)
1400  ENCODING("i32imm",          ENCODING_Iv)
1401  ENCODING("i32i8imm",        ENCODING_IB)
1402  ENCODING("i64i32imm",       ENCODING_ID)
1403  ENCODING("i64i8imm",        ENCODING_IB)
1404  ENCODING("i8imm",           ENCODING_IB)
1405  ENCODING("i64i32imm_pcrel", ENCODING_ID)
1406  ENCODING("i16imm_pcrel",    ENCODING_IW)
1407  ENCODING("i32imm_pcrel",    ENCODING_ID)
1408  ENCODING("brtarget",        ENCODING_Iv)
1409  ENCODING("brtarget8",       ENCODING_IB)
1410  ENCODING("i64imm",          ENCODING_IO)
1411  ENCODING("offset8",         ENCODING_Ia)
1412  ENCODING("offset16",        ENCODING_Ia)
1413  ENCODING("offset32",        ENCODING_Ia)
1414  ENCODING("offset64",        ENCODING_Ia)
1415  errs() << "Unhandled relocation encoding " << s << "\n";
1416  llvm_unreachable("Unhandled relocation encoding");
1417}
1418
1419OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString
1420  (const std::string &s,
1421   bool hasOpSizePrefix) {
1422  ENCODING("RST",             ENCODING_I)
1423  ENCODING("GR32",            ENCODING_Rv)
1424  ENCODING("GR64",            ENCODING_RO)
1425  ENCODING("GR16",            ENCODING_Rv)
1426  ENCODING("GR8",             ENCODING_RB)
1427  ENCODING("GR16_NOAX",       ENCODING_Rv)
1428  ENCODING("GR32_NOAX",       ENCODING_Rv)
1429  ENCODING("GR64_NOAX",       ENCODING_RO)
1430  errs() << "Unhandled opcode modifier encoding " << s << "\n";
1431  llvm_unreachable("Unhandled opcode modifier encoding");
1432}
1433#undef ENCODING
1434