1/************************************************************************** 2 * 3 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the 8 * "Software"), to deal in the Software without restriction, including 9 * without limitation the rights to use, copy, modify, merge, publish, 10 * distribute, sub license, and/or sell copies of the Software, and to 11 * permit persons to whom the Software is furnished to do so, subject to 12 * the following conditions: 13 * 14 * The above copyright notice and this permission notice (including the 15 * next paragraph) shall be included in all copies or substantial portions 16 * of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 * 26 **************************************************************************/ 27 28#include "i830_context.h" 29#include "i830_reg.h" 30#include "intel_batchbuffer.h" 31#include "intel_mipmap_tree.h" 32#include "intel_regions.h" 33#include "intel_tris.h" 34#include "intel_fbo.h" 35#include "intel_buffers.h" 36#include "tnl/tnl.h" 37#include "tnl/t_context.h" 38#include "tnl/t_vertex.h" 39#include "swrast_setup/swrast_setup.h" 40#include "main/renderbuffer.h" 41#include "main/framebuffer.h" 42#include "main/fbobject.h" 43 44#define FILE_DEBUG_FLAG DEBUG_STATE 45 46static bool i830_check_vertex_size(struct intel_context *intel, 47 GLuint expected); 48 49#define SZ_TO_HW(sz) ((sz-2)&0x3) 50#define EMIT_SZ(sz) (EMIT_1F + (sz) - 1) 51#define EMIT_ATTR( ATTR, STYLE, V0 ) \ 52do { \ 53 intel->vertex_attrs[intel->vertex_attr_count].attrib = (ATTR); \ 54 intel->vertex_attrs[intel->vertex_attr_count].format = (STYLE); \ 55 intel->vertex_attr_count++; \ 56 v0 |= V0; \ 57} while (0) 58 59#define EMIT_PAD( N ) \ 60do { \ 61 intel->vertex_attrs[intel->vertex_attr_count].attrib = 0; \ 62 intel->vertex_attrs[intel->vertex_attr_count].format = EMIT_PAD; \ 63 intel->vertex_attrs[intel->vertex_attr_count].offset = (N); \ 64 intel->vertex_attr_count++; \ 65} while (0) 66 67 68#define VRTX_TEX_SET_FMT(n, x) ((x)<<((n)*2)) 69#define TEXBIND_SET(n, x) ((x)<<((n)*4)) 70 71static void 72i830_render_prevalidate(struct intel_context *intel) 73{ 74} 75 76static void 77i830_render_start(struct intel_context *intel) 78{ 79 struct gl_context *ctx = &intel->ctx; 80 struct i830_context *i830 = i830_context(ctx); 81 TNLcontext *tnl = TNL_CONTEXT(ctx); 82 struct vertex_buffer *VB = &tnl->vb; 83 GLbitfield64 index_bitset = tnl->render_inputs_bitset; 84 GLuint v0 = _3DSTATE_VFT0_CMD; 85 GLuint v2 = _3DSTATE_VFT1_CMD; 86 GLuint mcsb1 = 0; 87 88 /* Important: 89 */ 90 VB->AttribPtr[VERT_ATTRIB_POS] = VB->NdcPtr; 91 intel->vertex_attr_count = 0; 92 93 /* EMIT_ATTR's must be in order as they tell t_vertex.c how to 94 * build up a hardware vertex. 95 */ 96 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { 97 EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_4F_VIEWPORT, VFT0_XYZW); 98 intel->coloroffset = 4; 99 } 100 else { 101 EMIT_ATTR(_TNL_ATTRIB_POS, EMIT_3F_VIEWPORT, VFT0_XYZ); 102 intel->coloroffset = 3; 103 } 104 105 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_POINTSIZE)) { 106 EMIT_ATTR(_TNL_ATTRIB_POINTSIZE, EMIT_1F, VFT0_POINT_WIDTH); 107 } 108 109 EMIT_ATTR(_TNL_ATTRIB_COLOR0, EMIT_4UB_4F_BGRA, VFT0_DIFFUSE); 110 111 intel->specoffset = 0; 112 if (index_bitset & (BITFIELD64_BIT(_TNL_ATTRIB_COLOR1) | 113 BITFIELD64_BIT(_TNL_ATTRIB_FOG))) { 114 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_COLOR1)) { 115 intel->specoffset = intel->coloroffset + 1; 116 EMIT_ATTR(_TNL_ATTRIB_COLOR1, EMIT_3UB_3F_BGR, VFT0_SPEC); 117 } 118 else 119 EMIT_PAD(3); 120 121 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_FOG)) 122 EMIT_ATTR(_TNL_ATTRIB_FOG, EMIT_1UB_1F, VFT0_SPEC); 123 else 124 EMIT_PAD(1); 125 } 126 127 if (index_bitset & BITFIELD64_RANGE(_TNL_ATTRIB_TEX0, _TNL_NUM_TEX)) { 128 int i, count = 0; 129 130 for (i = 0; i < I830_TEX_UNITS; i++) { 131 if (index_bitset & BITFIELD64_BIT(_TNL_ATTRIB_TEX(i))) { 132 GLuint sz = VB->AttribPtr[_TNL_ATTRIB_TEX0 + i]->size; 133 GLuint emit; 134 GLuint mcs = (i830->state.Tex[i][I830_TEXREG_MCS] & 135 ~TEXCOORDTYPE_MASK); 136 137 switch (sz) { 138 case 1: 139 case 2: 140 emit = EMIT_2F; 141 sz = 2; 142 mcs |= TEXCOORDTYPE_CARTESIAN; 143 break; 144 case 3: 145 emit = EMIT_3F; 146 sz = 3; 147 mcs |= TEXCOORDTYPE_VECTOR; 148 break; 149 case 4: 150 emit = EMIT_3F_XYW; 151 sz = 3; 152 mcs |= TEXCOORDTYPE_HOMOGENEOUS; 153 break; 154 default: 155 continue; 156 }; 157 158 159 EMIT_ATTR(_TNL_ATTRIB_TEX0 + i, emit, 0); 160 v2 |= VRTX_TEX_SET_FMT(count, SZ_TO_HW(sz)); 161 mcsb1 |= (count + 8) << (i * 4); 162 163 if (mcs != i830->state.Tex[i][I830_TEXREG_MCS]) { 164 I830_STATECHANGE(i830, I830_UPLOAD_TEX(i)); 165 i830->state.Tex[i][I830_TEXREG_MCS] = mcs; 166 } 167 168 count++; 169 } 170 } 171 172 v0 |= VFT0_TEX_COUNT(count); 173 } 174 175 /* Only need to change the vertex emit code if there has been a 176 * statechange to a new hardware vertex format: 177 */ 178 if (v0 != i830->state.Ctx[I830_CTXREG_VF] || 179 v2 != i830->state.Ctx[I830_CTXREG_VF2] || 180 mcsb1 != i830->state.Ctx[I830_CTXREG_MCSB1] || 181 index_bitset != i830->last_index_bitset) { 182 int k; 183 184 I830_STATECHANGE(i830, I830_UPLOAD_CTX); 185 186 /* Must do this *after* statechange, so as not to affect 187 * buffered vertices reliant on the old state: 188 */ 189 intel->vertex_size = 190 _tnl_install_attrs(ctx, 191 intel->vertex_attrs, 192 intel->vertex_attr_count, 193 intel->ViewportMatrix.m, 0); 194 195 intel->vertex_size >>= 2; 196 197 i830->state.Ctx[I830_CTXREG_VF] = v0; 198 i830->state.Ctx[I830_CTXREG_VF2] = v2; 199 i830->state.Ctx[I830_CTXREG_MCSB1] = mcsb1; 200 i830->last_index_bitset = index_bitset; 201 202 k = i830_check_vertex_size(intel, intel->vertex_size); 203 assert(k); 204 } 205} 206 207static void 208i830_reduced_primitive_state(struct intel_context *intel, GLenum rprim) 209{ 210 struct i830_context *i830 = i830_context(&intel->ctx); 211 GLuint st1 = i830->state.Stipple[I830_STPREG_ST1]; 212 213 st1 &= ~ST1_ENABLE; 214 215 switch (rprim) { 216 case GL_TRIANGLES: 217 if (intel->ctx.Polygon.StippleFlag && intel->hw_stipple) 218 st1 |= ST1_ENABLE; 219 break; 220 case GL_LINES: 221 case GL_POINTS: 222 default: 223 break; 224 } 225 226 i830->intel.reduced_primitive = rprim; 227 228 if (st1 != i830->state.Stipple[I830_STPREG_ST1]) { 229 INTEL_FIREVERTICES(intel); 230 231 I830_STATECHANGE(i830, I830_UPLOAD_STIPPLE); 232 i830->state.Stipple[I830_STPREG_ST1] = st1; 233 } 234} 235 236/* Pull apart the vertex format registers and figure out how large a 237 * vertex is supposed to be. 238 */ 239static bool 240i830_check_vertex_size(struct intel_context *intel, GLuint expected) 241{ 242 struct i830_context *i830 = i830_context(&intel->ctx); 243 int vft0 = i830->state.Ctx[I830_CTXREG_VF]; 244 int vft1 = i830->state.Ctx[I830_CTXREG_VF2]; 245 int nrtex = (vft0 & VFT0_TEX_COUNT_MASK) >> VFT0_TEX_COUNT_SHIFT; 246 int i, sz = 0; 247 248 switch (vft0 & VFT0_XYZW_MASK) { 249 case VFT0_XY: 250 sz = 2; 251 break; 252 case VFT0_XYZ: 253 sz = 3; 254 break; 255 case VFT0_XYW: 256 sz = 3; 257 break; 258 case VFT0_XYZW: 259 sz = 4; 260 break; 261 default: 262 fprintf(stderr, "no xyzw specified\n"); 263 return 0; 264 } 265 266 if (vft0 & VFT0_SPEC) 267 sz++; 268 if (vft0 & VFT0_DIFFUSE) 269 sz++; 270 if (vft0 & VFT0_DEPTH_OFFSET) 271 sz++; 272 if (vft0 & VFT0_POINT_WIDTH) 273 sz++; 274 275 for (i = 0; i < nrtex; i++) { 276 switch (vft1 & VFT1_TEX0_MASK) { 277 case TEXCOORDFMT_2D: 278 sz += 2; 279 break; 280 case TEXCOORDFMT_3D: 281 sz += 3; 282 break; 283 case TEXCOORDFMT_4D: 284 sz += 4; 285 break; 286 case TEXCOORDFMT_1D: 287 sz += 1; 288 break; 289 } 290 vft1 >>= VFT1_TEX1_SHIFT; 291 } 292 293 if (sz != expected) 294 fprintf(stderr, "vertex size mismatch %d/%d\n", sz, expected); 295 296 return sz == expected; 297} 298 299static void 300i830_emit_invarient_state(struct intel_context *intel) 301{ 302 BATCH_LOCALS; 303 304 BEGIN_BATCH(29); 305 306 OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD); 307 OUT_BATCH(0); 308 309 OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD); 310 OUT_BATCH(0); 311 312 OUT_BATCH(_3DSTATE_DFLT_Z_CMD); 313 OUT_BATCH(0); 314 315 OUT_BATCH(_3DSTATE_FOG_MODE_CMD); 316 OUT_BATCH(FOGFUNC_ENABLE | 317 FOG_LINEAR_CONST | FOGSRC_INDEX_Z | ENABLE_FOG_DENSITY); 318 OUT_BATCH(0); 319 OUT_BATCH(0); 320 321 322 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | 323 MAP_UNIT(0) | 324 DISABLE_TEX_STREAM_BUMP | 325 ENABLE_TEX_STREAM_COORD_SET | 326 TEX_STREAM_COORD_SET(0) | 327 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0)); 328 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | 329 MAP_UNIT(1) | 330 DISABLE_TEX_STREAM_BUMP | 331 ENABLE_TEX_STREAM_COORD_SET | 332 TEX_STREAM_COORD_SET(1) | 333 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1)); 334 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | 335 MAP_UNIT(2) | 336 DISABLE_TEX_STREAM_BUMP | 337 ENABLE_TEX_STREAM_COORD_SET | 338 TEX_STREAM_COORD_SET(2) | 339 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2)); 340 OUT_BATCH(_3DSTATE_MAP_TEX_STREAM_CMD | 341 MAP_UNIT(3) | 342 DISABLE_TEX_STREAM_BUMP | 343 ENABLE_TEX_STREAM_COORD_SET | 344 TEX_STREAM_COORD_SET(3) | 345 ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3)); 346 347 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); 348 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0)); 349 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); 350 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1)); 351 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); 352 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2)); 353 OUT_BATCH(_3DSTATE_MAP_COORD_TRANSFORM); 354 OUT_BATCH(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3)); 355 356 OUT_BATCH(_3DSTATE_VERTEX_TRANSFORM); 357 OUT_BATCH(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE); 358 359 OUT_BATCH(_3DSTATE_W_STATE_CMD); 360 OUT_BATCH(MAGIC_W_STATE_DWORD1); 361 OUT_BATCH(0x3f800000 /* 1.0 in IEEE float */ ); 362 363 364 OUT_BATCH(_3DSTATE_COLOR_FACTOR_CMD); 365 OUT_BATCH(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */ 366 367 ADVANCE_BATCH(); 368} 369 370 371#define emit( intel, state, size ) \ 372 intel_batchbuffer_data(intel, state, size, false) 373 374static GLuint 375get_dirty(struct i830_hw_state *state) 376{ 377 return state->active & ~state->emitted; 378} 379 380static GLuint 381get_state_size(struct i830_hw_state *state) 382{ 383 GLuint dirty = get_dirty(state); 384 GLuint sz = 0; 385 GLuint i; 386 387 if (dirty & I830_UPLOAD_INVARIENT) 388 sz += 40 * sizeof(int); 389 390 if (dirty & I830_UPLOAD_RASTER_RULES) 391 sz += sizeof(state->RasterRules); 392 393 if (dirty & I830_UPLOAD_CTX) 394 sz += sizeof(state->Ctx); 395 396 if (dirty & I830_UPLOAD_BUFFERS) 397 sz += sizeof(state->Buffer); 398 399 if (dirty & I830_UPLOAD_STIPPLE) 400 sz += sizeof(state->Stipple); 401 402 for (i = 0; i < I830_TEX_UNITS; i++) { 403 if ((dirty & I830_UPLOAD_TEX(i))) 404 sz += sizeof(state->Tex[i]); 405 406 if (dirty & I830_UPLOAD_TEXBLEND(i)) 407 sz += state->TexBlendWordsUsed[i] * 4; 408 } 409 410 return sz; 411} 412 413 414/* Push the state into the sarea and/or texture memory. 415 */ 416static void 417i830_emit_state(struct intel_context *intel) 418{ 419 struct i830_context *i830 = i830_context(&intel->ctx); 420 struct i830_hw_state *state = &i830->state; 421 int i, count; 422 GLuint dirty; 423 drm_intel_bo *aper_array[3 + I830_TEX_UNITS]; 424 int aper_count; 425 GET_CURRENT_CONTEXT(ctx); 426 BATCH_LOCALS; 427 428 /* We don't hold the lock at this point, so want to make sure that 429 * there won't be a buffer wrap between the state emits and the primitive 430 * emit header. 431 * 432 * It might be better to talk about explicit places where 433 * scheduling is allowed, rather than assume that it is whenever a 434 * batchbuffer fills up. 435 */ 436 intel_batchbuffer_require_space(intel, 437 get_state_size(state) + INTEL_PRIM_EMIT_SIZE, 438 false); 439 count = 0; 440 again: 441 aper_count = 0; 442 dirty = get_dirty(state); 443 444 aper_array[aper_count++] = intel->batch.bo; 445 if (dirty & I830_UPLOAD_BUFFERS) { 446 aper_array[aper_count++] = state->draw_region->bo; 447 if (state->depth_region) 448 aper_array[aper_count++] = state->depth_region->bo; 449 } 450 451 for (i = 0; i < I830_TEX_UNITS; i++) 452 if (dirty & I830_UPLOAD_TEX(i)) { 453 if (state->tex_buffer[i]) { 454 aper_array[aper_count++] = state->tex_buffer[i]; 455 } 456 } 457 458 if (dri_bufmgr_check_aperture_space(aper_array, aper_count)) { 459 if (count == 0) { 460 count++; 461 intel_batchbuffer_flush(intel); 462 goto again; 463 } else { 464 _mesa_error(ctx, GL_OUT_OF_MEMORY, "i830 emit state"); 465 assert(0); 466 } 467 } 468 469 470 /* Do this here as we may have flushed the batchbuffer above, 471 * causing more state to be dirty! 472 */ 473 dirty = get_dirty(state); 474 state->emitted |= dirty; 475 assert(get_dirty(state) == 0); 476 477 if (dirty & I830_UPLOAD_INVARIENT) { 478 DBG("I830_UPLOAD_INVARIENT:\n"); 479 i830_emit_invarient_state(intel); 480 } 481 482 if (dirty & I830_UPLOAD_RASTER_RULES) { 483 DBG("I830_UPLOAD_RASTER_RULES:\n"); 484 emit(intel, state->RasterRules, sizeof(state->RasterRules)); 485 } 486 487 if (dirty & I830_UPLOAD_CTX) { 488 DBG("I830_UPLOAD_CTX:\n"); 489 emit(intel, state->Ctx, sizeof(state->Ctx)); 490 491 } 492 493 if (dirty & I830_UPLOAD_BUFFERS) { 494 GLuint count = 15; 495 496 DBG("I830_UPLOAD_BUFFERS:\n"); 497 498 if (state->depth_region) 499 count += 3; 500 501 BEGIN_BATCH(count); 502 OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR0]); 503 OUT_BATCH(state->Buffer[I830_DESTREG_CBUFADDR1]); 504 OUT_RELOC(state->draw_region->bo, 505 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); 506 507 if (state->depth_region) { 508 OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR0]); 509 OUT_BATCH(state->Buffer[I830_DESTREG_DBUFADDR1]); 510 OUT_RELOC(state->depth_region->bo, 511 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0); 512 } 513 514 OUT_BATCH(state->Buffer[I830_DESTREG_DV0]); 515 OUT_BATCH(state->Buffer[I830_DESTREG_DV1]); 516 OUT_BATCH(state->Buffer[I830_DESTREG_SENABLE]); 517 OUT_BATCH(state->Buffer[I830_DESTREG_SR0]); 518 OUT_BATCH(state->Buffer[I830_DESTREG_SR1]); 519 OUT_BATCH(state->Buffer[I830_DESTREG_SR2]); 520 521 assert(state->Buffer[I830_DESTREG_DRAWRECT0] != MI_NOOP); 522 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT0]); 523 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT1]); 524 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT2]); 525 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT3]); 526 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT4]); 527 OUT_BATCH(state->Buffer[I830_DESTREG_DRAWRECT5]); 528 ADVANCE_BATCH(); 529 } 530 531 if (dirty & I830_UPLOAD_STIPPLE) { 532 DBG("I830_UPLOAD_STIPPLE:\n"); 533 emit(intel, state->Stipple, sizeof(state->Stipple)); 534 } 535 536 for (i = 0; i < I830_TEX_UNITS; i++) { 537 if ((dirty & I830_UPLOAD_TEX(i))) { 538 DBG("I830_UPLOAD_TEX(%d):\n", i); 539 540 BEGIN_BATCH(I830_TEX_SETUP_SIZE + 1); 541 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0LI]); 542 543 OUT_RELOC(state->tex_buffer[i], 544 I915_GEM_DOMAIN_SAMPLER, 0, 545 state->tex_offset[i]); 546 547 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S1]); 548 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S2]); 549 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S3]); 550 OUT_BATCH(state->Tex[i][I830_TEXREG_TM0S4]); 551 OUT_BATCH(state->Tex[i][I830_TEXREG_MCS]); 552 OUT_BATCH(state->Tex[i][I830_TEXREG_CUBE]); 553 554 ADVANCE_BATCH(); 555 } 556 557 if (dirty & I830_UPLOAD_TEXBLEND(i)) { 558 DBG("I830_UPLOAD_TEXBLEND(%d): %d words\n", i, 559 state->TexBlendWordsUsed[i]); 560 emit(intel, state->TexBlend[i], state->TexBlendWordsUsed[i] * 4); 561 } 562 } 563 564 assert(get_dirty(state) == 0); 565} 566 567static void 568i830_destroy_context(struct intel_context *intel) 569{ 570 GLuint i; 571 struct i830_context *i830 = i830_context(&intel->ctx); 572 573 intel_region_release(&i830->state.draw_region); 574 intel_region_release(&i830->state.depth_region); 575 576 for (i = 0; i < I830_TEX_UNITS; i++) { 577 if (i830->state.tex_buffer[i] != NULL) { 578 drm_intel_bo_unreference(i830->state.tex_buffer[i]); 579 i830->state.tex_buffer[i] = NULL; 580 } 581 } 582 583 _tnl_free_vertices(&intel->ctx); 584} 585 586static uint32_t i830_render_target_format_for_mesa_format[MESA_FORMAT_COUNT] = 587{ 588 [MESA_FORMAT_ARGB8888] = DV_PF_8888, 589 [MESA_FORMAT_XRGB8888] = DV_PF_8888, 590 [MESA_FORMAT_RGB565] = DV_PF_565, 591 [MESA_FORMAT_ARGB1555] = DV_PF_1555, 592 [MESA_FORMAT_ARGB4444] = DV_PF_4444, 593}; 594 595static bool 596i830_render_target_supported(struct intel_context *intel, 597 struct gl_renderbuffer *rb) 598{ 599 gl_format format = rb->Format; 600 601 if (format == MESA_FORMAT_S8_Z24 || 602 format == MESA_FORMAT_X8_Z24 || 603 format == MESA_FORMAT_Z16) { 604 return true; 605 } 606 607 return i830_render_target_format_for_mesa_format[format] != 0; 608} 609 610static void 611i830_set_draw_region(struct intel_context *intel, 612 struct intel_region *color_regions[], 613 struct intel_region *depth_region, 614 GLuint num_regions) 615{ 616 struct i830_context *i830 = i830_context(&intel->ctx); 617 struct gl_context *ctx = &intel->ctx; 618 struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[0]; 619 struct intel_renderbuffer *irb = intel_renderbuffer(rb); 620 struct gl_renderbuffer *drb; 621 struct intel_renderbuffer *idrb = NULL; 622 GLuint value; 623 struct i830_hw_state *state = &i830->state; 624 uint32_t draw_x, draw_y; 625 626 if (state->draw_region != color_regions[0]) { 627 intel_region_reference(&state->draw_region, color_regions[0]); 628 } 629 if (state->depth_region != depth_region) { 630 intel_region_reference(&state->depth_region, depth_region); 631 } 632 633 /* 634 * Set stride/cpp values 635 */ 636 i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_CBUFADDR0], 637 color_regions[0], BUF_3D_ID_COLOR_BACK); 638 639 i915_set_buf_info_for_region(&state->Buffer[I830_DESTREG_DBUFADDR0], 640 depth_region, BUF_3D_ID_DEPTH); 641 642 /* 643 * Compute/set I830_DESTREG_DV1 value 644 */ 645 value = (DSTORG_HORT_BIAS(0x8) | /* .5 */ 646 DSTORG_VERT_BIAS(0x8) | DEPTH_IS_Z); /* .5 */ 647 648 if (irb != NULL) { 649 value |= i830_render_target_format_for_mesa_format[intel_rb_format(irb)]; 650 } 651 652 if (depth_region && depth_region->cpp == 4) { 653 value |= DEPTH_FRMT_24_FIXED_8_OTHER; 654 } 655 else { 656 value |= DEPTH_FRMT_16_FIXED; 657 } 658 state->Buffer[I830_DESTREG_DV1] = value; 659 660 drb = ctx->DrawBuffer->Attachment[BUFFER_DEPTH].Renderbuffer; 661 if (!drb) 662 drb = ctx->DrawBuffer->Attachment[BUFFER_STENCIL].Renderbuffer; 663 664 if (drb) 665 idrb = intel_renderbuffer(drb); 666 667 /* We set up the drawing rectangle to be offset into the color 668 * region's location in the miptree. If it doesn't match with 669 * depth's offsets, we can't render to it. 670 * 671 * (Well, not actually true -- the hw grew a bit to let depth's 672 * offset get forced to 0,0. We may want to use that if people are 673 * hitting that case. Also, some configurations may be supportable 674 * by tweaking the start offset of the buffers around, which we 675 * can't do in general due to tiling) 676 */ 677 FALLBACK(intel, I830_FALLBACK_DRAW_OFFSET, 678 idrb && irb && (idrb->draw_x != irb->draw_x || 679 idrb->draw_y != irb->draw_y)); 680 681 if (irb) { 682 draw_x = irb->draw_x; 683 draw_y = irb->draw_y; 684 } else if (idrb) { 685 draw_x = idrb->draw_x; 686 draw_y = idrb->draw_y; 687 } else { 688 draw_x = 0; 689 draw_y = 0; 690 } 691 692 state->Buffer[I830_DESTREG_DRAWRECT0] = _3DSTATE_DRAWRECT_INFO; 693 state->Buffer[I830_DESTREG_DRAWRECT1] = 0; 694 state->Buffer[I830_DESTREG_DRAWRECT2] = (draw_y << 16) | draw_x; 695 state->Buffer[I830_DESTREG_DRAWRECT3] = 696 ((ctx->DrawBuffer->Width + draw_x - 1) & 0xffff) | 697 ((ctx->DrawBuffer->Height + draw_y - 1) << 16); 698 state->Buffer[I830_DESTREG_DRAWRECT4] = (draw_y << 16) | draw_x; 699 state->Buffer[I830_DESTREG_DRAWRECT5] = MI_NOOP; 700 701 I830_STATECHANGE(i830, I830_UPLOAD_BUFFERS); 702} 703 704/** 705 * Update the hardware state for drawing into a window or framebuffer object. 706 * 707 * Called by glDrawBuffer, glBindFramebufferEXT, MakeCurrent, and other 708 * places within the driver. 709 * 710 * Basically, this needs to be called any time the current framebuffer 711 * changes, the renderbuffers change, or we need to draw into different 712 * color buffers. 713 */ 714static void 715i830_update_draw_buffer(struct intel_context *intel) 716{ 717 struct gl_context *ctx = &intel->ctx; 718 struct gl_framebuffer *fb = ctx->DrawBuffer; 719 struct intel_region *colorRegions[MAX_DRAW_BUFFERS], *depthRegion = NULL; 720 struct intel_renderbuffer *irbDepth = NULL, *irbStencil = NULL; 721 722 if (!fb) { 723 /* this can happen during the initial context initialization */ 724 return; 725 } 726 727 irbDepth = intel_get_renderbuffer(fb, BUFFER_DEPTH); 728 irbStencil = intel_get_renderbuffer(fb, BUFFER_STENCIL); 729 730 /* Do this here, not core Mesa, since this function is called from 731 * many places within the driver. 732 */ 733 if (ctx->NewState & _NEW_BUFFERS) { 734 /* this updates the DrawBuffer->_NumColorDrawBuffers fields, etc */ 735 _mesa_update_framebuffer(ctx); 736 /* this updates the DrawBuffer's Width/Height if it's a FBO */ 737 _mesa_update_draw_buffer_bounds(ctx); 738 } 739 740 if (fb->_Status != GL_FRAMEBUFFER_COMPLETE_EXT) { 741 /* this may occur when we're called by glBindFrameBuffer() during 742 * the process of someone setting up renderbuffers, etc. 743 */ 744 /*_mesa_debug(ctx, "DrawBuffer: incomplete user FBO\n");*/ 745 return; 746 } 747 748 /* How many color buffers are we drawing into? 749 * 750 * If there are zero buffers or the buffer is too big, don't configure any 751 * regions for hardware drawing. We'll fallback to software below. Not 752 * having regions set makes some of the software fallback paths faster. 753 */ 754 if ((fb->Width > ctx->Const.MaxRenderbufferSize) 755 || (fb->Height > ctx->Const.MaxRenderbufferSize) 756 || (fb->_NumColorDrawBuffers == 0)) { 757 /* writing to 0 */ 758 colorRegions[0] = NULL; 759 } 760 else if (fb->_NumColorDrawBuffers > 1) { 761 int i; 762 struct intel_renderbuffer *irb; 763 764 for (i = 0; i < fb->_NumColorDrawBuffers; i++) { 765 irb = intel_renderbuffer(fb->_ColorDrawBuffers[i]); 766 colorRegions[i] = (irb && irb->mt) ? irb->mt->region : NULL; 767 } 768 } 769 else { 770 /* Get the intel_renderbuffer for the single colorbuffer we're drawing 771 * into. 772 */ 773 if (_mesa_is_winsys_fbo(fb)) { 774 /* drawing to window system buffer */ 775 if (fb->_ColorDrawBufferIndexes[0] == BUFFER_FRONT_LEFT) 776 colorRegions[0] = intel_get_rb_region(fb, BUFFER_FRONT_LEFT); 777 else 778 colorRegions[0] = intel_get_rb_region(fb, BUFFER_BACK_LEFT); 779 } 780 else { 781 /* drawing to user-created FBO */ 782 struct intel_renderbuffer *irb; 783 irb = intel_renderbuffer(fb->_ColorDrawBuffers[0]); 784 colorRegions[0] = (irb && irb->mt->region) ? irb->mt->region : NULL; 785 } 786 } 787 788 if (!colorRegions[0]) { 789 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, true); 790 } 791 else { 792 FALLBACK(intel, INTEL_FALLBACK_DRAW_BUFFER, false); 793 } 794 795 /* Check for depth fallback. */ 796 if (irbDepth && irbDepth->mt) { 797 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false); 798 depthRegion = irbDepth->mt->region; 799 } else if (irbDepth && !irbDepth->mt) { 800 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, true); 801 depthRegion = NULL; 802 } else { /* !irbDepth */ 803 /* No fallback is needed because there is no depth buffer. */ 804 FALLBACK(intel, INTEL_FALLBACK_DEPTH_BUFFER, false); 805 depthRegion = NULL; 806 } 807 808 /* Check for stencil fallback. */ 809 if (irbStencil && irbStencil->mt) { 810 assert(intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24); 811 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false); 812 } else if (irbStencil && !irbStencil->mt) { 813 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, true); 814 } else { /* !irbStencil */ 815 /* No fallback is needed because there is no stencil buffer. */ 816 FALLBACK(intel, INTEL_FALLBACK_STENCIL_BUFFER, false); 817 } 818 819 /* If we have a (packed) stencil buffer attached but no depth buffer, 820 * we still need to set up the shared depth/stencil state so we can use it. 821 */ 822 if (depthRegion == NULL && irbStencil && irbStencil->mt 823 && intel_rb_format(irbStencil) == MESA_FORMAT_S8_Z24) { 824 depthRegion = irbStencil->mt->region; 825 } 826 827 /* 828 * Update depth and stencil test state 829 */ 830 ctx->Driver.Enable(ctx, GL_DEPTH_TEST, ctx->Depth.Test); 831 ctx->Driver.Enable(ctx, GL_STENCIL_TEST, 832 (ctx->Stencil.Enabled && fb->Visual.stencilBits > 0)); 833 834 intel->vtbl.set_draw_region(intel, colorRegions, depthRegion, 835 fb->_NumColorDrawBuffers); 836 intel->NewGLState |= _NEW_BUFFERS; 837 838 /* update viewport since it depends on window size */ 839 intelCalcViewport(ctx); 840 841 /* Set state we know depends on drawable parameters: 842 */ 843 ctx->Driver.Scissor(ctx, ctx->Scissor.X, ctx->Scissor.Y, 844 ctx->Scissor.Width, ctx->Scissor.Height); 845 846 ctx->Driver.DepthRange(ctx, ctx->Viewport.Near, ctx->Viewport.Far); 847 848 /* Update culling direction which changes depending on the 849 * orientation of the buffer: 850 */ 851 ctx->Driver.FrontFace(ctx, ctx->Polygon.FrontFace); 852} 853 854/* This isn't really handled at the moment. 855 */ 856static void 857i830_new_batch(struct intel_context *intel) 858{ 859 struct i830_context *i830 = i830_context(&intel->ctx); 860 i830->state.emitted = 0; 861} 862 863static void 864i830_assert_not_dirty( struct intel_context *intel ) 865{ 866 struct i830_context *i830 = i830_context(&intel->ctx); 867 assert(!get_dirty(&i830->state)); 868 (void) i830; 869} 870 871static void 872i830_invalidate_state(struct intel_context *intel, GLuint new_state) 873{ 874 struct gl_context *ctx = &intel->ctx; 875 876 _swsetup_InvalidateState(ctx, new_state); 877 _tnl_InvalidateState(ctx, new_state); 878 _tnl_invalidate_vertex_state(ctx, new_state); 879 880 if (new_state & _NEW_LIGHT) 881 i830_update_provoking_vertex(&intel->ctx); 882} 883 884static bool 885i830_is_hiz_depth_format(struct intel_context *intel, gl_format format) 886{ 887 return false; 888} 889 890void 891i830InitVtbl(struct i830_context *i830) 892{ 893 i830->intel.vtbl.check_vertex_size = i830_check_vertex_size; 894 i830->intel.vtbl.destroy = i830_destroy_context; 895 i830->intel.vtbl.emit_state = i830_emit_state; 896 i830->intel.vtbl.new_batch = i830_new_batch; 897 i830->intel.vtbl.reduced_primitive_state = i830_reduced_primitive_state; 898 i830->intel.vtbl.set_draw_region = i830_set_draw_region; 899 i830->intel.vtbl.update_draw_buffer = i830_update_draw_buffer; 900 i830->intel.vtbl.update_texture_state = i830UpdateTextureState; 901 i830->intel.vtbl.render_start = i830_render_start; 902 i830->intel.vtbl.render_prevalidate = i830_render_prevalidate; 903 i830->intel.vtbl.assert_not_dirty = i830_assert_not_dirty; 904 i830->intel.vtbl.finish_batch = intel_finish_vb; 905 i830->intel.vtbl.invalidate_state = i830_invalidate_state; 906 i830->intel.vtbl.render_target_supported = i830_render_target_supported; 907 i830->intel.vtbl.is_hiz_depth_format = i830_is_hiz_depth_format; 908} 909