1/*
2 $License:
3   Copyright 2011 InvenSense, Inc.
4
5 Licensed under the Apache License, Version 2.0 (the "License");
6 you may not use this file except in compliance with the License.
7 You may obtain a copy of the License at
8
9 http://www.apache.org/licenses/LICENSE-2.0
10
11 Unless required by applicable law or agreed to in writing, software
12 distributed under the License is distributed on an "AS IS" BASIS,
13 WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
14 See the License for the specific language governing permissions and
15 limitations under the License.
16  $
17 */
18
19#ifndef __MPU_H_
20#error Do not include this file directly.  Include mpu.h instead.
21#endif
22
23#ifndef __MPU3050_H_
24#define __MPU3050_H_
25
26#ifdef __KERNEL__
27#include <linux/types.h>
28#endif
29
30#if !defined CONFIG_MPU_SENSORS_MPU3050
31#error MPU6000 build including MPU3050 header
32#endif
33
34#define MPU_NAME "mpu3050"
35#define DEFAULT_MPU_SLAVEADDR       0x68
36
37/*==== MPU REGISTER SET ====*/
38enum mpu_register {
39	MPUREG_WHO_AM_I = 0,	/* 00 0x00 */
40	MPUREG_PRODUCT_ID,	/* 01 0x01 */
41	MPUREG_02_RSVD,		/* 02 0x02 */
42	MPUREG_03_RSVD,		/* 03 0x03 */
43	MPUREG_04_RSVD,		/* 04 0x04 */
44	MPUREG_XG_OFFS_TC,	/* 05 0x05 */
45	MPUREG_06_RSVD,		/* 06 0x06 */
46	MPUREG_07_RSVD,		/* 07 0x07 */
47	MPUREG_YG_OFFS_TC,	/* 08 0x08 */
48	MPUREG_09_RSVD,		/* 09 0x09 */
49	MPUREG_0A_RSVD,		/* 10 0x0a */
50	MPUREG_ZG_OFFS_TC,	/* 11 0x0b */
51	MPUREG_X_OFFS_USRH,	/* 12 0x0c */
52	MPUREG_X_OFFS_USRL,	/* 13 0x0d */
53	MPUREG_Y_OFFS_USRH,	/* 14 0x0e */
54	MPUREG_Y_OFFS_USRL,	/* 15 0x0f */
55	MPUREG_Z_OFFS_USRH,	/* 16 0x10 */
56	MPUREG_Z_OFFS_USRL,	/* 17 0x11 */
57	MPUREG_FIFO_EN1,	/* 18 0x12 */
58	MPUREG_FIFO_EN2,	/* 19 0x13 */
59	MPUREG_AUX_SLV_ADDR,	/* 20 0x14 */
60	MPUREG_SMPLRT_DIV,	/* 21 0x15 */
61	MPUREG_DLPF_FS_SYNC,	/* 22 0x16 */
62	MPUREG_INT_CFG,		/* 23 0x17 */
63	MPUREG_ACCEL_BURST_ADDR,/* 24 0x18 */
64	MPUREG_19_RSVD,		/* 25 0x19 */
65	MPUREG_INT_STATUS,	/* 26 0x1a */
66	MPUREG_TEMP_OUT_H,	/* 27 0x1b */
67	MPUREG_TEMP_OUT_L,	/* 28 0x1c */
68	MPUREG_GYRO_XOUT_H,	/* 29 0x1d */
69	MPUREG_GYRO_XOUT_L,	/* 30 0x1e */
70	MPUREG_GYRO_YOUT_H,	/* 31 0x1f */
71	MPUREG_GYRO_YOUT_L,	/* 32 0x20 */
72	MPUREG_GYRO_ZOUT_H,	/* 33 0x21 */
73	MPUREG_GYRO_ZOUT_L,	/* 34 0x22 */
74	MPUREG_23_RSVD,		/* 35 0x23 */
75	MPUREG_24_RSVD,		/* 36 0x24 */
76	MPUREG_25_RSVD,		/* 37 0x25 */
77	MPUREG_26_RSVD,		/* 38 0x26 */
78	MPUREG_27_RSVD,		/* 39 0x27 */
79	MPUREG_28_RSVD,		/* 40 0x28 */
80	MPUREG_29_RSVD,		/* 41 0x29 */
81	MPUREG_2A_RSVD,		/* 42 0x2a */
82	MPUREG_2B_RSVD,		/* 43 0x2b */
83	MPUREG_2C_RSVD,		/* 44 0x2c */
84	MPUREG_2D_RSVD,		/* 45 0x2d */
85	MPUREG_2E_RSVD,		/* 46 0x2e */
86	MPUREG_2F_RSVD,		/* 47 0x2f */
87	MPUREG_30_RSVD,		/* 48 0x30 */
88	MPUREG_31_RSVD,		/* 49 0x31 */
89	MPUREG_32_RSVD,		/* 50 0x32 */
90	MPUREG_33_RSVD,		/* 51 0x33 */
91	MPUREG_34_RSVD,		/* 52 0x34 */
92	MPUREG_DMP_CFG_1,	/* 53 0x35 */
93	MPUREG_DMP_CFG_2,	/* 54 0x36 */
94	MPUREG_BANK_SEL,	/* 55 0x37 */
95	MPUREG_MEM_START_ADDR,	/* 56 0x38 */
96	MPUREG_MEM_R_W,		/* 57 0x39 */
97	MPUREG_FIFO_COUNTH,	/* 58 0x3a */
98	MPUREG_FIFO_COUNTL,	/* 59 0x3b */
99	MPUREG_FIFO_R_W,	/* 60 0x3c */
100	MPUREG_USER_CTRL,	/* 61 0x3d */
101	MPUREG_PWR_MGM,		/* 62 0x3e */
102	MPUREG_3F_RSVD,		/* 63 0x3f */
103	NUM_OF_MPU_REGISTERS	/* 64 0x40 */
104};
105
106/*==== BITS FOR MPU ====*/
107
108/*---- MPU 'FIFO_EN1' register (12) ----*/
109#define BIT_TEMP_OUT                0x80
110#define BIT_GYRO_XOUT               0x40
111#define BIT_GYRO_YOUT               0x20
112#define BIT_GYRO_ZOUT               0x10
113#define BIT_ACCEL_XOUT              0x08
114#define BIT_ACCEL_YOUT              0x04
115#define BIT_ACCEL_ZOUT              0x02
116#define BIT_AUX_1OUT                0x01
117/*---- MPU 'FIFO_EN2' register (13) ----*/
118#define BIT_AUX_2OUT                0x02
119#define BIT_AUX_3OUT                0x01
120/*---- MPU 'DLPF_FS_SYNC' register (16) ----*/
121#define BITS_EXT_SYNC_NONE          0x00
122#define BITS_EXT_SYNC_TEMP          0x20
123#define BITS_EXT_SYNC_GYROX         0x40
124#define BITS_EXT_SYNC_GYROY         0x60
125#define BITS_EXT_SYNC_GYROZ         0x80
126#define BITS_EXT_SYNC_ACCELX        0xA0
127#define BITS_EXT_SYNC_ACCELY        0xC0
128#define BITS_EXT_SYNC_ACCELZ        0xE0
129#define BITS_EXT_SYNC_MASK          0xE0
130#define BITS_FS_250DPS              0x00
131#define BITS_FS_500DPS              0x08
132#define BITS_FS_1000DPS             0x10
133#define BITS_FS_2000DPS             0x18
134#define BITS_FS_MASK                0x18
135#define BITS_DLPF_CFG_256HZ_NOLPF2  0x00
136#define BITS_DLPF_CFG_188HZ         0x01
137#define BITS_DLPF_CFG_98HZ          0x02
138#define BITS_DLPF_CFG_42HZ          0x03
139#define BITS_DLPF_CFG_20HZ          0x04
140#define BITS_DLPF_CFG_10HZ          0x05
141#define BITS_DLPF_CFG_5HZ           0x06
142#define BITS_DLPF_CFG_2100HZ_NOLPF  0x07
143#define BITS_DLPF_CFG_MASK          0x07
144/*---- MPU 'INT_CFG' register (17) ----*/
145#define BIT_ACTL                    0x80
146#define BIT_ACTL_LOW                0x80
147#define BIT_ACTL_HIGH               0x00
148#define BIT_OPEN                    0x40
149#define BIT_OPEN_DRAIN              0x40
150#define BIT_PUSH_PULL               0x00
151#define BIT_LATCH_INT_EN            0x20
152#define BIT_INT_PULSE_WIDTH_50US    0x00
153#define BIT_INT_ANYRD_2CLEAR        0x10
154#define BIT_INT_STAT_READ_2CLEAR    0x00
155#define BIT_MPU_RDY_EN              0x04
156#define BIT_DMP_INT_EN              0x02
157#define BIT_RAW_RDY_EN              0x01
158/*---- MPU 'INT_STATUS' register (1A) ----*/
159#define BIT_INT_STATUS_FIFO_OVERLOW 0x80
160#define BIT_MPU_RDY                 0x04
161#define BIT_DMP_INT                 0x02
162#define BIT_RAW_RDY                 0x01
163/*---- MPU 'BANK_SEL' register (37) ----*/
164#define BIT_PRFTCH_EN               0x20
165#define BIT_CFG_USER_BANK           0x10
166#define BITS_MEM_SEL                0x0f
167/*---- MPU 'USER_CTRL' register (3D) ----*/
168#define BIT_DMP_EN                  0x80
169#define BIT_FIFO_EN                 0x40
170#define BIT_AUX_IF_EN               0x20
171#define BIT_AUX_RD_LENG             0x10
172#define BIT_AUX_IF_RST              0x08
173#define BIT_DMP_RST                 0x04
174#define BIT_FIFO_RST                0x02
175#define BIT_GYRO_RST                0x01
176/*---- MPU 'PWR_MGM' register (3E) ----*/
177#define BIT_H_RESET                 0x80
178#define BIT_SLEEP                   0x40
179#define BIT_STBY_XG                 0x20
180#define BIT_STBY_YG                 0x10
181#define BIT_STBY_ZG                 0x08
182#define BITS_CLKSEL                 0x07
183
184/*---- MPU Silicon Revision ----*/
185#define MPU_SILICON_REV_A4           1	/* MPU A4 Device */
186#define MPU_SILICON_REV_B1           2	/* MPU B1 Device */
187#define MPU_SILICON_REV_B4           3	/* MPU B4 Device */
188#define MPU_SILICON_REV_B6           4	/* MPU B6 Device */
189
190/*---- MPU Memory ----*/
191#define MPU_MEM_BANK_SIZE           (256)
192#define FIFO_HW_SIZE                (512)
193
194enum MPU_MEMORY_BANKS {
195	MPU_MEM_RAM_BANK_0 = 0,
196	MPU_MEM_RAM_BANK_1,
197	MPU_MEM_RAM_BANK_2,
198	MPU_MEM_RAM_BANK_3,
199	MPU_MEM_NUM_RAM_BANKS,
200	MPU_MEM_OTP_BANK_0 = MPU_MEM_NUM_RAM_BANKS,
201	/* This one is always last */
202	MPU_MEM_NUM_BANKS
203};
204
205/*---- structure containing control variables used by MLDL ----*/
206/*---- MPU clock source settings ----*/
207/*---- MPU filter selections ----*/
208enum mpu_filter {
209	MPU_FILTER_256HZ_NOLPF2 = 0,
210	MPU_FILTER_188HZ,
211	MPU_FILTER_98HZ,
212	MPU_FILTER_42HZ,
213	MPU_FILTER_20HZ,
214	MPU_FILTER_10HZ,
215	MPU_FILTER_5HZ,
216	MPU_FILTER_2100HZ_NOLPF,
217	NUM_MPU_FILTER
218};
219
220enum mpu_fullscale {
221	MPU_FS_250DPS = 0,
222	MPU_FS_500DPS,
223	MPU_FS_1000DPS,
224	MPU_FS_2000DPS,
225	NUM_MPU_FS
226};
227
228enum mpu_clock_sel {
229	MPU_CLK_SEL_INTERNAL = 0,
230	MPU_CLK_SEL_PLLGYROX,
231	MPU_CLK_SEL_PLLGYROY,
232	MPU_CLK_SEL_PLLGYROZ,
233	MPU_CLK_SEL_PLLEXT32K,
234	MPU_CLK_SEL_PLLEXT19M,
235	MPU_CLK_SEL_RESERVED,
236	MPU_CLK_SEL_STOP,
237	NUM_CLK_SEL
238};
239
240enum mpu_ext_sync {
241	MPU_EXT_SYNC_NONE = 0,
242	MPU_EXT_SYNC_TEMP,
243	MPU_EXT_SYNC_GYROX,
244	MPU_EXT_SYNC_GYROY,
245	MPU_EXT_SYNC_GYROZ,
246	MPU_EXT_SYNC_ACCELX,
247	MPU_EXT_SYNC_ACCELY,
248	MPU_EXT_SYNC_ACCELZ,
249	NUM_MPU_EXT_SYNC
250};
251
252#define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \
253	((ext_sync << 5) | (full_scale << 3) | lpf)
254
255#endif				/* __MPU3050_H_ */
256