1895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/* 2895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall $License: 3895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall Copyright 2011 InvenSense, Inc. 4895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 5895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall Licensed under the Apache License, Version 2.0 (the "License"); 6895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall you may not use this file except in compliance with the License. 7895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall You may obtain a copy of the License at 8895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 9895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall http://www.apache.org/licenses/LICENSE-2.0 10895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 11895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall Unless required by applicable law or agreed to in writing, software 12895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall distributed under the License is distributed on an "AS IS" BASIS, 13895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 14895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall See the License for the specific language governing permissions and 15895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall limitations under the License. 16895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall $ 17895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall */ 18895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 19895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#ifndef __MPU_H_ 20895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#error Do not include this file directly. Include mpu.h instead. 21895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#endif 22895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 23895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#ifndef __MPU3050_H_ 24895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define __MPU3050_H_ 25895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 26895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#ifdef __KERNEL__ 27895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#include <linux/types.h> 28895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#endif 29895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 30895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#if !defined CONFIG_MPU_SENSORS_MPU3050 31895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#error MPU6000 build including MPU3050 header 32895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#endif 33895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 34895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define MPU_NAME "mpu3050" 35895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define DEFAULT_MPU_SLAVEADDR 0x68 36895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 37895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*==== MPU REGISTER SET ====*/ 38895401859313187f15a800e62d43e6bcbf48fadaJP Abgrallenum mpu_register { 39895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_WHO_AM_I = 0, /* 00 0x00 */ 40895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_PRODUCT_ID, /* 01 0x01 */ 41895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_02_RSVD, /* 02 0x02 */ 42895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_03_RSVD, /* 03 0x03 */ 43895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_04_RSVD, /* 04 0x04 */ 44895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_XG_OFFS_TC, /* 05 0x05 */ 45895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_06_RSVD, /* 06 0x06 */ 46895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_07_RSVD, /* 07 0x07 */ 47895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_YG_OFFS_TC, /* 08 0x08 */ 48895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_09_RSVD, /* 09 0x09 */ 49895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_0A_RSVD, /* 10 0x0a */ 50895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_ZG_OFFS_TC, /* 11 0x0b */ 51895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_X_OFFS_USRH, /* 12 0x0c */ 52895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_X_OFFS_USRL, /* 13 0x0d */ 53895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_Y_OFFS_USRH, /* 14 0x0e */ 54895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_Y_OFFS_USRL, /* 15 0x0f */ 55895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_Z_OFFS_USRH, /* 16 0x10 */ 56895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_Z_OFFS_USRL, /* 17 0x11 */ 57895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_FIFO_EN1, /* 18 0x12 */ 58895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_FIFO_EN2, /* 19 0x13 */ 59895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_AUX_SLV_ADDR, /* 20 0x14 */ 60895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_SMPLRT_DIV, /* 21 0x15 */ 61895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_DLPF_FS_SYNC, /* 22 0x16 */ 62895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_INT_CFG, /* 23 0x17 */ 63895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_ACCEL_BURST_ADDR,/* 24 0x18 */ 64895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_19_RSVD, /* 25 0x19 */ 65895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_INT_STATUS, /* 26 0x1a */ 66895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_TEMP_OUT_H, /* 27 0x1b */ 67895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_TEMP_OUT_L, /* 28 0x1c */ 68895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_GYRO_XOUT_H, /* 29 0x1d */ 69895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_GYRO_XOUT_L, /* 30 0x1e */ 70895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_GYRO_YOUT_H, /* 31 0x1f */ 71895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_GYRO_YOUT_L, /* 32 0x20 */ 72895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_GYRO_ZOUT_H, /* 33 0x21 */ 73895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_GYRO_ZOUT_L, /* 34 0x22 */ 74895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_23_RSVD, /* 35 0x23 */ 75895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_24_RSVD, /* 36 0x24 */ 76895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_25_RSVD, /* 37 0x25 */ 77895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_26_RSVD, /* 38 0x26 */ 78895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_27_RSVD, /* 39 0x27 */ 79895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_28_RSVD, /* 40 0x28 */ 80895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_29_RSVD, /* 41 0x29 */ 81895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_2A_RSVD, /* 42 0x2a */ 82895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_2B_RSVD, /* 43 0x2b */ 83895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_2C_RSVD, /* 44 0x2c */ 84895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_2D_RSVD, /* 45 0x2d */ 85895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_2E_RSVD, /* 46 0x2e */ 86895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_2F_RSVD, /* 47 0x2f */ 87895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_30_RSVD, /* 48 0x30 */ 88895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_31_RSVD, /* 49 0x31 */ 89895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_32_RSVD, /* 50 0x32 */ 90895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_33_RSVD, /* 51 0x33 */ 91895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_34_RSVD, /* 52 0x34 */ 92895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_DMP_CFG_1, /* 53 0x35 */ 93895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_DMP_CFG_2, /* 54 0x36 */ 94895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_BANK_SEL, /* 55 0x37 */ 95895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_MEM_START_ADDR, /* 56 0x38 */ 96895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_MEM_R_W, /* 57 0x39 */ 97895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_FIFO_COUNTH, /* 58 0x3a */ 98895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_FIFO_COUNTL, /* 59 0x3b */ 99895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_FIFO_R_W, /* 60 0x3c */ 100895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_USER_CTRL, /* 61 0x3d */ 101895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_PWR_MGM, /* 62 0x3e */ 102895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPUREG_3F_RSVD, /* 63 0x3f */ 103895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall NUM_OF_MPU_REGISTERS /* 64 0x40 */ 104895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall}; 105895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 106895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*==== BITS FOR MPU ====*/ 107895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 108895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU 'FIFO_EN1' register (12) ----*/ 109895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_TEMP_OUT 0x80 110895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_GYRO_XOUT 0x40 111895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_GYRO_YOUT 0x20 112895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_GYRO_ZOUT 0x10 113895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_ACCEL_XOUT 0x08 114895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_ACCEL_YOUT 0x04 115895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_ACCEL_ZOUT 0x02 116895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_AUX_1OUT 0x01 117895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU 'FIFO_EN2' register (13) ----*/ 118895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_AUX_2OUT 0x02 119895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_AUX_3OUT 0x01 120895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU 'DLPF_FS_SYNC' register (16) ----*/ 121895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_EXT_SYNC_NONE 0x00 122895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_EXT_SYNC_TEMP 0x20 123895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_EXT_SYNC_GYROX 0x40 124895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_EXT_SYNC_GYROY 0x60 125895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_EXT_SYNC_GYROZ 0x80 126895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_EXT_SYNC_ACCELX 0xA0 127895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_EXT_SYNC_ACCELY 0xC0 128895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_EXT_SYNC_ACCELZ 0xE0 129895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_EXT_SYNC_MASK 0xE0 130895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_FS_250DPS 0x00 131895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_FS_500DPS 0x08 132895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_FS_1000DPS 0x10 133895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_FS_2000DPS 0x18 134895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_FS_MASK 0x18 135895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_DLPF_CFG_256HZ_NOLPF2 0x00 136895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_DLPF_CFG_188HZ 0x01 137895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_DLPF_CFG_98HZ 0x02 138895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_DLPF_CFG_42HZ 0x03 139895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_DLPF_CFG_20HZ 0x04 140895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_DLPF_CFG_10HZ 0x05 141895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_DLPF_CFG_5HZ 0x06 142895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_DLPF_CFG_2100HZ_NOLPF 0x07 143895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_DLPF_CFG_MASK 0x07 144895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU 'INT_CFG' register (17) ----*/ 145895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_ACTL 0x80 146895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_ACTL_LOW 0x80 147895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_ACTL_HIGH 0x00 148895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_OPEN 0x40 149895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_OPEN_DRAIN 0x40 150895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_PUSH_PULL 0x00 151895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_LATCH_INT_EN 0x20 152895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_INT_PULSE_WIDTH_50US 0x00 153895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_INT_ANYRD_2CLEAR 0x10 154895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_INT_STAT_READ_2CLEAR 0x00 155895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_MPU_RDY_EN 0x04 156895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_DMP_INT_EN 0x02 157895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_RAW_RDY_EN 0x01 158895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU 'INT_STATUS' register (1A) ----*/ 159895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_INT_STATUS_FIFO_OVERLOW 0x80 160895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_MPU_RDY 0x04 161895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_DMP_INT 0x02 162895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_RAW_RDY 0x01 163895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU 'BANK_SEL' register (37) ----*/ 164895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_PRFTCH_EN 0x20 165895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_CFG_USER_BANK 0x10 166895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_MEM_SEL 0x0f 167895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU 'USER_CTRL' register (3D) ----*/ 168895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_DMP_EN 0x80 169895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_FIFO_EN 0x40 170895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_AUX_IF_EN 0x20 171895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_AUX_RD_LENG 0x10 172895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_AUX_IF_RST 0x08 173895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_DMP_RST 0x04 174895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_FIFO_RST 0x02 175895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_GYRO_RST 0x01 176895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU 'PWR_MGM' register (3E) ----*/ 177895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_H_RESET 0x80 178895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_SLEEP 0x40 179895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_STBY_XG 0x20 180895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_STBY_YG 0x10 181895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BIT_STBY_ZG 0x08 182895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define BITS_CLKSEL 0x07 183895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 184895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU Silicon Revision ----*/ 185895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define MPU_SILICON_REV_A4 1 /* MPU A4 Device */ 186895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define MPU_SILICON_REV_B1 2 /* MPU B1 Device */ 187895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define MPU_SILICON_REV_B4 3 /* MPU B4 Device */ 188895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define MPU_SILICON_REV_B6 4 /* MPU B6 Device */ 189895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 190895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU Memory ----*/ 191895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define MPU_MEM_BANK_SIZE (256) 192895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define FIFO_HW_SIZE (512) 193895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 194895401859313187f15a800e62d43e6bcbf48fadaJP Abgrallenum MPU_MEMORY_BANKS { 195895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_MEM_RAM_BANK_0 = 0, 196895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_MEM_RAM_BANK_1, 197895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_MEM_RAM_BANK_2, 198895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_MEM_RAM_BANK_3, 199895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_MEM_NUM_RAM_BANKS, 200895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_MEM_OTP_BANK_0 = MPU_MEM_NUM_RAM_BANKS, 201895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall /* This one is always last */ 202895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_MEM_NUM_BANKS 203895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall}; 204895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 205895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- structure containing control variables used by MLDL ----*/ 206895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU clock source settings ----*/ 207895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall/*---- MPU filter selections ----*/ 208895401859313187f15a800e62d43e6bcbf48fadaJP Abgrallenum mpu_filter { 209895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FILTER_256HZ_NOLPF2 = 0, 210895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FILTER_188HZ, 211895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FILTER_98HZ, 212895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FILTER_42HZ, 213895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FILTER_20HZ, 214895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FILTER_10HZ, 215895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FILTER_5HZ, 216895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FILTER_2100HZ_NOLPF, 217895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall NUM_MPU_FILTER 218895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall}; 219895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 220895401859313187f15a800e62d43e6bcbf48fadaJP Abgrallenum mpu_fullscale { 221895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FS_250DPS = 0, 222895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FS_500DPS, 223895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FS_1000DPS, 224895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_FS_2000DPS, 225895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall NUM_MPU_FS 226895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall}; 227895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 228895401859313187f15a800e62d43e6bcbf48fadaJP Abgrallenum mpu_clock_sel { 229895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_CLK_SEL_INTERNAL = 0, 230895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_CLK_SEL_PLLGYROX, 231895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_CLK_SEL_PLLGYROY, 232895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_CLK_SEL_PLLGYROZ, 233895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_CLK_SEL_PLLEXT32K, 234895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_CLK_SEL_PLLEXT19M, 235895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_CLK_SEL_RESERVED, 236895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_CLK_SEL_STOP, 237895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall NUM_CLK_SEL 238895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall}; 239895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 240895401859313187f15a800e62d43e6bcbf48fadaJP Abgrallenum mpu_ext_sync { 241895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_EXT_SYNC_NONE = 0, 242895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_EXT_SYNC_TEMP, 243895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_EXT_SYNC_GYROX, 244895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_EXT_SYNC_GYROY, 245895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_EXT_SYNC_GYROZ, 246895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_EXT_SYNC_ACCELX, 247895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_EXT_SYNC_ACCELY, 248895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall MPU_EXT_SYNC_ACCELZ, 249895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall NUM_MPU_EXT_SYNC 250895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall}; 251895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 252895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#define DLPF_FS_SYNC_VALUE(ext_sync, full_scale, lpf) \ 253895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall ((ext_sync << 5) | (full_scale << 3) | lpf) 254895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall 255895401859313187f15a800e62d43e6bcbf48fadaJP Abgrall#endif /* __MPU3050_H_ */ 256