0c2dc522d0e120f346cf0a40c8cf0c93346131c2 |
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03-Jul-2012 |
Dong-Yuan Chen <dong-yuan.chen@intel.com> |
[X86] X86 trace JIT compiler support This patch provides a fully functional x86 trace JIT compiler for Dalvik VM. It is built on top of the existing x86 fast interpreter with bug fixes and needed extension to support trace JIT interface. The x86 trace JIT code generator was developed independent of the existing template-based code generator and thus does not share exactly the same infrastructure. Included in this patch are: * Deprecated and removed the x86-atom fast interpreter that is no longer functional since ICS. * Augmented x86 fast interpreter to provide interfaces for x86 trace JIT compiler. * Added x86 trace JIT code generator with full JDWP debugging support. * Method JIT and self-verification mode are not supported. The x86 code generator uses the x86 instruction encoder/decoder library from the Apache Harmony project. Additional wrapper extension and bug fixes were added to support the x86 trace JIT code generator. The x86 instruction encoder/decoder is embedded inside the x86 code generator under the libenc subdirectory. Change-Id: I241113681963a16c13a3562390813cbaaa6eedf0 Signed-off-by: Dong-Yuan Chen <dong-yuan.chen@intel.com> Signed-off-by: Yixin Shou <yixin.shou@intel.com> Signed-off-by: Johnnie Birch <johnnie.l.birch.jr@intel.com> Signed-off-by: Udayan <udayan.banerji@intel.com> Signed-off-by: Sushma Kyasaralli Thimmappa <sushma.kyasaralli.thimmappa@intel.com> Signed-off-by: Bijoy Jose <bijoy.a.jose@intel.com> Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Signed-off-by: Tim Hartley <timothy.d.hartley@intel.com>
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30bc0d46ae730d78c42c39cfa56a59ba3025380b |
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22-Apr-2011 |
buzbee <buzbee@google.com> |
Consolidate curFrame fields in thread storage We ended up with two locations in the Thread structure for saved Dalvik frame pointer. This change consolidates them. Change-Id: I78f288e4e57e232f29663be930101e775bfe370f
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9a3147c7412f4794434b4c2604aa2ba784867774 |
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03-Mar-2011 |
buzbee <buzbee@google.com> |
Interpreter restructuring This is a restructuring of the Dalvik ARM and x86 interpreters: o Combine the old portstd and portdbg interpreters into a single portable interpreter. o Add debug/profiling support to the fast (mterp) interpreters. o Delete old mechansim of switching between interpreters. Now, once you choose an interpreter at startup, you stick with it. o Allow JIT to co-exist with profiling & debugging (necessary for first-class support of debugging with the JIT active). o Adds single-step capability to the fast assembly interpreters without slowing them down (and, in fact, measurably improves their performance). o Remove old "polling for safe point" mechanism. Breakouts now achieved via modifying base of interpreter handler table. o Simplify interpeter control mechanism. o Allow thread-granularity control for profiling & debugging The primary motivation behind this change was to improve the responsiveness of debugging and profiling and to make it easier to add new debugging and profiling capabilities in the future. Instead of always bailing out to the slow debug portable interpreter, we can now stay in the fast interpreter. A nice side effect of the change is that the fast interpreters got a healthy speed boost because we were able to replace the polling safepoint check that involved a dozen or so instructions with a single table-base reload. When combined with the two earlier CLs related to this restructuring, we show a 5.6% performance improvement using libdvm_interp.so on the Checkers benchmark relative to Honeycomb. Change-Id: I8d37e866b3618def4e582fc73f1cf69ffe428f3c
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4570ad0a7706d3338d58bd0204e102719e4d68fb |
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09-Mar-2011 |
Eugene Surovegin <surovegin@google.com> |
x86: restore standard stack frame layout and fix stack alignment. Native x86 can contain SSE instructions, this requires 16-byte aligned stack which is what GCC expects these days. Enforce this in dvmPlatformInvoke and in mterp. Also fix stack frame layout, so debuggers can produce backtraces across dvmMterpStdRun invocations. Change-Id: I43d00a6bf8210b7d3aa9276edabc08978084e4f2
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a7d59bbafea5430fe81fc21ba94ddf6f6a63b0b3 |
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24-Feb-2011 |
buzbee <buzbee@google.com> |
New interpreter breakout mechanism Introduce parallel handler entry points for mterp interpreters as a step towards fully supporting debug, profile and JIT within mterp (instead of bailing out to the portable debug interpreter). This CL contains most of the structural changes that need to happen, but does not yet enable the new switch mode. In short, within the mterp assembly interpreter register rIBASE points to an array of handlers for Dalvik opcodes. Instead of periodically checking for suspend, debug, profiling and JIT trace selection breakouts, rIBASE may simply be altered to point to the parallel breakout handlers when control needs to be rerouted. This will enable us to eliminate the separate portable debug interpreter and the entire mechanism of switching between the fast and portable interpreters. The x86 implementation required a large number of changes because of the need to dedicate a register to holding the table base. It will now use %edx (which was previously scratch). Changes include: o Support for two styles of mterp assembly code generation: computed goto and jump table (ARM uses computed goto, x86 uses jump table) o New mterp config operators to trigger generation of alternate entry points. o Alternate entries route execution through new dvmCheckInst(). That's where the checking code will go. o For x86, reserved register edx as dedicated rIBASE. o For jump-table mterps, ignore "%break" operator and allow variable-sized handlers with no "sister" region. Note that the x86-atom implementation will need substantial changes to function in this new model. Change-Id: I3a22048adb7dcfdeba4f94fbb977b26c3ab2fcb3
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9f601a917c8878204482c37aec7005054b6776fa |
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12-Feb-2011 |
buzbee <buzbee@google.com> |
Interpreter restructuring: eliminate InterpState The key datastructure for the interpreter is InterpState. This change eliminates it, merging its data with the Thread structure. Here's why: In principio creavit Fadden Thread et InterpState. And it was good. Thread holds thread-private state, while InterpState captures data associated with a Dalvik interpreter activation. Because JNI calls can result in nested interpreter invocations, we can have more than one InterpState for each actual thread. InterpState was relatively small, and it all worked well. It was used enough that in the Arm version a register (rGLUE) was dedicated to it. Then, along came the JIT guys, who saw InterpState as a convenient place to dump all sorts of useful data that they wanted quick access to through that dedicated register. InterpState grew and grew. In terms of space, this wasn't a big problem - but it did mean that the initialization cost of each interpreter activation grew as well. For applications that do a lot of callbacks from native code into Dalvik, this is measurable. It's also mostly useless cost because much of the JIT-related InterpState initialization was setting up useful constants - things that don't need to be saved and restored all the time. The biggest problem, though, deals with thread control. When something interesting is happening that needs all threads to be stopped (such as GC and debugger attach), we have access to all of the Thread structures, but we don't have access to all of the InterpState structures (which may be buried/nested on the native stack). As a result, polling for thread suspension is done via a one-indirection pointer chase. InterpState itself can't hold the stop bits because we can't always find it, so instead it holds a pointer to the global or thread-specific stop control. Yuck. With this change, we eliminate InterpState and merge all needed data into Thread. Further, we replace the decidated rGLUE register with a pointer to the Thread structure (rSELF). The small subset of state data that needs to be saved and restored across nested interpreter activations is collected into a record that is saved to the interpreter frame, and restored on exit. Further, these small records are linked together to allow tracebacks to show nested activations. Old InterpState variables that simply contain useful constants are initialized once at thread creation time. This CL is large enough by itself that the new ability to streamline suspend checks is not done here - that will happen in a future CL. Here we just focus on consolidation. Change-Id: Ide6b2fb85716fea454ac113f5611263a96687356
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750d110b62cef538e193b6f91f5239b0c4b63ef1 |
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12-Feb-2011 |
Andy McFadden <fadden@android.com> |
Rename invoke-direct-empty to invoke-object-init The invoke-direct-empty instruction was introduced to remove the overhead of calling the empty Object constructor. We now need it to do some extra work on behalf of object construction, so it's appropriate to change the instruction name to match the role it fills rather than the more general role it was hoped to fill. No functional changes. Bug 3342343 Change-Id: I65dd6a2c00c99581c9a19b16fe193b70642c8fbb
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71eee1f0c2eb514585fdbee16730c9c2209e8f68 |
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04-Jan-2011 |
jeffhao <jeffhao@google.com> |
Added vm support for new jumbo opcodes. This enables jumbo opcodes by default, and they will get used by the current build without modification. Support has been added for arm, x86, and the portable interpreter. x86-atom support is on the TODO list. This commit also includes a test for the new jumbo opcodes. Change-Id: Ic3f1b41b51645861c5196f76aaf0e96e727ea537
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90f15431b24a4004fab2db70f273155fcd1c42a4 |
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03-Dec-2010 |
Dan Bornstein <danfuzz@android.com> |
Make opcode 00ff be called "dispatch-ff". With this change, it's still implemented as an unused opcode, but it's now ready for its new life! Change-Id: Ic70d311704925067e47d87b657d133a792144e65
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c11e0e14df2c0c4264e5cc6c3e96d14832cbecad |
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22-Sep-2010 |
buzbee <buzbee@google.com> |
Fix x86 mterp "longjmp" The recent x86 mterp update failed to properly restore callee save registers when returning from the call to dvmMterpStdRun. Change-Id: Ied73cc5fb380a6375d1f71ce679003fbc293d08d
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f3e177289ac078f18401cfd8eebafe584dd0d01f |
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12-Sep-2010 |
buzbee <buzbee@google.com> |
x86 mterp: reduce x86/x86-atom differences To ease future x86 development, elminate unnecessary differences between x86 and x86-atom targets. 1. Macros instead of defines (cosmetic change) 2. Register naming convention (cosmetic change) 3. Register usage convention - Drop rIBASE, freeing %edx for general usage - use %edi for rPC (callee-save) & eliminate spills 4. Spill & temp frame layout 5. rGLUE usage 0(%ebp) instead of -24(%ebp) 6. Jump table transition between instruction interpretations instead of computed goto. 7. Change entry convention for instruction handlers: Previously: %bl contains 8-bit Dalvik opcode %bh contains 2nd half of 16-bit Dalvik insn (usually AA or BA) upper 16 bits of %ebx are zero Now: %bl contains 2nd half of 16-bit Dalvik insn (usually AA or BA) upper 24 bits of %ebx are zero 8. Include copies of x86-atom macros and defines into x86 build. This allows the x86 build to mix-and-match x86 and x86-atom handlers via the normal config mechanism. [Note - only for non-control-flow instructions. There are still some conflicts in the footer.S main loop re-entry points]. Change-Id: Ib9d549b56f7ffd7420f9dbf97b2169f65603ee83
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f6c387128427e121477c1b32ad35cdcaa5101ba3 |
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04-Mar-2009 |
The Android Open Source Project <initial-contribution@android.com> |
auto import from //depot/cupcake/@135843
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f72d5de56a522ac3be03873bdde26f23a5eeeb3c |
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04-Mar-2009 |
The Android Open Source Project <initial-contribution@android.com> |
auto import from //depot/cupcake/@135843
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89c1feb0a69a7707b271086e749975b3f7acacf7 |
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18-Dec-2008 |
The Android Open Source Project <initial-contribution@android.com> |
Code drop from //branches/cupcake/...@124589
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