| 3492eefa4b2509c87598678a6977074a3f6a50e6 |
|
07-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Use VSrc_* register classes as the default classes for types
Since the VSrc_* register classes contain both VGPRs and SGPRs, copies
that used be emitted by isel like this:
SGPR = COPY VGPR
Will now be emitted like this:
VSrC = COPY VGPR
This patch also adds a pass that tries to identify and fix situations where
a VGPR to SGPR copy may occur. Hopefully, these changes will make it
impossible for the compiler to generate illegal VGPR to SGPR copies.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187831 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
|
| 692ee102ebef535d311c35d53457028083e5c5be |
|
01-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add 64-bit float load/store support
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
|
| 8ea83d499935f406f9fc190de783710c2293ab63 |
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24-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Treat CONSTANT_ADDRESS loads like GLOBAL_ADDRESS loads when necessary
These are really the same address space in hardware. The only
difference is that CONSTANT_ADDRESS uses a special cache for faster
access. When we are unable to use the constant kcache for some reason
(e.g. smaller types or lack of indirect addressing) then the instruction
selector must use GLOBAL_ADDRESS loads instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187006 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
|
| 3f5d63b95618860ca69eeab9be37cf26a253150e |
|
23-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Add support for 24-bit MUL instructions
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186922 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
|
| 20027547b98c0867fa92f3c18eddaa417f3f44da |
|
23-Jul-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Rename AMDILISelDAGToDAG.cpp -> AMDGPUISelDAGToDAG.cpp
Reviewed-by: Vincent Lejeune <vljn at ovi.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186920 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/AMDGPUISelDAGToDAG.cpp
|