| c18f4efc5dd24adcc653806455fc7ae8508e9c66 |
|
28-Jul-2013 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added encoding prefixes for KNL instructions (EVEX).
Added 512-bit operands printing.
Added instruction formats for KNL instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187324 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c208c43a8ac5bfd3ee09b048cbc3f760691cefad |
|
07-May-2013 |
Michael Kuperstein <michael.m.kuperstein@intel.com> |
Re-enable AVX detection on x64 platforms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181313 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 3ff641f22215d0add0ab29648c7fca45af34ffda |
|
03-May-2013 |
Aaron Ballman <aaron@aaronballman.com> |
Unbreaking the non-x86 build bots by protecting the AVX test code properly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180992 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f57563b61b0b3604a25c6388714068713e027e18 |
|
03-May-2013 |
Aaron Ballman <aaron@aaronballman.com> |
Correctly testing for AVX support in x86 based off code from Hosts.cpp.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180991 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| d6ac8e9a03d8fa7115079d86192bc4529e8281aa |
|
25-Apr-2013 |
Preston Gurd <preston.gurd@intel.com> |
This patch adds the X86FixupLEAs pass, which will reduce instruction
latency for certain models of the Intel Atom family, by converting
instructions into their equivalent LEA instructions, when it is both
useful and possible to do so.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f5ebc39fc5d69a800d38f8f6a585d06e61519ab0 |
|
03-Apr-2013 |
Eric Christopher <echristo@gmail.com> |
Formatting.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178589 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c26392aa5d9c2dbca2909d6874d181455f8aeb8f |
|
29-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add support of RDSEED defined in AVX2 extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 5a8386e1dfc9897bde39be2519bb5a6949623f64 |
|
28-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add ADX CPUID detection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 1edadea42f6f5c393b4fdb9d7ce1cf7eb9c24ab4 |
|
27-Mar-2013 |
Preston Gurd <preston.gurd@intel.com> |
For the current Atom processor, the fastest way to handle a call
indirect through a memory address is to load the memory address into
a register and then call indirect through the register.
This patch implements this improvement by modifying SelectionDAG to
force a function address which is a memory reference to be loaded
into a virtual register.
Patch by Sriram Murali.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 0ca1a7f177ffd29c0af49f23cc7bd5f0b56a60d0 |
|
26-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add HLE target feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178082 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 675eb3b9ac547119f6db676ebdd172d40a797b1c |
|
26-Mar-2013 |
Michael Liao <michael.liao@intel.com> |
Add PREFETCHW codegen support
- Add 'PRFCHW' feature defined in AVX2 ISA extension
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178040 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f8b80de1a952f14921c3137545e05575ea88e4ab |
|
27-Feb-2013 |
Nadav Rotem <nrotem@apple.com> |
Revert r176166 because it broke one of the lit tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176171 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| e7c52282dd1b0f2d53c72c0036e28badb43221b6 |
|
27-Feb-2013 |
Nadav Rotem <nrotem@apple.com> |
std::string to StringRef.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 901d80065c9afa0ba33e8546c2e1e99a00aceb14 |
|
16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Reinitialize the ivars in the subtarget so that they can be reset with the new features.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ba6867d0ce3de9b7b4385f98d215edfcd36c4b32 |
|
16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Temporary revert of 175320.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175322 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 9be8b4fc92e1ace819a78db512c1f945c1471be7 |
|
16-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Reinitialize the ivars in the subtarget.
When we're recalculating the feature set of the subtarget, we need to have the
ivars in their initial state.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175320 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 789cb5df9ca61f8a3794a4fbde7cc020fd00a02a |
|
15-Feb-2013 |
Bill Wendling <isanbard@gmail.com> |
Use the 'target-features' and 'target-cpu' attributes to reset the subtarget features.
If two functions require different features (e.g., `-mno-sse' vs. `-msse') then
we want to honor that, especially during LTO. We can do that by resetting the
subtarget's features depending upon the 'target-feature' attribute.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175314 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 7b672ed380cf44894f8b96c52558dcfc136af383 |
|
14-Feb-2013 |
Kay Tiong Khoo <kkhoo@perfwizard.com> |
added basic support for Intel ADX instructions
-feature flag, instructions definitions, test cases
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175196 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| a66f40a8cc685b2869e7f8d988f9a17439875ece |
|
30-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Restrict sin/cos optimization to 64-bit only for now. 32-bit is a bit messy and less critical.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173987 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 8688a58c53b46d2dda9bf50dafd5195790a7ed58 |
|
29-Jan-2013 |
Evan Cheng <evan.cheng@apple.com> |
Teach SDISel to combine fsin / fcos into a fsincos node if the following
conditions are met:
1. They share the same operand and are in the same BB.
2. Both outputs are used.
3. The target has a native instruction that maps to ISD::FSINCOS node or
the target provides a sincos library call.
Implemented the generic optimization in sdisel and enabled it for
Mac OSX. Also added an additional optimization for x86_64 Mac OSX by
using an alternative entry point __sincos_stret which returns the two
results in xmm0 / xmm1.
rdar://13087969
PR13204
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c7b902e7fe3498503efbfd98cabb1b1c67cadda6 |
|
08-Jan-2013 |
Preston Gurd <preston.gurd@intel.com> |
Pad Short Functions for Intel Atom
The current Intel Atom microarchitecture has a feature whereby
when a function returns early then it is slightly faster to execute
a sequence of NOP instructions to wait until the return address is ready,
as opposed to simply stalling on the ret instruction until
the return address is ready.
When compiling for X86 Atom only, this patch will run a pass,
called "X86PadShortFunction" which will add NOP instructions where less
than four cycles elapse between function entry and return.
It includes tests.
This patch has been updated to address Nadav's review comments
- Optimize only at >= O1 and don't do optimization if -Os is set
- Stores MachineBasicBlock* instead of BBNum
- Uses DenseMap instead of std::map
- Fixes placement of braces
Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 5d1f5c17377e56d88a525cf82d02e6e5df254580 |
|
05-Jan-2013 |
Nadav Rotem <nrotem@apple.com> |
Revert revision 171524. Original message:
URL: http://llvm.org/viewvc/llvm-project?rev=171524&view=rev
Log:
The current Intel Atom microarchitecture has a feature whereby when a function
returns early then it is slightly faster to execute a sequence of NOP
instructions to wait until the return address is ready,
as opposed to simply stalling on the ret instruction
until the return address is ready.
When compiling for X86 Atom only, this patch will run a pass, called
"X86PadShortFunction" which will add NOP instructions where less than four
cycles elapse between function entry and return.
It includes tests.
Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| dd30b471750aca5c652873f9a8972df162b7e5eb |
|
04-Jan-2013 |
Preston Gurd <preston.gurd@intel.com> |
The current Intel Atom microarchitecture has a feature whereby when a function
returns early then it is slightly faster to execute a sequence of NOP
instructions to wait until the return address is ready,
as opposed to simply stalling on the ret instruction
until the return address is ready.
When compiling for X86 Atom only, this patch will run a pass, called
"X86PadShortFunction" which will add NOP instructions where less than four
cycles elapse between function entry and return.
It includes tests.
Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171524 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 0b8c9a80f20772c3793201ab5b251d3520b9cea3 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.
There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.
The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.
I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).
I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 2c0575f2f4ce9a2db1472ee9d17aff1b0b658960 |
|
10-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Fix a typo in my previous commit -- bloomfield is 0x1A not 0x2A.
Thanks to the PaX folks for noticing in review! We need some tests here,
any sugestions welcome...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169739 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 9f3f40f6efe7085999e800d1c562e400d8b2211c |
|
10-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Address a FIXME and update the fast unaligned memory feature for newer
Intel chips.
The model number rules were determined by inspecting Intel's
documentation for their newer chip model numbers. My understanding is
that all of the newer Intel chips have fast unaligned memory access, but
if anyone is concerned about a particular chip, just shout.
No tests updated; it's not clear we have dedicated tests for the chips'
various features, but if anyone would like tests (or can point me at
some existing ones), I'm happy to oblige.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169730 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| d04a8d4b33ff316ca4cf961e06c9e312eff8e64f |
|
03-Dec-2012 |
Chandler Carruth <chandlerc@gmail.com> |
Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.
Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169131 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 64f03673d20931b0c3c8f388988fc4dd29626182 |
|
09-Nov-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Switch FreeBSD/i386 back to 4byte stack alignment. This partially
reverts r126226.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| be02a90de17f857ba65bbd8a11653ca1bad30adc |
|
08-Nov-2012 |
Michael Liao <michael.liao@intel.com> |
Add support of RTM from TSX extension
- Add RTM code generation support throught 3 X86 intrinsics:
xbegin()/xend() to start/end a transaction region, and xabort() to abort a
tranaction region
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167573 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 39817f9d393fdc29ec35fc8626d8b372415df414 |
|
08-Oct-2012 |
Andrew Trick <atrick@apple.com> |
misched: remove the unused getSpecialAddressLatency hook.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| bfcb4aa10b5948539f6ee59eecfe88faa9fc4e94 |
|
03-Oct-2012 |
Preston Gurd <preston.gurd@intel.com> |
Set up MCSchedModel after detecting the CPU type in X86SubTarget.
Corrects a problem whereby MCSchedModel was not being set up when
the CPU type was auto-detected.
Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 2e2efd960056bbb7e4bbd843c8de55116d52aa7d |
|
04-Sep-2012 |
Preston Gurd <preston.gurd@intel.com> |
Generic Bypass Slow Div
- CodeGenPrepare pass for identifying div/rem ops
- Backend specifies the type mapping using addBypassSlowDivType
- Enabled only for Intel Atom with O2 32-bit -> 8-bit
- Replace IDIV with instructions which test its value and use DIVB if the value
is positive and less than 256.
- In the case when the quotient and remainder of a divide are used a DIV
and a REM instruction will be present in the IR. In the non-Atom case
they are both lowered to IDIVs and CSE removes the redundant IDIV instruction,
using the quotient and remainder from the first IDIV. However,
due to this optimization CSE is not able to eliminate redundant
IDIV instructions because they are located in different basic blocks.
This is overcome by calculating both the quotient (DIV) and remainder (REM)
in each basic block that is inserted by the optimization and reusing the result
values when a subsequent DIV or REM instruction uses the same operands.
- Test cases check for the presents of the optimization when calculating
either the quotient, remainder, or both.
Patch by Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163150 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| de7f1c251705cad8dc86f498402045235ff8aaaa |
|
13-Aug-2012 |
Manman Ren <mren@apple.com> |
X86: when auto-detecting the subtarget features, make sure use IsIntel to detect
Nehalem, Westmere and Sandy Bridge. AMD also has processor family 6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 743a2cff0422031da007bcdc70ced28c09057aea |
|
11-Aug-2012 |
Manman Ren <mren@apple.com> |
X86: when we are auto-detecting the subtarget features, make sure we turn on
FeatureFastUAMem for Nehalem, Westmere and Sandy Bridge.
FeatureFastUAMem is already on if we pass in nehalem or westmere as a command
argument.
rdar: 7252306
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161717 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c42a7017864fc62bfff36c1b8b7f4cd68e198861 |
|
07-Aug-2012 |
Andrew Trick <atrick@apple.com> |
Allow x86 subtargets to use the GenericModel defined in X86Schedule.td.
This allows codegen passes to query properties like
InstrItins->SchedModel->IssueWidth. It also ensure's that
computeOperandLatency returns the X86 defaults for loads and "high
latency ops". This should have no significant impact on existing
schedulers because X86 defaults happen to be the same as global
defaults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| a20e1e7ef596842127794372244fd5c646f71296 |
|
01-Aug-2012 |
Chad Rosier <mcrosier@apple.com> |
Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| fd012b2e040ad0335c5163e85fbee4869328ad14 |
|
19-Jul-2012 |
Preston Gurd <preston.gurd@intel.com> |
Adds the family codes for the Midview Atom processors so that the
Atom buildbot will auto-detect Atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| d4d961615c67082bc24bfa5d372a93a1dcff3457 |
|
18-Jul-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch fixes 8 out of 20 unexpected failures in "make check"
when run on an Intel Atom processor. The failures have arisen due
to changes elsewhere in the trunk over the past 8 weeks or so.
These failures were not detected by the Atom buildbot because the
CPU on the Atom buildbot was not being detected as an Atom CPU.
The fix for this problem is in Host.cpp and X86Subtarget.cpp, but
shall remain commented out until the current set of Atom test failures
are fixed.
Patch by Andy Zhang and Tyler Nowicki!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160451 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| a15f9d53114a86005b260cbc451b0c63aa92bc1d |
|
03-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Rename FMA3 feature flag to just FMA to match gcc so it can be added to clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157903 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 14f094bb2b1d72266d8d29daddb27ec3b1be5e14 |
|
01-Jun-2012 |
Craig Topper <craig.topper@gmail.com> |
Enable automatic detection of FMA3 support to allow intrinsics to be used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157805 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c8e340da823e8ff10b947429ef99e34ffc3067d8 |
|
31-May-2012 |
Benjamin Kramer <benny.kra@googlemail.com> |
X86: Rename the CLMUL target feature to PCLMUL.
It was renamed in gcc/gas a while ago and causes all kinds of
confusion because it was named differently in llvm and clang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 177cf1e1a3685209ab805f82897902a8d2b61661 |
|
31-May-2012 |
Elena Demikhovsky <elena.demikhovsky@intel.com> |
Added FMA3 Intel instructions.
I disabled FMA3 autodetection, since the result may differ from expected for some benchmarks.
I added tests for GodeGen and intrinsics.
I did not change llvm.fma.f32/64 - it may be done later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157737 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 79bbe855cd3443bc646b2aedb2973c9968ca3b7f |
|
02-May-2012 |
Preston Gurd <preston.gurd@intel.com> |
Change the Intel Atom detection code to recognize
Lincroft and Medfield.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156025 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c80e7d2ea46589c5e42e09081a079392f6fbf041 |
|
01-May-2012 |
Craig Topper <craig.topper@gmail.com> |
Allow BMI, AES, F16C, POPCNT, FMA3, and CLMUL to be detected on AMD processors.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155899 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c573b1f7ae7ea3bf3757a383a46e9d4426de013e |
|
26-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
Trivial change to set UseLeaForSP flag in addition to toggling
the FeatureLeaForSP feature bit when llvm auto detects Intel Atom.
Patch by Andy Zhang
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 1203f2f138ec8298ffcf6c6138e56ce6b2413b4b |
|
26-Apr-2012 |
Craig Topper <craig.topper@gmail.com> |
Enable detection of AVX and AVX2 support through CPUID. Add AVX/AVX2 to corei7-avx, core-avx-i, and core-avx2 cpu names.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155618 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 6a8c7bf8e72338e55f0f9583e1828f62da165d4a |
|
23-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.
This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.
This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.
The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().
It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.
It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.
Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.
Patch by Andy Zhang!
Thanks to Jakob and Anton for their reviews.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155395 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f23293793aaf3a566fd000d734eb7217bb3db974 |
|
17-Apr-2012 |
Preston Gurd <preston.gurd@intel.com> |
Temporarily turn off anti-dependency checking
during Post RA scheduling in X86,
until the X86 target is changed to properly set up
post RA liveness.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154874 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 4e02f23de24375294005f88b5254a3775d39fcb2 |
|
27-Mar-2012 |
Craig Topper <craig.topper@gmail.com> |
Prune some includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 90f20044ade3712c8b0c3f4ebe47d57ad15ae6ce |
|
22-Feb-2012 |
Chad Rosier <mcrosier@apple.com> |
Remove extra semi-colons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| de1df103b9c578d0a1609054a5944342c5d0ba23 |
|
07-Feb-2012 |
Evan Cheng <evan.cheng@apple.com> |
Use LEA to adjust stack ptr for Atom. Patch by Andy Zhang.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 922d314e8f9f0d8e447c055485a2969ee9cf2dd2 |
|
02-Feb-2012 |
Andrew Trick <atrick@apple.com> |
Instruction scheduling itinerary for Intel Atom.
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT.
Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches.
Adds a test to verify that the scheduler is working.
Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP.
Patch by Preston Gurd!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 893a045cdbdc08fdaa5a62a24838be2df35cb628 |
|
31-Jan-2012 |
Evan Cheng <evan.cheng@apple.com> |
PR11834: Use macros which are defined on Windows. Patch by Marina Yatsina.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@149294 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 216f63702fabd57ac570feebc56005b2a5cb3216 |
|
10-Jan-2012 |
Joerg Sonnenberger <joerg@bec.de> |
Default stack alignment for 32bit x86 should be 4 Bytes, not 8 Bytes.
Add a test that checks the stack alignment of a simple function for
Darwin, Linux and NetBSD for 32bit and 64bit mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 16de4632bb263d7e0def43ebc13af5077726f067 |
|
09-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Remove AVX hack in X86Subtarget. AVX/AVX2 are now treated as an SSE level. Predicate functions have been altered to maintain previous names and behavior.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 39f227e4dd98d36ed852175825c3a74c05614bd6 |
|
09-Jan-2012 |
Craig Topper <craig.topper@gmail.com> |
Don't disable MMX support when AVX is enabled. Fix predicates for MMX instructions that were added along with SSE instructions to check for AVX in addition to SSE level.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 5ebee4494b8bcf8d1d969110dae5b5f971305367 |
|
29-Dec-2011 |
Craig Topper <craig.topper@gmail.com> |
Change XOP detection to use the correct CPUID bit instead of using the FMA4 bit.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@147348 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 8a8d479214745c82ef00f08d4e4f1c173b5f9ce2 |
|
02-Dec-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Move global variables in TargetMachine into new TargetOptions class. As an API
change, now you need a TargetOptions object to create a TargetMachine. Clang
patch to follow.
One small functionality change in PTX. PTX had commented out the machine
verifier parts in their copy of printAndVerify. That now calls the version in
LLVMTargetMachine. Users of PTX who need verification disabled should rely on
not passing the command-line flag to enable it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145714 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ce25d26b400d25c9e20ac9fe2d5b0cafb9d7fa15 |
|
02-Dec-2011 |
Jan Sjödin <jan_sjodin@yahoo.com> |
Add XOP feature flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| e7b05504faa86a5c0b80a62ddb60cbb0cf163d5d |
|
30-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add intrinsics and feature flag for read/write FS/GS base instructions. Also add AVX2 feature flag.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@143319 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 928698b14e4bcd0f231dc28e246920a242d81fc1 |
|
18-Oct-2011 |
David Meyer <pdox@google.com> |
Remove NaClMode
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 4b2dc74d3f17b40a57eba3068ce498a7f30769fe |
|
17-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Don't use inline assembly in 64-bit Visual Studio. Unfortunately, this means that cpuid leaf 7 can't be queried on versions of Visual Studio earlier than VS 2008 SP1. Fixes PR11147.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| b53fa8bf19a51f0c49a9f8b6ede3e2ff3bdfb961 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 BZHI instruction as well as BMI2 feature detection.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 4145c49aa0e0e70a51a395bdd4107a464d05e592 |
|
16-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 feature detection support for BMI instructions. Added new cpuid function for accessing leafs with sub leafs specified in ECX. Also added code to keep track of the max cpuid level supported in both basic and extended leaves and qualified the existing cpuid calls and the new call to leaf 7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@142089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 909652f6876a97d63db20606cd1b37e95d016caf |
|
14-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141939 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 37f2167f15608ff56d202ff21954a456aab6e534 |
|
11-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add X86 LZCNT instruction. Including instruction selection support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141651 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 1f104804bf30f1457e92fa6ee958a618a958b1ad |
|
10-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Put a bunch of calls to ToggleFeature behind proper if statements.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| da394041c409cb06008e60b9f9f845e845215b03 |
|
09-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 581fe82c84839f769a7275cf4cde7ea209f5ed04 |
|
03-Oct-2011 |
Craig Topper <craig.topper@gmail.com> |
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141007 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ca59221fdcb343ef45eb962bf72497bb1917d673 |
|
07-Sep-2011 |
Rafael Espindola <rafael.espindola@gmail.com> |
Detect attempt to use segmented stacks on non ELF systems and error
(not assert) early.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 1fac6b50ea720d75fc2bf01a288e99f239869e90 |
|
05-Sep-2011 |
Nick Lewycky <nicholas@mxc.ca> |
Add a new MC bit for NaCl (Native Client) mode. NaCl requires that certain
instructions are more aligned than the CPU requires, and adds some additional
directives, to follow in future patches. Patch by David Meyer!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139125 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 43f51aeca8367ea35adad963c00bd2bc5b8d1391 |
|
26-Aug-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@138660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c60f9b752381baa6c4b80c0739034660f1748c84 |
|
14-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Next round of MC refactoring. This patch factor MC table instantiations, MC
registeration and creation code into XXXMCDesc libraries.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@135184 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 59ee62d2418df8db499eca1ae17f5900dc2dcbba |
|
11-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
MCSubtargetInfo so MC code emitter can do the right thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 439d05d587b225d912ece9ce038ae298bc55e1c2 |
|
09-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Really force on 64bit for 64-bit targets. Should fix remaining failures on unknown x86/non-x86 targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134773 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 6dfef6605f788013099ea29e36e077015e2cfc23 |
|
09-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Revert earlier unnecessary hack. Make sure we correctly force on 64bit and cmov for 64-bit targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 4d1a8dde2d9eea508f66d51428b4f155fa6a6756 |
|
09-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Restore old behavior. Always auto-detect features unless cpu or features are specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134757 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f06ff4eae3ed2277555b25ee8e95b539f589b63c |
|
09-Jul-2011 |
Eli Friedman <eli.friedman@gmail.com> |
Default 64-bit target features and SSE2 on when a triple specifies x86-64. Clean up all the other hacks which are now unnecessary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134753 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| cc0ddc707d5a7b1dd11141881df0bf4210f8aeee |
|
08-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
For non-x86 host, used generic as CPU name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ebdeeab812beec0385b445f3d4c41a114e0d972f |
|
08-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Eliminate asm parser's dependency on TargetMachine:
- Each target asm parser now creates its own MCSubtatgetInfo (if needed).
- Changed AssemblerPredicate to take subtarget features which tablegen uses
to generate asm matcher subtarget feature queries. e.g.
"ModeThumb,FeatureThumb2" is translated to
"(Bits & ModeThumb) != 0 && (Bits & FeatureThumb2) != 0".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134678 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 18fb1d35db9e2160be3a5bd2950f7e0d206bdbb8 |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Add Mode64Bit feature and sink it down to MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134641 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 0ddff1b5359433faf2eb1c4ff5320ddcbd42f52f |
|
07-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Compute feature bits at time of MCSubtargetInfo initialization.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 385e930d55f3ecd3c9538823dfa5896a12461845 |
|
02-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename XXXGenSubtarget.inc to XXXGenSubtargetInfo.inc for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 5b1b4489cf3a0f56f8be0673fc5cc380a32d277b |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
Rename TargetSubtarget to TargetSubtargetInfo for consistency.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134259 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 94214703d97d8d9dfca88174ffc7e94820a85e62 |
|
01-Jul-2011 |
Evan Cheng <evan.cheng@apple.com> |
- Added MCSubtargetInfo to capture subtarget features and scheduling
itineraries.
- Refactor TargetSubtarget to be based on MCSubtargetInfo.
- Change tablegen generated subtarget info to initialize MCSubtargetInfo
and hide more details from targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134257 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 276365dd4bc0c2160f91fd8062ae1fc90c86c324 |
|
30-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name to
be the first encoded as the first feature. It then uses the CPU name to look up
features / scheduling itineray even though clients know full well the CPU name
being used to query these properties.
The fix is to just have the clients explictly pass the CPU name!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ef41ff618f2537539b538e6c7bf471c753391f92 |
|
23-Jun-2011 |
Evan Cheng <evan.cheng@apple.com> |
Remove TargetOptions.h dependency from X86Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133726 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| fee22869ca8fc1b703f06eeb2e530345032fb2f3 |
|
17-May-2011 |
Mon P Wang <wangmp@apple.com> |
Enable autodetect of popcnt
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 558692fd0a31d4d3ae4fd09a3a02f80da2e44e5c |
|
20-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
ADT/Triple: Renambe isOSX... methods to isMacOSX for consistency with the OS
triple component.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 2cf711f1e69dc1d00d57814478c8eb12d97ce3a8 |
|
19-Apr-2011 |
Daniel Dunbar <daniel@zuster.org> |
Target/X86: Eliminate uses of getDarwinVers().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129813 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 4c3ab58c4766bb48526523b000fa54186c97877e |
|
22-Feb-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Stack alignment is 16 bytes on FreeBSD/i386 too.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126226 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 7331ca853af405460960d7cc07f48fd01fb58acf |
|
21-Feb-2011 |
Duncan Sands <baldrick@free.fr> |
The stack should be 16 byte aligned on 32 bit solaris. Patch by Yuri.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126130 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 04f5079ca1fd6c46a2b2efc369e293fb6feab793 |
|
13-Jan-2011 |
Eric Christopher <echristo@apple.com> |
Experiment with changing the default 32-bit linux stack alignment to
16 bytes for PR8969. Update all testcases accordingly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| de7f92083569dd5dde89a7fd75cd1a4c8b5b9794 |
|
13-Dec-2010 |
Evan Cheng <evan.cheng@apple.com> |
Disable auto-detection of AVX support since AVX codegen support is not ready.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121677 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 2ea8ee7c76b8d8754d81072e691caf25d23289e3 |
|
10-Dec-2010 |
Nate Begeman <natebegeman@mac.com> |
Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@121439 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| d643486058dcece4d35f4855e8d39e6f85b24cbe |
|
05-Dec-2010 |
Bill Wendling <isanbard@gmail.com> |
Initialize HasPOPCNT.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120923 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 1f6efa3996dd1929fbc129203ce5009b620e6969 |
|
29-Nov-2010 |
Michael J. Spencer <bigcheesegs@gmail.com> |
Merge System into Support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120298 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 699647cabcd98efd10b3bfb7cedc4d4b54f9b93d |
|
21-Aug-2010 |
Anton Korobeynikov <asl@math.spbu.ru> |
Use rip-rel addressing on win64 by default. For this we just
defaults to small pic code model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111741 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| cdae7e8244e37f539a5f1c9b780de7817b40de52 |
|
23-Jul-2010 |
Bruno Cardoso Lopes <bruno.cardoso@gmail.com> |
Add x86 CLMUL (Carry-less multiplication) cpu feature
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109206 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 62f35a2c133cd7de818dfc366a393282f01b111c |
|
05-Jul-2010 |
Eric Christopher <echristo@apple.com> |
Have the X86 backend use Triple instead of a string and some enums.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 6b601536ff1f5d18f738a322a331ed5fdc89e46a |
|
14-Jun-2010 |
Chris Lattner <sabre@nondot.org> |
fix a nasty bug where we were not treating available_externally
symbols as declarations in the X86 backend. This would manifest
on darwin x86-32 as errors like this with -fvisibility=hidden:
symbol '__ZNSbIcED1Ev' can not be undefined in a subtraction expression
This fixes PR7353.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105954 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 4d3d6e1a0c99e2212953a90185a8d027c595bf5a |
|
27-May-2010 |
Dan Gohman <gohman@apple.com> |
FastISel doesn't yet handle callee-pop functions.
To support this, move IsCalleePop from X86ISelLowering to X86Subtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@104866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 2bce5f4b56ac0ea8e452a79e13abba1deca9b7b6 |
|
28-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Enable i16 to i32 promotion by default.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@102493 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 5528e7bcb1209094a68bbf6d1efeefc3ca34774f |
|
21-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
isel (i32 anyext i16) as insert_subreg when 16-bit ops are being promoted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101979 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 6d1cd1cd04abb1828a14980e15252985c8c728b2 |
|
02-Apr-2010 |
Eric Christopher <echristo@apple.com> |
Separate out the AES-NI instructions from the SSE4.2 instructions. Add
a new subtarget option for AES and check for the support. Add "westmere"
line of processors and add AES-NI support to the core i7.
Add a couple of TODOs for information I couldn't verify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 48c58bb8610cd475d1acb073694e0d2b4dd7cc8c |
|
01-Apr-2010 |
Evan Cheng <evan.cheng@apple.com> |
Nehalem unaligned memory access is fast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@100089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| bdc652bab899d86f2181ed30caf689e43237ffb3 |
|
18-Mar-2010 |
Evan Cheng <evan.cheng@apple.com> |
Turning off post-ra scheduling for x86. It isn't a consistent win.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98810 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 1c436d0b0b6f2b843916a11dd57e7fa3fab5795b |
|
14-Mar-2010 |
Chris Lattner <sabre@nondot.org> |
no really, all 64-bit cpu's have cmov support. This should
fix the rest of the buildbot failures on non-x86 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@98522 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f0356fe140af1a30587b9a86bcfb1b2c51b8ce20 |
|
27-Jan-2010 |
Jeffrey Yasskin <jyasskin@google.com> |
Kill ModuleProvider and ghost linkage by inverting the relationship between
Modules and ModuleProviders. Because the "ModuleProvider" simply materializes
GlobalValues now, and doesn't provide modules, it's renamed to
"GVMaterializer". Code that used to need a ModuleProvider to materialize
Functions can now materialize the Functions directly. Functions no longer use a
magic linkage to record that they're materializable; they simply ask the
GVMaterializer.
Because the C ABI must never change, we can't remove LLVMModuleProviderRef or
the functions that refer to it. Instead, because Module now exposes the same
functionality ModuleProvider used to, we store a Module* in any
LLVMModuleProviderRef and translate in the wrapper methods. The bindings to
other languages still use the ModuleProvider concept. It would probably be
worth some time to update them to follow the C++ more closely, but I don't
intend to do it.
Fixes http://llvm.org/PR5737 and http://llvm.org/PR5735.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@94686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 95eb2eeea65fbae223ffd517f3984f14b034fcb8 |
|
11-Jan-2010 |
David Greene <greened@obbligato.org> |
Implement a feature (-vector-unaligned-mem) to allow targets to
ignore alignment requirements for SIMD memory operands. This
is useful on architectures like the AMD 10h that do not trap on
unaligned references if a status bit is twiddled at startup time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93151 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| bd7b8458d1a3af49a7faeeb52f3ed71eea08f70c |
|
05-Jan-2010 |
David Greene <greened@obbligato.org> |
Change errs() to dbgs().
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@92648 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| b1f49813334278094b1ecd7ad920f5c276f7b3e6 |
|
22-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 400073d5467b79534d8c63b0d996a55e4252ff4b |
|
18-Dec-2009 |
Evan Cheng <evan.cheng@apple.com> |
On recent Intel u-arch's, folding loads into some unary SSE instructions can
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.
movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0
instead of
cvtss2sd (%rdi), %xmm0
An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| d84ea47b896cbe6072a344118853ae22e937a04f |
|
07-Dec-2009 |
Dan Gohman <gohman@apple.com> |
Don't enable the post-RA scheduler on x86 except at -O3. In its
current form, it is too expensive in compile time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@90781 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 29cbade25aa094ca9a149a96a8614cf6f3247480 |
|
21-Nov-2009 |
Dan Gohman <gohman@apple.com> |
Target-independent support for TargetFlags on BlockAddress operands,
and support for blockaddresses in x86-32 PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@89506 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 067d024b05e56d2847608c9149a7151d6531c036 |
|
14-Nov-2009 |
Daniel Dunbar <daniel@zuster.org> |
Add llvm::sys::getHostCPUName, for detecting the LLVM name for the host CPU.
- This is an initial step towards -march=native support in Clang, and towards
eliminating host dependencies in the targets. See PR5389.
- Patch by Roman Divacky!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88768 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 87d21b92fc42f6b3bd8567a83fc5b5191c1205e5 |
|
13-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Allow target to specify regclass for which antideps will only be broken along the critical path.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@88682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c2e8a7e8d2ab156afaa8ab0d0317dd9ee3db7d30 |
|
10-Nov-2009 |
David Goodwin <david_goodwin@apple.com> |
Fixed to address code review. No functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 79f7400e4f98929571431f4e8c21f6ef52c63f6b |
|
15-Oct-2009 |
Evan Cheng <evan.cheng@apple.com> |
Remove X86Subtarget::IsLinux. It's no longer being used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84200 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 63476a80404125e5196b6c09113c1d4796da0604 |
|
03-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80904 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 848113833fc51bdd170cdce17abe7783ca52a34a |
|
03-Sep-2009 |
Daniel Dunbar <daniel@zuster.org> |
Make these functions static and local.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80892 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| d0da6ff3ad761dc5eb00cbe32b850de7b0bf27b6 |
|
03-Sep-2009 |
Evan Cheng <evan.cheng@apple.com> |
X86JITInfo::getLazyResolverFunction() should not read cpu id to determine whether sse is available. Just use consult subtarget.
No functionality changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80880 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 700841617a9cfdc08323449ab14f42513c106430 |
|
02-Sep-2009 |
Chris Lattner <sabre@nondot.org> |
Add support for modeling whether or not the processor has support for
conditional moves as a subtarget feature. This is the easy part of
PR4841.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 6f9bb6f31b37380fa9c4412b400b53eba65b7410 |
|
28-Aug-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
Short-term workaround for frame-related weirdness on win64.
Some other minor win64 fixes as well.
Patch by Michael Beck!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80370 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ce914b8f945bdd42126991a7fda8984681c2c067 |
|
12-Aug-2009 |
Chris Lattner <sabre@nondot.org> |
change the -x86-asm-syntax=intel/att flag to be in X86TAI
instead of X86 Subtarget. This elimianates dependencies on
X86Subtarget from X86TAI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| e22f4da01d57f51757663fdcae986af0aeca49fe |
|
05-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Remove some dead code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 0ea8bf3590d7553179f95e4b0fc47c02f066fcfb |
|
03-Aug-2009 |
Bill Wendling <isanbard@gmail.com> |
- s/DOUT/DEBUG(errs()/g
- Tidy up some headers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 3be03406c9c3b2075d5ae416499af2f15f703d6f |
|
03-Aug-2009 |
Daniel Dunbar <daniel@zuster.org> |
Normalize Subtarget constructors to take a target triple string instead of
Module*.
Also, dropped uses of TargetMachine where unnecessary. The only target which
still takes a TargetMachine& is Mips, I would appreciate it if someone would
normalize this to match other targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77918 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| cfb8a1bea15f50e6609283c0e06f815a1448a14b |
|
19-Jul-2009 |
Daniel Dunbar <daniel@zuster.org> |
Fix some minor MSVC compiler warnings.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| a82b22c667f66224edaf83f33815c8015fb74444 |
|
17-Jul-2009 |
Evan Cheng <evan.cheng@apple.com> |
GV with ghost linkage (module being lazily streamed in in JIT lazy compilation mode) do not require extra load from stub. This fixes ExecutionEngine/2005-12-02-TailCallBug.ll.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c7822326df54ad766996875851f0796c14268c13 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
fix indentation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75277 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| e2c920845a407957b8ae2600feae1f4c85a0d4d0 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
remove the now-dead TM argument to these methods.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 8097b65c432c3cc39339b6bb0ead9e1e09232ff7 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
make PIC vs DynamicNoPIC be explicit in PICStyles.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75275 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 84853a17a3f79f37277f6b67ac9f5468ea6d8438 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
some minor simplifications.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 3b67e9ba015624a9904a41d6d0fd61cac1b02055 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
add a couple of predicates to test for "stub style pic in PIC mode" and "stub style pic in dynamic-no-pic" mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 0d786dd954622b8e7981eee32e9d585ee067d9c5 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
simplify fast isel by using ClassifyGlobalReference. This
elimiantes the last use of GVRequiresExtraLoad, so delete it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75244 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| dfed413ef6bfb05754ee5a9f3a3c7f98c764a374 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
eliminate GVRequiresRegister, replacing it with predicates we
need for other purposes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75243 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| d392bd97c8203ab4a770dfdd0a5565ac6cd6cacd |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
move some classification logic around. Now GVRequiresExtraLoad
is just a trivial wrapper around "ClassifyGlobalReference", which
stole a ton of logic from LowerGlobalAddress.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ed0dca6a5dfa26e63c5636eb092640159182df89 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
GVRequiresExtraLoad is now never used for calls, simplify it based on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75232 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 754b7650c20a0fa3a9df3f067dc02a0905992325 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
actually, just eliminate PCRelGVRequiresExtraLoad. It makes the code
more complex and slow than just directly testing what we care about.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| e6c07b52e76b19d83338901b2e103bd8cbabd42f |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
There is only one case where GVRequiresExtraLoad returns true for calls:
split its handling out to PCRelGVRequiresExtraLoad, and simplify code
based on this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75230 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 04b304caf633a471946c59c7d313e1560c5d07a5 |
|
10-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
the "isDirectCall" operand of GVRequiresRegister is always false, eliminate it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75229 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 15a380a03567deba90c074a2cd5a45b81ae0958b |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
simplify some code based on the fact that picstyles != none are only valid
in pic or dynamic-no-pic mode. Also, x86-64 never used picstylegot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75101 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 73b5b71369d7324dd87e89791edb7000b1d0bd29 |
|
09-Jul-2009 |
Chris Lattner <sabre@nondot.org> |
Reduce indentation in GVRequiresExtraLoad. Return true for windows
with DLLImport symbols even when in -static mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75093 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 343dadbb368ec4de546c2cc3ffb1dac4cdbe14b9 |
|
27-Jun-2009 |
David Greene <greened@obbligato.org> |
Add feature flags for AVX and FMA and fix some SSE4A feature flag
initialization problems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74350 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 0eebf653a7b2978e7761f8d068b6fbec22aea0f6 |
|
09-Jun-2009 |
Anton Korobeynikov <asl@math.spbu.ru> |
The attached patches implement most of the ARM AAPCS-VFP hard float
ABI. The missing piece is support for putting "homogeneous aggregates"
into registers.
Patch by Sandeep Patel!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@73095 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 8cf5ab153d3873d8565d5433527bd0219f7b8043 |
|
26-May-2009 |
Stefanus Du Toit <stefanus.dutoit@rapidmind.com> |
Update CPU capabilities for AMD machines
- added processors k8-sse3, opteron-sse3, athlon64-sse3, amdfam10, and
barcelona with appropriate sse3/4a levels
- added FeatureSSE4A for amdfam10 processors
in X86Subtarget:
- added hasSSE4A
- updated AutoDetectSubtargetFeatures to detect SSE4A
- updated GetCurrentX86CPU to detect family 15 with sse3 as k8-sse3 and
family 10h as amdfam10
New processor names match those used by gcc.
Patch by Paul Redmond!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72434 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| d7f666a869966a22b0b8f9fcd5056c1d475039cc |
|
20-May-2009 |
Evan Cheng <evan.cheng@apple.com> |
Try again. Allow call to immediate address for ELF or when in static relocation mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72160 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| bc58322d6a15fc06207a9e0c01786aa140fe9a29 |
|
25-Apr-2009 |
Chris Lattner <sabre@nondot.org> |
add support for detecting process features on win64, patch by
Nicolas Capens!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70057 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 667d4b8de6dea70195ff12ef39a4deebffa2f5c7 |
|
07-Mar-2009 |
Duncan Sands <baldrick@free.fr> |
Introduce new linkage types linkonce_odr, weak_odr, common_odr
and extern_weak_odr. These are the same as the non-odr versions,
except that they indicate that the global will only be overridden
by an *equivalent* global. In C, a function with weak linkage can
be overridden by a function which behaves completely differently.
This means that IP passes have to skip weak functions, since any
deductions made from the function definition might be wrong, since
the definition could be replaced by something completely different
at link time. This is not allowed in C++, thanks to the ODR
(One-Definition-Rule): if a function is replaced by another at
link-time, then the new function must be the same as the original
function. If a language knows that a function or other global can
only be overridden by an equivalent global, it can give it the
weak_odr linkage type, and the optimizers will understand that it
is alright to make deductions based on the function body. The
code generators on the other hand map weak and weak_odr linkage
to the same thing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@66339 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 9feb5dd5685d8d52f40f2d88a1125bff8d67adfe |
|
28-Feb-2009 |
Mon P Wang <wangmp@apple.com> |
Added another darwin subtarget
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@65662 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 605679f0cdbfae59374dbb28de4ab3eee27804f2 |
|
03-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Tevert part of the x86 subtarget logic changes: when -march=x86-64
is given, override the subtarget settings and enable 64-bit support.
This restores the earlier behavior, and fixes regressions on
Non-64-bit-capable x86-32 hosts.
This isn't necessarily the best approach, but the most obvious
alternative is to require -mcpu=x86-64 or -mattr=+64bit to be used
with -march=x86-64 when the host doesn't have 64-bit support. This
makes things little more consistent, but it's less convenient, and
it has the practical drawback of requiring lots of test changes, so
I opted for the above approach for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63642 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f75e5b4d8cbbec83924a3186a167a03564e5c373 |
|
03-Feb-2009 |
Dan Gohman <gohman@apple.com> |
Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has
SSE2, however it's possible to disable SSE2, and the subtarget support
code thinks that if 64-bit implies SSE2 and SSE2 is disabled then
64-bit should also be disabled. Instead, just mark all the 64-bit
subtargets as explicitly supporting SSE2.
Also, move the code that makes -march=x86-64 enable 64-bit support by
default to only apply when there is no explicit subtarget. If you
need to specify a subtarget and you want 64-bit code, you'll need to
select a subtarget that supports 64-bit code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63575 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| b68a88bd48c0fcee7bba2d01a3e3602e98aa27e7 |
|
02-Feb-2009 |
Torok Edwin <edwintorok@gmail.com> |
Only force SSE level if it is not correct.
Add an assert to check HasX86_64 status.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 38870ed13c17ec8169b2c64f77dcf54186dcd8a1 |
|
02-Feb-2009 |
Torok Edwin <edwintorok@gmail.com> |
remove #if 0 code on Bill's request.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63542 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 3f142c36ad04c1aabac90df6a866bd2b0767f24f |
|
01-Feb-2009 |
Torok Edwin <edwintorok@gmail.com> |
Implement -mno-sse: if SSE is disabled on x86-64, don't store XMM on stack for
var-args, and don't allow FP return values
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63495 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| afb564c6977c70087862723374d1da45e3777153 |
|
25-Jan-2009 |
Torok Edwin <edwintorok@gmail.com> |
should have removed the + when manually applying a patch!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c8ad2d2abf4ef988d7dffb687cd3366cb02c49ff |
|
25-Jan-2009 |
Torok Edwin <edwintorok@gmail.com> |
revert this patch for now, because Codegen does still want to generate SSE code,
for example in the case of va-args. XFAIL associated tests.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 7f1d5252c719ec57a9cba08256770e8b71ba624a |
|
25-Jan-2009 |
Torok Edwin <edwintorok@gmail.com> |
If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62967 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| bb46f52027416598a662dc1c58f48d9d56b1a65b |
|
15-Jan-2009 |
Rafael Espindola <rafael.espindola@gmail.com> |
Add the private linkage.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62279 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 7877112775b97d13e225124d6f1181c30d75853a |
|
05-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Atom and Core i7 do not have same model number after all.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61686 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 0be6d3fb2a3f502c3dd750961c8c571f03727331 |
|
03-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Add Intel processors core i7 and atom.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61603 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 5b925c031dab6e6b79e9de281fdb177ac69cbd1c |
|
03-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix PR3210: Detect more Intel processors. Patch by Torok Edwin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61602 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ccb6976a69a6e146db049fff8e6338e31c91b6f8 |
|
02-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Do not isel load folding bt instructions for pentium m, core, core2, and AMD processors. These are significantly slower than a load followed by a bt of a register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61557 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 018b7ee91a1dc8e1f87ea8c9133b5e44d9e57972 |
|
02-Jan-2009 |
Evan Cheng <evan.cheng@apple.com> |
Fix x86 CPU id detection to identify Penryn (and future processors).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 8749b61178228ba1fb2668034d79da1b247173d7 |
|
16-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add initial support for back-scheduling address computations,
especially in the case of addresses computed from loop induction
variables.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61075 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| e4d1082b2c63919f3abb6de18ce47ce9e05cfdea |
|
08-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Re-apply 60689 now my head is screwed on right.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 2d4e9bc922001000db1141da3bdc6541a586271a |
|
08-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Revert 60689. It caused many regressions on Darwin targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60705 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| dda346aa717f12e9e99587d66c825429760a4e1d |
|
08-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Perform cheap checks first.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60689 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 203af58aea3ae341d38e5c2c5b390b0c31d25557 |
|
05-Dec-2008 |
Dale Johannesen <dalej@apple.com> |
Make LoopStrengthReduce smarter about hoisting things out of
loops when they can be subsumed into addressing modes.
Change X86 addressing mode check to realize that
some PIC references need an extra register.
(I believe this is correct for Linux, if not, I'm sure
someone will tell me.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60608 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ae94e594164b193236002516970aeec4c4574768 |
|
05-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Re-did 60519. It turns out Darwin's handling of hidden visibility symbols are a bit more complicate than I expected. Both declarations and weak definitions still need a stub indirection. However, the stubs are in data section and they contain the addresses of the actual symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60571 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| a8103dad4e84e031c5845e18268655cc0bfbdb8d |
|
04-Dec-2008 |
Bill Wendling <isanbard@gmail.com> |
Temporarily revert r60519. It was causing a bootstrap failure:
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT barrier.lo -MD -MP -MF .deps/barrier.Tpo -c ../../../llvm-gcc.src/libgomp/barrier.c -fno-common -DPIC -o .libs/barrier.o
checking for sys/file.h... /var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:non-relocatable subtraction expression, "_gomp_tls_key" minus "L1$pb"
/var/folders/zG/zGE-ZJOGFiGjv0B5cs5oYE+++TM/-Tmp-//cc34Jg5P.s:13:symbol: "_gomp_tls_key" can't be undefined in a subtraction expression
make[4]: *** [barrier.lo] Error 1
make[4]: *** Waiting for unfinished jobs....
/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/xgcc -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.obj/./gcc/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/bin/ -B/Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/lib/ -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/include -isystem /Volumes/Sandbox/Buildbot/llvm/full-llvm/build/llvm-gcc.install/i386-apple-darwin9.5.0/sys-include -DHAVE_CONFIG_H -I. -I../../../llvm-gcc.src/libgomp -I. -I../../../llvm-gcc.src/libgomp/config/posix -I../../../llvm-gcc.src/libgomp -Wall -pthread -Werror -O2 -g -O2 -MT alloc.lo -MD -MP -MF .deps/alloc.Tpo -c ../../../llvm-gcc.src/libgomp/alloc.c -o alloc.o >/dev/null 2>&1
yes
checking for sys/param.h... make[3]: *** [all-recursive] Error 1
make[2]: *** [all] Error 2
make[1]: *** [all-target-libgomp] Error 2
make[1]: *** Waiting for unfinished jobs....
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60527 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| eb83dfde66b4614fe48a572ea2ee1d7b91bcbc19 |
|
04-Dec-2008 |
Evan Cheng <evan.cheng@apple.com> |
Visibility hidden GVs do not require extra load of symbol address from the GOT or non-lazy-ptr.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60519 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f9a67a894366482cb2aa70a0e4dfeb5d76f91988 |
|
28-Nov-2008 |
Duncan Sands <baldrick@free.fr> |
Fix build with gcc-4.4: it doesn't like PICStyle
being both a namespace and a variable name.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60208 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| b8cab9227a0f6ffbdaae33e3c64268e265008a6a |
|
14-Oct-2008 |
Dan Gohman <gohman@apple.com> |
Fix command-line option printing to print two spaces where needed,
instead of requiring all "short description" strings to begin with
two spaces. This makes these strings less mysterious, and it fixes
some cases where short description strings mistakenly did not
begin with two spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@57521 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 6e08738d4b1bb6c087d81bca656c24cdc1d504f8 |
|
01-Oct-2008 |
Bill Wendling <isanbard@gmail.com> |
Just don't transform this memset into "bzero" if no-builtin is specified.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56888 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 6f287b22d2e57600b4cd5dc209d0d869e7736c0b |
|
30-Sep-2008 |
Bill Wendling <isanbard@gmail.com> |
Add the new `-no-builtin' flag. This flag is meant to mimic the GCC
`-fno-builtin' flag. Currently, it's used to replace "memset" with "_bzero"
instead of "__bzero" on Darwin10+. This arguably violates the meaning of this
flag, but is currently sufficient. The meaning of this flag should become more
specific over time.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 817a6a9eaa96a82c821143f13c756d7fa76cea71 |
|
16-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
x86-64 PIC JIT fixes: do not generate the extra load for external GV's.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53661 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 3b48591a84d4dd16309454783a0676952b698827 |
|
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Revert accidentially added stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53321 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| e87f52d722d4184becb2ecaf4500dd01d176bfc2 |
|
09-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Switch to new section name handling facility
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53316 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| cb2627395d995e7727711c3319303183cb741ef3 |
|
03-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Back out 53091 for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53109 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f550f472ee0a9717f70c78ac422c04e252dbeec9 |
|
03-Jul-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
llvm-gcc sometimes marks external declarations hidden, because intializers are
processed separately. Honour such situation and emit PIC relocations properly
in such case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| da5860fa8b8ad7f8622fc096a55d68a140c7c3ac |
|
02-Jun-2008 |
Rafael Espindola <rafael.espindola@gmail.com> |
Don't use the GOT for symbols that are not externally visible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51865 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| aafce77b17d340aace52bcd49d1944109d82f14a |
|
14-May-2008 |
Dale Johannesen <dalej@apple.com> |
Add CommonLinkage; currently tentative definitions
are represented as "weak", but there are subtle differences
in some cases on Darwin, so we need both. The intent
is that "common" will behave identically to "weak" unless
somebody changes their target to do something else.
No functional change as yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 844731a7f1909f55935e3514c9e713a62d67662e |
|
13-May-2008 |
Dan Gohman <gohman@apple.com> |
Clean up the use of static and anonymous namespaces. This turned up
several things that were neither in an anonymous namespace nor static
but not intended to be global.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@51017 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 63307c335aa08b0d6a75f81d64d79af7e90eb78b |
|
05-May-2008 |
Mon P Wang <wangmp@apple.com> |
Added addition atomic instrinsics and, or, xor, min, and max.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 94bbdc8c254e259eff22eb5d6a1012fc1438fb45 |
|
05-May-2008 |
Dan Gohman <gohman@apple.com> |
Fix IsLinux being uninitialized on non-Linux targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50660 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 600bf16cf7b1667f85c8531432aae0dd23d553ab |
|
05-May-2008 |
Dan Gohman <gohman@apple.com> |
Use a dedicated IsLinux flag instead of an ELFLinux TargetType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50649 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| a779a9899a5e23bd5198973f4709d66cb4bc2e64 |
|
05-May-2008 |
Dan Gohman <gohman@apple.com> |
Add AsmPrinter support for emitting a directive to declare that
the code being generated does not require an executable stack.
Also, add target-specific code to make use of this on Linux
on x86.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 45709ae09b252a18efd342bbd56574a12437c81c |
|
23-Apr-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Make stack alignment options global for all targets
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50157 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 890fe888be0e19ce675bb2cd7c127ece88d8064d |
|
23-Apr-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide ABI-correct stack alignment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50154 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| dc00858e11d243bd2c7cb39bbb92c557b123573e |
|
16-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
Initialize X863DNowLevel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49808 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 78c80fdbdd7a0db3cd5c84f60ddc95e72702fe2e |
|
13-Apr-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Provide option for stack alignment override
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49593 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 68d599df37218452acd5a680d5360d3caaa1623c |
|
01-Apr-2008 |
Dan Gohman <gohman@apple.com> |
Speculatively micro-optimize memory-zeroing calls on Darwin 10.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 2b4f7805851912d05b5bd5ef9b8a9afee1c60e39 |
|
22-Mar-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Honour built-in defines on win64 targets for automatically subtarget recognize.
Force stack alignment to 16 bytes on win targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48695 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 508f0fdb534e23d453ecc4d4892d581bb9647c50 |
|
22-Mar-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Recognize "windows" in target triple, not only "win32"
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48694 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 7c1c261272b43f2a9397c3052819b92c53918075 |
|
20-Feb-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Remove bunch of gcc 4.3-related warnings from Target
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47369 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ab1a0354ecff51d27098d6f11fbeabc65dec7123 |
|
15-Feb-2008 |
Dale Johannesen <dalej@apple.com> |
Remove warning about 64-bit code on processor
that doesn't support it. Per Chris.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47162 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| be3bf423315394f15f0c71afdaed26e5cfbcad4a |
|
07-Feb-2008 |
Evan Cheng <evan.cheng@apple.com> |
Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.
Before:
_main:
subq $8, %rsp
leaq _X(%rip), %rax
movsd 8(%rax), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Now:
_main:
subq $8, %rsp
movsd _X+8(%rip), %xmm1
movss _X(%rip), %xmm0
call _t
xorl %ecx, %ecx
movl %ecx, %eax
addq $8, %rsp
ret
Notice there is another idiotic codegen issue that needs to be fixed asap:
xorl %ecx, %ecx
movl %ecx, %eax
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46850 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 63ec90a6a8e0e441a1560f4386c5b6d538ad6583 |
|
03-Feb-2008 |
Nate Begeman <natebegeman@mac.com> |
SSE 4.1 Intrinsics and detection
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46681 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 49964d6847291900992b7fc75cb88a395f468817 |
|
20-Jan-2008 |
Anton Korobeynikov <asl@math.spbu.ru> |
Enable PIC codegen on x86-64/linux
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46198 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| e51775dc5e3503092313fe77174127f4f4d17374 |
|
08-Jan-2008 |
Duncan Sands <baldrick@free.fr> |
Use size_t to store Pos, avoid truncating value
on 64-bit builds. Analysis and original patch
by Török Edwin. Code audit found another place
with the same problem, also fixed here.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 7ad92d81e2c2d1fe8ae89e5638fc57925d747429 |
|
02-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
darwin9 and above support aligned common symbols.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45494 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| fc05f402ea22e8a9ae465d209b65be7e857a89ff |
|
31-Oct-2007 |
Rafael Espindola <rafael.espindola@gmail.com> |
Make ARM an X86 memcpy expansion more similar to each other.
Now both subtarget define getMaxInlineSizeThreshold and the expansion uses it.
This should not change generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f6844ca0e4a02fae3b100db7b0c62170d05e5b53 |
|
02-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Mac OS X X86-64 low 4G address not available.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| a99be51bf5cdac1438069d4b01766c47704961c8 |
|
05-Jul-2007 |
Gabor Greif <ggreif@gmail.com> |
Here is the bulk of the sanitizing.
Almost all occurrences of "bytecode" in the sources have been eliminated.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37913 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c3987095259e2c80f0bb015e61b2b766db63b33f |
|
16-Apr-2007 |
Jeff Cohen <jeffc@jolt-lang.org> |
In the event that some really old non-Intel or -AMD CPU is encountered...
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 22114c319a58074cc5d0ad60d09e0020db89f127 |
|
16-Apr-2007 |
Jeff Cohen <jeffc@jolt-lang.org> |
Before assuming that the original code didn't work for Athlon64, the person who
replaced it with a FIXME should have determined what did work. Then he would have
realized that the code was in fact correct, and would have avoided breaking it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@36173 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| bb1ee05253d965e0944351a21e9970c02b1aebfe |
|
11-Apr-2007 |
Bill Wendling <isanbard@gmail.com> |
Add support for our first SSSE3 instruction "pmulhrsw".
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35869 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 3b5ee73a13f3b6c70b8d14827da3ee72260fc963 |
|
24-Mar-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Autodetect MMX & SSE stuff for AMD processors
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35292 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 5cbf985dcbc89fba3208e7baf8b6f488b06d3ec9 |
|
30-Jan-2007 |
Reid Spencer <rspencer@reidspencer.com> |
For PR1136: Rename GlobalVariable::isExternal as isDeclaration to avoid
confusion with external linkage types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33663 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| b10308e440c80dd6ffb4b478f741ff7e5f30cb48 |
|
28-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.
NOTEs: 1. Documentation will be updated soon.
2. llvm-upgrade should be improved to translate csret => sret.
Before this, there will be some unexpected test fails.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33597 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 706535db86868d710ad10ddad4adc4bc8b838f10 |
|
22-Jan-2007 |
Evan Cheng <evan.cheng@apple.com> |
Linux GOT indirect reference is only necessary in PIC mode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33441 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 5032e5a61381437174e035de2a7dd728978f7bd5 |
|
17-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
* Fix one more bug in PIC codegen: extra load is needed for *all*
non-statics.
* Introduce new option to output zero-initialized data to .bss section.
This can reduce size of binaries. Enable it by default for ELF &
Cygwin/Mingw targets. Probably, Darwin should be also added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33299 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 7f70559bc47877bafc6dfa92b7df6b64650445fb |
|
12-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
* PIC codegen for X86/Linux has been implemented
* PIC-aware internal structures in X86 Codegen have been refactored
* Visibility (default/weak) has been added
* Docs fixes (external weak linkage, visibility, formatting)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33136 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 317848f4a11f7fe55afdd6d90ded8444069b56fb |
|
03-Jan-2007 |
Anton Korobeynikov <asl@math.spbu.ru> |
Really big cleanup.
- New target type "mingw" was introduced
- Same things for both mingw & cygwin are marked as "cygming" (as in
gcc)
- .lcomm is supported here, so allow LLVM to use it
- Correctly use underscored versions of setjmp & _longjmp for both mingw
& cygwin
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 2b2bc688849234b9ee5e0c8704a2984f0e9cbba3 |
|
22-Dec-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Refactored JIT codegen for mingw32. Now we're using standart relocation
type for distinguish JIT & non-JIT instead of "dirty" hacks :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32745 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 48c8e3de2ff1a6734a8207eb8422e0ee7ef79077 |
|
20-Dec-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fixed 80 cols & style violation
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32720 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 15fccf1d9395ccf3f60404e71dc9db029d04f910 |
|
20-Dec-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Fixed dllimported symbols support during JIT'ing. JIT on mingw32
platform should be more or less workable. At least, sim is running fine
under lli :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8 |
|
07-Dec-2006 |
Bill Wendling <isanbard@gmail.com> |
What should be the last unnecessary <iostream>s in the library.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32333 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 7784ebc239202bba4859855c3f438319144535f0 |
|
30-Nov-2006 |
Anton Korobeynikov <asl@math.spbu.ru> |
Factor out GVRequiresExtraLoad() from .h to .cpp
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32048 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| b4809b2b8f017fd6343aaf64f6417dd3396aecb9 |
|
29-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
16-byte stack alignment for X86-64 ELF. Patch by Dan Gohman.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 3b6f4978735ff529e59f77423fd9f8a21ca77a8d |
|
20-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Fix codegen for x86-64 on systems (like ppc or i386) that don't have 64-bit
features autodetected. This fixes PR1010 and Regression/CodeGen/X86/xmm-r64.ll
on non-x86-64 hosts.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| aacf99964f6f37d566f9fda5160b3826f3ce2da4 |
|
08-Nov-2006 |
Evan Cheng <evan.cheng@apple.com> |
Use movl+xchgl instead of pushl+popl.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31572 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| f896d1e24757fccbbd5173913a6f035c1a54fdeb |
|
17-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Proper fix.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30993 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 751c0e12dbabe90c98f1f050baea714e79c837d6 |
|
16-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Proper fix for rdar://problem/4770604 Thanks to Stuart Hastings!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30985 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 3cff9f8947fe4792f3266aa9b7f8de8f039bd34a |
|
06-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
80 col violation.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| a26eb5e1a7e36521caff281da687764a0c43e428 |
|
06-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Still need to support -mcpu=<> or cross compilation will fail. Doh.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30764 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| abc346ceda2374971513535f21cea5fcb4b7cf46 |
|
06-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Do away with CPU feature list. Just use CPUID to detect MMX, SSE, SSE2, SSE3, and 64-bit support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30763 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 88c1578011e0beec5e81889ff27f6cbff523e771 |
|
06-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
It appears the inline asm in GetCpuIDAndInfo() may clobbers some registers if it isn't inlined (at < -O3). Force it to be inlined.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30762 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 8e0055de8a5b397172f985550f7e3380b026d647 |
|
04-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Formating.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30722 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 25ab690a43cbbb591b76d49e3595b019c32f4b3f |
|
08-Sep-2006 |
Evan Cheng <evan.cheng@apple.com> |
Committing X86-64 support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30177 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| cdb341dcfa371b842d0299250e961e4206a5ff5a |
|
08-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Fix a cross-build issue. The asmsyntax shouldn't be affected by the build
host, it should be affected by the target. Allow the command line option to
override in either case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30164 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 05a059d5d8d039dbbec3607b313c38fba14f972e |
|
07-Sep-2006 |
Jim Laskey <jlaskey@mac.com> |
Make the x86 asm flavor part of the subtarget info.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30146 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 54edc840005074e6119fa4ca3c2c020ec02a6627 |
|
16-Jun-2006 |
Evan Cheng <evan.cheng@apple.com> |
Later models likely to have Yonah like attributes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28843 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 932ad51feabc4119dda978c4f147dfe1b010a95d |
|
25-May-2006 |
Evan Cheng <evan.cheng@apple.com> |
X86 / Cygwin asm / alignment fixes.
Patch contributed by Anton Korobeynikov!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 7ccced634ae0ecdc1c4f599fd3abf188c367e231 |
|
18-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
x86 / Darwin PIC support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26273 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 18a8452f3d2cc0bbfea427b10e2c7dccc86f2188 |
|
16-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
A bit more memset / memcpy optimization.
Turns them into calls to memset / memcpy if 1) buffer(s) are not DWORD aligned,
2) size is not known to be greater or equal to some minimum value (currently 128).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26224 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| ddf7532442cf2d7b47dfd767edcfbc4298e173ea |
|
14-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Duh
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 968c1781726511e4f90ca78355a3c1b582c22692 |
|
14-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Remove -disable-x86-sse
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 82eaf628b4c9574f297bc1d8c44ae5237bc62a8c |
|
14-Feb-2006 |
Evan Cheng <evan.cheng@apple.com> |
Enable SSE (for the right subtargets)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26169 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c4013d677202d34750280c960ab54856f17ef465 |
|
28-Jan-2006 |
Jeff Cohen <jeffc@jolt-lang.org> |
Flesh out AMD family/models.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25755 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 216d281d0a2b005585f449a512025e5062152f58 |
|
28-Jan-2006 |
Jeff Cohen <jeffc@jolt-lang.org> |
Correctly determine CPU vendor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| a349640b7f39bba1ccce1b6d135c2a4239b2ccb7 |
|
28-Jan-2006 |
Jeff Cohen <jeffc@jolt-lang.org> |
Use union instead of reinterpret_cast.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25751 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 76177174960d03c6ac35acc27e9b45e206a6f633 |
|
28-Jan-2006 |
Jeff Cohen <jeffc@jolt-lang.org> |
Fix recognition of Intel CPUs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25750 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| c2fad16155d7b3d8499c01c538bb90fb4d5252b5 |
|
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
Is64Bit reflects the capability of the chip, not an aspect of the target os
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25749 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 41adb0d679416397b4c8153ad55f75453107bc8d |
|
28-Jan-2006 |
Jeff Cohen <jeffc@jolt-lang.org> |
Improve X86 subtarget support for Windows and AMD.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25747 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 1e39a15b42a55a8dea3d9485e7ea7ce77af5f4ef |
|
28-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
make this work on non-native hosts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 104988a16a710dee8c42998b414248ae81e63c1f |
|
27-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
initialize all instance vars
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| dbd38d7f64697b72364387e25dd062c5ce276466 |
|
27-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added a temporary option -enable-x86-sse to enable sse support. It is used by
llc-beta.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25701 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| b3a7e21b7e441ed4d51e673b0890aed6b0524566 |
|
27-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
A better workaround
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 9f96a3283159d4912ebeb7504e1c467b5e6392b9 |
|
27-Jan-2006 |
Chris Lattner <sabre@nondot.org> |
force sse/3dnow off until they work. This fixes all the x86 failures last night
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 559806f575297866609c7bef0e5c1084dcdda9a5 |
|
27-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
x86 CPU detection and proper subtarget support
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 97c7fc351e4dd73041bc7e47c8a144216a50a648 |
|
26-Jan-2006 |
Evan Cheng <evan.cheng@apple.com> |
Added preliminary x86 subtarget support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25645 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| d460f57d65ce7d1d0db6f0183d31eae1ecdb8788 |
|
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Simplify the subtarget info, allow the asmwriter to do some target sensing
based on TargetType.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| e5600e5509be43097e5f3b7e0f5d33305dc77630 |
|
21-Nov-2005 |
Chris Lattner <sabre@nondot.org> |
Make the X86 subtarget compute the basic target type: ELF, Cygwin, Darwin,
or native Win32
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24476 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| b1e1180ca0b32f37aa74d7ad703eeaf91e66c8fa |
|
01-Sep-2005 |
Jim Laskey <jlaskey@mac.com> |
1. Use SubtargetFeatures in llc/lli.
2. Propagate feature "string" to all targets.
3. Implement use of SubtargetFeatures in PowerPCTargetSubtarget.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23192 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 8c00f8cdc7ae0cdd18d91b3a31a70da0f78aa04f |
|
04-Aug-2005 |
Nate Begeman <natebegeman@mac.com> |
Add Subtarget support to PowerPC. Next up, using it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22644 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 00b16889ab461b7ecef1c91ade101186b7f1fce2 |
|
27-Jul-2005 |
Jeff Cohen <jeffc@jolt-lang.org> |
Eliminate all remaining tabs and trailing spaces.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22523 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| 0e219eb9b8a2f6cb1128066584b06c6bd1b51238 |
|
12-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Clean up the TargetSubtarget class a bit, removing an unnecessary argument
to the constructor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22392 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| b151acadc85011961e24d98fa6ce626ea45cd074 |
|
12-Jul-2005 |
Chris Lattner <sabre@nondot.org> |
Minor changes to improve comments and fix the build on _WIN32 systems.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|
| fb5792f416089d8d8d0c6ee62c1f41a55d2cf75d |
|
12-Jul-2005 |
Nate Begeman <natebegeman@mac.com> |
Implement Subtarget support
Implement the X86 Subtarget.
This consolidates the checks for target triple, and setting options based
on target triple into one place. This allows us to convert the asm printer
and isel over from being littered with "forDarwin", "forCygwin", etc. into
just having the appropriate flags for each subtarget feature controlling
the code for that feature.
This patch also implements indirect external and weak references in the
X86 pattern isel, for darwin. Next up is to convert over the asm printers
to use this new interface.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22389 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/X86/X86Subtarget.cpp
|