| 32118cfe37495738ed5931c6b1a71b8ee2ad189c |
|
06-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Don't make consumers of brw_DO()/brw_WHILE() track loop start.
This is a similar cleanup to what we did for brw_IF(), brw_ELSE(),
brw_ENDIF() handling.
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 2252e5e3f1e8caece5c73df82f3ddf306baa2c91 |
|
02-Dec-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: Clean up misleading defines for DWORD 2 of URB_WRITE header.
R02_PRIM_END and R02_PRIM_START don't actually refer to bits in DWORD
2 of R0 (as the name, and comments in the code, would seem to
indicate). Actually they refer to bits in DWORD 2 of the header for
URB_WRITE messages.
This patch renames the defines to reflect what they actually mean. It
also addes a define URB_WRITE_PRIM_TYPE_SHIFT, which previously was
just hardcoded in .c files.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 2ef1fa6b3c8d52e059bf6ccf519c45604962b27c |
|
01-Sep-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: clip: Convert computations to ..._to_offset() for clarity.
This patch replaces some ad-hoc computations using ATTR_SIZE and the
offset[] array to use the VUE map functions
brw_vert_result_to_offset() and brw_vue_slot_to_offset().
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 2bc421845e7d334bc5a91b62d834b8f77e769570 |
|
25-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: clip: Modify brw_clip_tri_alloc_regs() to use the VUE map.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 62b0c8561e2d259e4dc1f27346bf2f36c3b098c8 |
|
25-Aug-2011 |
Paul Berry <stereotype441@gmail.com> |
i965: clip: Move hpos_offest and ndc_offset into local functions.
The offsets within the VUE of HPOS and NDC are needed only in a few
auxiliary clipping functions. This patch moves computation of those
offsets into the functions that need them, and does the computation
using the VUE map.
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 5936d96d33e767aa99f6afa92f2a6582ff04df23 |
|
16-May-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Move IF stack handling into the EU abstraction layer/brw_compile.
This hides the IF stack and back-patching of IF/ELSE instructions from
each of the code generators, greatly simplifying the interface.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 09788ce10e354b3af6139c04a13b38df18632b13 |
|
20-Jul-2010 |
Eric Anholt <eric@anholt.net> |
i965: Reduce repeated calculation of the attribute-offset-in-VUE.
This cleans up some chipset dependency sprinkled around, and fixes a
potential overflow of the attribute offset array for many vertex
results.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| ec2b92f98c2e7f161521b447cc1d9a36bce3707c |
|
11-Jun-2010 |
Brian Paul <brianp@vmware.com> |
mesa: rename src/mesa/shader/ to src/mesa/program/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 4e84dc8729cac4c78e521436ae091638a490da76 |
|
15-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Set the correct provoking vertex for clipped first-mode trifans.
Bug #24470: glean clipFlat test.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 9b22427911ad27efc1f36faee9462c6082d0417c |
|
25-Jan-2010 |
Brian Paul <brianp@vmware.com> |
Merge branch 'mesa_7_7_branch'
Conflicts:
src/mesa/drivers/dri/intel/intel_screen.c
src/mesa/drivers/dri/intel/intel_swapbuffers.c
src/mesa/drivers/dri/r300/r300_emit.c
src/mesa/drivers/dri/r300/r300_ioctl.c
src/mesa/drivers/dri/r300/r300_tex.c
src/mesa/drivers/dri/r300/r300_texstate.c
|
| 634ec5c2abf05a9a8c27d9199ded5d1ad91e538a |
|
23-Jan-2010 |
Vinson Lee <vlee@vmware.com> |
i965: Remove unnecessary headers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| cb3810dd19760797e699c47929f655b829c4d339 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_965 checks with context structure usage.
Saves another 600 bytes or so of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| ab12e764ba3f57ad9f0d7252262cfc6e07839928 |
|
12-Nov-2009 |
Roland Scheidegger <sroland@vmware.com> |
i965: fix EXT_provoking_vertex support
This didn't work for quad/quadstrips at all, and for all other primitive types
it only worked when they were unclipped.
Fix up the former in gs stage (could probably do without these changes and
instead set QuadsFollowProvokingVertexConvention to false), and the rest in
clip stage.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 3e2b6a204966b962c9881e90fe3f0b74cf84d8c4 |
|
30-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: Postpone ff_sync message in CLIP kernel on IGDNG
In addition, it guarantees ff_sync message is issued
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 68915fd6fac44dd000080298e3afb0669e8754aa |
|
26-Feb-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: fix for RHW workaround
It is possible that an object whose vertices all are outside of a
view plane is passed to clip thread due to the RHW workaround. This
object should be rejected by clip thread. Fix bug #19879
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 34b1776e8d965605d12807884c9c447214d57281 |
|
02-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Merge GM45 into the G4X chipset define.
The mobile and desktop chipsets are the same, and having them separate is
more typing and more chances to screw up.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| ecadb51bbcb972a79f3ed79e65a7986b9396e757 |
|
18-Sep-2008 |
Brian Paul <brian.paul@tungstengraphics.com> |
mesa: added "main/" prefix to includes, remove some -I paths from Makefile.template
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| a35002c1673a1a37ec79b237dda7e8f6b9c9962a |
|
22-Aug-2008 |
Krzysztof Czurylo <krzysztof.czurylo@intel.com> |
965: Fix incorrect backface culling
Fix incorrect backface culling for OGL tunnel in wireframe and
point mode.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 92c075eeb7c330ea420400d1c2bae57356b19f03 |
|
08-Jul-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: official name for GM45 chipset
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 08f9b190a798c9c61ae07208345d0c2b37e54d39 |
|
17-Apr-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
Revert "[i965] renable regative rhw test"
This reverts commit 3158e981f5f37768e9b04765704b9eaece8b899b.
rhw issue has gone away on IGD.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 3158e981f5f37768e9b04765704b9eaece8b899b |
|
31-Jan-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] renable regative rhw test
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
|
29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| fc81f428176c8914fd2ea8691390c9171a125618 |
|
25-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: re-define the type of reg.loopcount.
avoid some issues such that 1 + (-2) gets a big
positive value.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| aa88d11e7d881f0dd4c02fcefceb4085bdb3cf8a |
|
27-Sep-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
fix ppracer and bzflag issue with clip optimization
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| b47c9f8c915ae4ca8c7fa5ee3b6b64f17c38b569 |
|
31-Aug-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
optimize 965 clip
1. increase clip thread number to 2
2. do cliptest for -rhw
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_clip_tri.c
|