Searched defs:Tmp1 (Results 1 - 19 of 19) sorted by relevance

/external/chromium_org/third_party/mesa/src/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp243 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
244 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, local
257 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
258 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
273 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
274 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
/external/llvm/lib/CodeGen/
H A DIntrinsicLowering.cpp176 Value *Tmp1 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8), local
180 V = Builder.CreateOr(Tmp1, Tmp2, "bswap.i16");
190 Value *Tmp1 = Builder.CreateLShr(V,ConstantInt::get(V->getType(), 24), local
199 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or2");
220 Value* Tmp1 = Builder.CreateLShr(V, local
250 Tmp2 = Builder.CreateOr(Tmp2, Tmp1, "bswap.or4");
/external/mesa3d/src/gallium/drivers/radeon/
H A DAMDGPUISelLowering.cpp243 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
244 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, local
257 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
258 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
273 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
274 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
/external/llvm/lib/Target/R600/
H A DAMDGPUISelLowering.cpp402 // Tmp1 = Remainder_GE_Den & Remainder_GE_Zero
403 SDValue Tmp1 = DAG.getNode(ISD::AND, DL, VT, Remainder_GE_Den, local
416 // Div = (Tmp1 == 0 ? Quotient : Quotient_A_One)
417 SDValue Div = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
432 // Rem = (Tmp1 == 0 ? Remainder : Remainder_S_Den)
433 SDValue Rem = DAG.getSelectCC(DL, Tmp1, DAG.getConstant(0, VT),
/external/llvm/lib/CodeGen/SelectionDAG/
H A DLegalizeDAG.cpp578 SDValue Tmp1 = Vec; local
588 EVT VT = Tmp1.getValueType();
597 SDValue Ch = DAG.getStore(DAG.getEntryNode(), dl, Tmp1, StackPtr,
1502 SDValue Tmp1 = Node->getOperand(0);
1553 SDValue AbsVal = DAG.getNode(ISD::FABS, dl, Tmp1.getValueType(), Tmp1);
1568 SDValue Tmp1 = SDValue(Node, 0);
1571 SDValue Chain = Tmp1.getOperand(0);
1586 Tmp1 = DAG.getNode(ISD::SUB, dl, VT, SP, Size); // Value
1587 Chain = DAG.getCopyToReg(Chain, dl, SPReg, Tmp1); // Outpu
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H A DLegalizeVectorOps.cpp278 SDValue Tmp1 = TLI.LowerOperation(Op, DAG); local
279 if (Tmp1.getNode()) {
280 Result = Tmp1;
H A DLegalizeFloatTypes.cpp1295 SDValue Tmp1, Tmp2, Tmp3; local
1296 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1300 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1301 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSHi.getValueType()),
1305 Tmp1 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1306 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp
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H A DLegalizeIntegerTypes.cpp2563 // Tmp1 = lo(op1) < lo(op2) // Always unsigned comparison
2565 // dest = hi(op1) == hi(op2) ? Tmp1 : Tmp2;
2570 SDValue Tmp1, Tmp2; local
2571 Tmp1 = TLI.SimplifySetCC(getSetCCResultType(LHSLo.getValueType()),
2573 if (!Tmp1.getNode())
2574 Tmp1 = DAG.getSetCC(dl, getSetCCResultType(LHSLo.getValueType()),
2583 ConstantSDNode *Tmp1C = dyn_cast<ConstantSDNode>(Tmp1.getNode());
2606 NewLHS = DAG.getSelect(dl, Tmp1.getValueType(),
2607 NewLHS, Tmp1, Tmp2);
/external/llvm/lib/Transforms/Utils/
H A DIntegerDivision.cpp106 Value *Tmp1 = Builder.CreateAShr(Divisor, ThirtyOne); local
109 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor);
110 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1);
111 Value *Q_Sgn = Builder.CreateXor(Tmp1, Tmp);
213 Value *Tmp1 = Builder.CreateCall2(CTLZi32, Dividend, True); local
214 Value *SR = Builder.CreateSub(Tmp0, Tmp1);
/external/clang/lib/StaticAnalyzer/Core/
H A DCheckerManager.cpp108 ExplodedNodeSet Tmp1, Tmp2; local
116 CurrSet = (PrevSet == &Tmp1) ? &Tmp2 : &Tmp1;
/external/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp442 SDValue Tmp1, Tmp2; local
1357 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); local
1360 return CurDAG->getMachineNode(Opc3, dl, VT, SDValue(Tmp1, 0),
1371 SDNode *Tmp1 = CurDAG->getMachineNode(Opc1, dl, VT, EltVal); local
1374 return CurDAG->getMachineNode(Opc2, dl, VT, SDValue(Tmp1, 0),
H A DPPCISelLowering.cpp5019 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, local
5022 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
5048 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, local
5051 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
5076 SDValue Tmp1 = DAG.getNode(ISD::SUB, dl, AmtVT, local
5079 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
/external/clang/lib/CodeGen/
H A DCGExprComplex.cpp579 llvm::Value *Tmp1 = Builder.CreateFMul(LHSr, RHSr); // a*c local
581 llvm::Value *Tmp3 = Builder.CreateFAdd(Tmp1, Tmp2); // ac+bd
595 llvm::Value *Tmp1 = Builder.CreateMul(LHSr, RHSr); // a*c local
597 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd
/external/llvm/lib/Target/Hexagon/
H A DHexagonHardwareLoops.cpp1432 SmallVector<MachineOperand,2> Tmp1; local
1435 if (TII->AnalyzeBranch(*Latch, TB, FB, Tmp1, false))
1441 bool NotAnalyzed = TII->AnalyzeBranch(*PB, TB, FB, Tmp1, false);
/external/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp1294 SDValue Tmp1 = ST->getChain(); local
1302 SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
/external/webrtc/src/modules/audio_coding/codecs/isac/main/source/
H A Dstructs.h251 double Tmp1[MAXFFTSIZE]; member in struct:__anon28097
/external/llvm/lib/Target/X86/
H A DX86ISelDAGToDAG.cpp1567 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
1568 if (!SelectAddr(Node, In1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1572 const SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, In2L, In2H, Chain};
1768 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
1769 if (!SelectAddr(Node, Ptr, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4))
1841 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Chain };
1844 SDValue Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Val, Chain };
2317 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
2318 bool foldedLoad = TryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4);
2321 foldedLoad = TryFoldLoad(Node, N0, Tmp0, Tmp1, Tmp
2458 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4; local
2466 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Move, Chain; local
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H A DX86ISelLowering.cpp8308 SDValue Tmp1 = isSRA ? DAG.getNode(ISD::SRA, dl, VT, ShOpHi, local
8329 SDValue Ops1[4] = { Tmp3, Tmp1, CC, Cond };
12552 SDValue Tmp1; local
12556 Tmp1 = LowerVectorIntExtend(Op00, DAG);
12557 if (Tmp1.getNode()) {
12558 SDValue Tmp1Op0 = Tmp1.getOperand(0);
12565 Tmp1 = getTargetVShiftNode(X86ISD::VSHLI, dl, VT, Op0, ShAmt, DAG);
12566 return getTargetVShiftNode(X86ISD::VSRAI, dl, VT, Tmp1, ShAmt, DAG);
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp3513 SDValue Tmp1 = Op.getOperand(1); local
3516 EVT SrcVT = Tmp1.getValueType();
3534 Tmp1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v2f32, Tmp1);
3536 Tmp1 = DAG.getNode(ARMISD::VSHL, dl, OpVT,
3537 DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1),
3540 Tmp1 = DAG.getNode(ARMISD::VSHRu, dl, MVT::v1i64,
3541 DAG.getNode(ISD::BITCAST, dl, MVT::v1i64, Tmp1),
3544 Tmp1 = DAG.getNode(ISD::BITCAST, dl, OpVT, Tmp1);
3742 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt); local
3776 SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt); local
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