Searched defs:VReg (Results 1 - 18 of 18) sorted by relevance

/external/llvm/lib/CodeGen/
H A DLiveIntervalUnion.cpp149 LiveInterval *VReg = LiveUnionI.value(); local
150 if (VReg != RecentReg && !isSeenInterference(VReg)) {
151 RecentReg = VReg;
152 InterferingVRegs.push_back(VReg);
H A DLiveRangeEdit.cpp34 unsigned VReg = MRI.createVirtualRegister(MRI.getRegClass(OldReg)); local
37 VRM->setIsSplitFromReg(VReg, VRM->getOriginal(OldReg));
39 LiveInterval &LI = LIS.getOrCreateInterval(VReg);
H A DTailDuplication.cpp231 unsigned VReg = SSAUpdateVRs[i]; local
232 SSAUpdate.Initialize(VReg);
236 MachineInstr *DefMI = MRI->getVRegDef(VReg);
240 SSAUpdate.AddAvailableValue(DefBB, VReg);
245 SSAUpdateVals.find(VReg);
253 MachineRegisterInfo::use_iterator UI = MRI->use_begin(VReg);
H A DMachineFunction.cpp426 unsigned VReg = MRI.getLiveInVirtReg(PReg); local
427 if (VReg) {
428 assert(MRI.getRegClass(VReg) == RC && "Register class mismatch!");
429 return VReg;
431 VReg = MRI.createVirtualRegister(RC);
432 MRI.addLiveIn(PReg, VReg);
433 return VReg;
/external/llvm/lib/Target/NVPTX/InstPrinter/
H A DNVPTXInstPrinter.cpp68 unsigned VReg = RegNo & 0x0FFFFFFF; local
69 OS << VReg; local
/external/llvm/include/llvm/CodeGen/
H A DLiveIntervalUnion.h119 Query(LiveInterval *VReg, LiveIntervalUnion *LIU): argument
120 LiveUnion(LIU), VirtReg(VReg), CheckedFirstInterference(false),
135 void init(unsigned UTag, LiveInterval *VReg, LiveIntervalUnion *LIU) { argument
136 assert(VReg && LIU && "Invalid arguments");
137 if (UserTag == UTag && VirtReg == VReg &&
144 VirtReg = VReg;
162 bool isSeenInterference(LiveInterval *VReg) const;
/external/llvm/lib/CodeGen/SelectionDAG/
H A DInstrEmitter.cpp272 unsigned VReg = getDstOfOnlyCopyToRegUse(Op.getNode(), Op.getResNo()); local
275 if (!VReg) {
278 VReg = MRI->createVirtualRegister(RC);
281 TII->get(TargetOpcode::IMPLICIT_DEF), VReg);
282 return VReg;
305 unsigned VReg = getVR(Op, VRBaseMap); local
306 assert(TargetRegisterInfo::isVirtualRegister(VReg) && "Not a vreg?");
314 // shrink VReg's register class within reason. For example, if VReg == GR32
315 // and II requires a GR32_NOSP, just constrain VReg t
[all...]
/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp351 unsigned VReg = RegInfo.createVirtualRegister(&MSP430::GR16RegClass); local
352 RegInfo.addLiveIn(VA.getLocReg(), VReg);
353 SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
/external/llvm/lib/Target/R600/
H A DSIISelLowering.cpp707 // VReg or and SReg. In order to get a more accurate
1019 unsigned VReg = MI->getOperand(0).getReg(); local
1034 MRI.setRegClass(VReg, RC);
1076 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT); local
1079 cast<RegisterSDNode>(VReg)->getReg(), VT);
/external/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp858 unsigned VReg = local
860 RegInfo.addLiveIn(VA.getLocReg(), VReg);
861 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
863 unsigned VReg = local
865 RegInfo.addLiveIn(VA.getLocReg(), VReg);
866 InVals.push_back(DAG.getCopyFromReg(Chain, dl, VReg, RegVT));
/external/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp393 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); local
394 MF.getRegInfo().addLiveIn(VA.getLocReg(), VReg);
395 SDValue Arg = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
505 unsigned VReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass); local
506 MF.getRegInfo().addLiveIn(*CurArgReg, VReg);
507 SDValue Arg = DAG.getCopyFromReg(DAG.getRoot(), dl, VReg, MVT::i32);
556 unsigned VReg = MF.addLiveIn(VA.getLocReg(), local
558 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
627 unsigned VReg = MF.addLiveIn(SP::I0 + ArgOffset/8, &SP::I64RegsRegClass); local
628 SDValue VArg = DAG.getCopyFromReg(Chain, DL, VReg, MV
[all...]
/external/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp623 unsigned VReg = MRI.createVirtualRegister(RC); local
624 MRI.addLiveIn(VA.getLocReg(), VReg);
625 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
674 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I], local
676 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
/external/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1119 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); local
1120 RegInfo.addLiveIn(VA.getLocReg(), VReg);
1121 ArgIn = DAG.getCopyFromReg(Chain, dl, VReg, RegVT);
1172 unsigned VReg = RegInfo.createVirtualRegister(&XCore::GRRegsRegClass); local
1173 RegInfo.addLiveIn(ArgRegs[i], VReg);
1174 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
/external/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp900 unsigned VReg = MF.addLiveIn(AArch64ArgRegs[i], &AArch64::GPR64RegClass); local
901 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::i64);
919 unsigned VReg = MF.addLiveIn(AArch64FPRArgRegs[i], local
921 SDValue Val = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f128);
/external/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp767 unsigned VReg = MF.getRegInfo().createVirtualRegister(RC); local
768 MF.getRegInfo().addLiveIn(PReg, VReg);
769 return VReg;
3375 unsigned VReg = addLiveIn(MF, ArgReg, RC); local
3379 SDValue Store = DAG.getStore(Chain, DL, DAG.getRegister(VReg, RegTy),
/external/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp2811 unsigned VReg = MF.addLiveIn(GPRArgRegs[firstRegToSaveIndex], RC); local
2812 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp2099 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]); local
2100 if (!VReg)
2101 VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
2103 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
2118 unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]); local
2119 if (!VReg)
2120 VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
2122 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
2289 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); local
2290 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrV
2327 unsigned VReg; local
2351 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); local
2375 unsigned VReg; local
2398 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); local
2453 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); local
2621 unsigned VReg; local
2645 unsigned VReg; local
2672 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass); local
2686 unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass); local
2713 unsigned VReg; local
2736 unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass); local
2798 unsigned VReg; local
[all...]
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp2346 unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs], local
2348 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
2373 unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs], local
2375 SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);

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