/dalvik/vm/compiler/template/mips/ |
H A D | TEMPLATE_SHL_LONG.S | 2 * Long integer shift. This is different from the generic 32/64-bit 3 * binary operations because vAA/vBB are 64-bit but vCC (the shift 8 sll rRESULT0, rARG0, a2 # rlo<- alo << (shift&31) 9 not rRESULT1, a2 # rhi<- 31-shift (shift is 5b) 11 srl rARG0, rRESULT1 # alo<- alo >> (32-(shift&31)) 12 sll rRESULT1, rARG1, a2 # rhi<- ahi << (shift&31) 14 andi a2, 0x20 # shift< shift & 0x20 15 movn rRESULT1, rRESULT0, a2 # rhi<- rlo (if shift [all...] |
H A D | TEMPLATE_USHR_LONG.S | 2 * Long integer shift. This is different from the generic 32/64-bit 3 * binary operations because vAA/vBB are 64-bit but vCC (the shift 8 srl rRESULT1, rARG1, a2 # rhi<- ahi >> (shift&31) 9 srl rRESULT0, rARG0, a2 # rlo<- alo >> (shift&31) 10 not rARG0, a2 # alo<- 31-n (shift is 5b) 12 sll rARG1, rARG0 # ahi<- ahi << (32-(shift&31)) 14 andi a2, 0x20 # shift & 0x20 15 movn rRESULT0, rRESULT1, a2 # rlo<- rhi (if shift&0x20) 16 movn rRESULT1, zero, a2 # rhi<- 0 (if shift&0x20)
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H A D | TEMPLATE_SHR_LONG.S | 2 * Long integer shift. This is different from the generic 32/64-bit 3 * binary operations because vAA/vBB are 64-bit but vCC (the shift 8 sra rRESULT1, rARG1, a2 # rhi<- ahi >> (shift&31) 9 srl rRESULT0, rARG0, a2 # rlo<- alo >> (shift&31) 11 not rARG0, a2 # alo<- 31-shift (shift is 5b) 13 sll rARG1, rARG0 # ahi<- ahi << (32-(shift&31)) 15 andi a2, 0x20 # shift & 0x20 16 movn rRESULT0, rRESULT1, a2 # rlo<- rhi (if shift&0x20) 17 movn rRESULT1, a3, a2 # rhi<- sign(ahi) (if shift [all...] |
/dalvik/vm/mterp/mips/ |
H A D | OP_SHL_LONG_2ADDR.S | 3 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 4 * 32-bit shift distance. 15 sll v0, a0, a2 # rlo<- alo << (shift&31) 16 not v1, a2 # rhi<- 31-shift (shift is 5b) 18 srl a0, v1 # alo<- alo >> (32-(shift&31)) 19 sll v1, a1, a2 # rhi<- ahi << (shift&31) 21 andi a2, 0x20 # shift< shift & 0x20 22 movn v1, v0, a2 # rhi<- rlo (if shift [all...] |
H A D | OP_USHR_LONG_2ADDR.S | 3 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 4 * 32-bit shift distance. 14 srl v1, a1, a2 # rhi<- ahi >> (shift&31) 15 srl v0, a0, a2 # rlo<- alo >> (shift&31) 16 not a0, a2 # alo<- 31-n (shift is 5b) 18 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 20 andi a2, 0x20 # shift & 0x20 21 movn v0, v1, a2 # rlo<- rhi (if shift&0x20) 22 movn v1, zero, a2 # rhi<- 0 (if shift&0x20)
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H A D | OP_SHL_LONG.S | 3 * Long integer shift. This is different from the generic 32/64-bit 4 * binary operations because vAA/vBB are 64-bit but vCC (the shift 6 * 6 bits of the shift distance. 20 sll v0, a0, a2 # rlo<- alo << (shift&31) 21 not v1, a2 # rhi<- 31-shift (shift is 5b) 23 srl a0, v1 # alo<- alo >> (32-(shift&31)) 24 sll v1, a1, a2 # rhi<- ahi << (shift&31) 26 andi a2, 0x20 # shift< shift [all...] |
H A D | OP_SHR_LONG.S | 3 * Long integer shift. This is different from the generic 32/64-bit 4 * binary operations because vAA/vBB are 64-bit but vCC (the shift 6 * 6 bits of the shift distance. 19 sra v1, a1, a2 # rhi<- ahi >> (shift&31) 20 srl v0, a0, a2 # rlo<- alo >> (shift&31) 22 not a0, a2 # alo<- 31-shift (shift is 5b) 24 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 26 andi a2, 0x20 # shift & 0x20 27 movn v0, v1, a2 # rlo<- rhi (if shift [all...] |
H A D | OP_SHR_LONG_2ADDR.S | 3 * Long integer shift, 2addr version. vA is 64-bit value/result, vB is 4 * 32-bit shift distance. 14 sra v1, a1, a2 # rhi<- ahi >> (shift&31) 15 srl v0, a0, a2 # rlo<- alo >> (shift&31) 17 not a0, a2 # alo<- 31-shift (shift is 5b) 19 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 21 andi a2, 0x20 # shift & 0x20 22 movn v0, v1, a2 # rlo<- rhi (if shift&0x20) 23 movn v1, a3, a2 # rhi<- sign(ahi) (if shift [all...] |
H A D | OP_USHR_LONG.S | 3 * Long integer shift. This is different from the generic 32/64-bit 4 * binary operations because vAA/vBB are 64-bit but vCC (the shift 6 * 6 bits of the shift distance. 19 srl v1, a1, a2 # rhi<- ahi >> (shift&31) 20 srl v0, a0, a2 # rlo<- alo >> (shift&31) 21 not a0, a2 # alo<- 31-n (shift is 5b) 23 sll a1, a0 # ahi<- ahi << (32-(shift&31)) 25 andi a2, 0x20 # shift & 0x20 26 movn v0, v1, a2 # rlo<- rhi (if shift&0x20) 27 movn v1, zero, a2 # rhi<- 0 (if shift [all...] |
H A D | OP_AGET.S | 1 %default { "load":"lw", "shift":"2" } 6 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 20 .if $shift 21 EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width
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H A D | OP_APUT.S | 1 %default { "store":"sw", "shift":"2" } 16 .if $shift 17 EASN(a0, a0, a1, $shift) # a0 <- arrayObj + index*width
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H A D | OP_EXECUTE_INLINE.S | 59 lw a3, 0(t1) # a3 <- vF (shift right 12, left 2)
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/dalvik/vm/alloc/ |
H A D | HeapBitmap.cpp | 110 const int shift = CLZ(word); local 111 Object* obj = (Object *)(ptrBase + shift * HB_OBJECT_ALIGNMENT); 113 word &= ~(highBit >> shift); 146 const int shift = CLZ(word); local 147 Object *obj = (Object *)(ptrBase + shift * HB_OBJECT_ALIGNMENT); 149 word &= ~(highBit >> shift); 194 int shift = CLZ(garbage); local 195 garbage &= ~(highBit >> shift); 196 *pb++ = (void *)(ptrBase + shift * HB_OBJECT_ALIGNMENT);
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/dalvik/vm/mterp/x86/ |
H A D | OP_AGET.S | 1 %default { "load":"movl", "shift":"4" } 19 $load offArrayObject_contents(%eax,%ecx,$shift),%eax
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H A D | OP_APUT.S | 1 %default { "reg":"rINST", "store":"movl", "shift":"4" } 19 leal offArrayObject_contents(%eax,%ecx,$shift),%eax
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/dalvik/vm/compiler/codegen/arm/Thumb2/ |
H A D | Factory.cpp | 307 int rSrc2, int shift) 309 bool thumbForm = ((shift == 0) && LOWREG(rDestSrc1) && LOWREG(rSrc2)); 322 assert(shift == 0); 328 else if ((shift == 0) && !LOWREG(rDestSrc1) && !LOWREG(rSrc2)) 330 else if ((shift == 0) && LOWREG(rDestSrc1)) 332 else if (shift == 0) 341 assert(shift == 0); 352 assert(shift == 0); 359 assert(shift == 0); 372 assert(shift 306 opRegRegShift(CompilationUnit *cUnit, OpKind op, int rDestSrc1, int rSrc2, int shift) argument 428 opRegRegRegShift(CompilationUnit *cUnit, OpKind op, int rDest, int rSrc1, int rSrc2, int shift) argument [all...] |
/dalvik/vm/compiler/codegen/mips/ |
H A D | CodegenCommon.cpp | 98 int shift; local 113 shift = kFPReg0; 116 shift = kFPRegEnd; 118 shift = 0; 122 shift += regId; 123 return (seed << shift);
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/dalvik/vm/mterp/armv5te/ |
H A D | OP_AGET.S | 1 %default { "load":"ldr", "shift":"2" } 6 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 20 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
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H A D | OP_APUT.S | 1 %default { "store":"str", "shift":"2" } 6 * Note: using the usual FETCH/and/shift stuff, this fits in exactly 17 20 add r0, r0, r1, lsl #$shift @ r0<- arrayObj + index*width
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H A D | OP_EXECUTE_INLINE.S | 54 ldr r3, [rFP, ip, lsr #10] @ r3<- vF (shift right 12, left 2)
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/dalvik/dx/etc/ |
H A D | dx.bat | 76 shift /1
81 shift /1
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/dalvik/vm/compiler/codegen/arm/ |
H A D | CodegenCommon.cpp | 95 int shift; local 103 shift = FPREG(reg) ? kFPReg0 : 0; 105 shift += regId; 106 return (seed << shift);
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/dalvik/vm/arch/arm/ |
H A D | CallEABI.S | 200 sub sp, sp, ip, lsr #21 @ shift right 24, then left 3
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/dalvik/vm/compiler/codegen/x86/libenc/ |
H A D | encoder.h | 125 // opcodes for shift instructions 493 // shift instructions: shl, shr, sar, shld, shrd, ror 494 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode opc, const RM_Opnd & rm, const Imm_Opnd & imm, Opnd_Size sz = size_platf); 495 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode opc, const RM_Opnd & rm, Opnd_Size sz = size_platf); 496 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode opc, const RM_Opnd & rm, const R_Opnd & r, const Imm_Opnd & imm, Opnd_Size sz = size_platf); 497 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode opc, const RM_Opnd & rm, const R_Opnd & r, Opnd_Size sz = size_platf);
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H A D | encoder.inl | 223 // shift instructions: shl, shr, sar, shld, shrd 224 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode shc, const RM_Opnd & rm, const Imm_Opnd & imm, Opnd_Size sz) { 231 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode shc, const RM_Opnd & rm, Opnd_Size sz) { 238 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode shc, const RM_Opnd & rm, 248 ENCODER_DECLARE_EXPORT char * shift(char * stream, Shift_Opcode shc, const RM_Opnd & rm,
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