/external/llvm/include/llvm/Target/ |
H A D | TargetSelectionDAGInfo.h | 60 SDValue Op3, unsigned Align, bool isVolatile, 77 SDValue Op3, unsigned Align, bool isVolatile, 93 SDValue Op3, unsigned Align, bool isVolatile, 57 EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 74 EmitTargetCodeForMemmove(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const argument 90 EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, unsigned Align, bool isVolatile, MachinePointerInfo DstPtrInfo) const argument
|
/external/llvm/lib/Target/XCore/Disassembler/ |
H A D | XCoreDisassembler.cpp | 271 unsigned &Op3) { 281 Op3 = (Op3High << 2) | fieldFromInstruction(Insn, 0, 2); 550 unsigned Op1, Op2, Op3; local 551 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 555 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 563 unsigned Op1, Op2, Op3; local 564 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 568 DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); 576 unsigned Op1, Op2, Op3; local 577 DecodeStatus S = Decode3OpInstruction(Insn, Op1, Op2, Op3); 270 Decode3OpInstruction(unsigned Insn, unsigned &Op1, unsigned &Op2, unsigned &Op3) argument 589 unsigned Op1, Op2, Op3; local 602 unsigned Op1, Op2, Op3; local 616 unsigned Op1, Op2, Op3; local 631 unsigned Op1, Op2, Op3; local 645 unsigned Op1, Op2, Op3; local 659 unsigned Op1, Op2, Op3, Op4, Op5, Op6; local 693 unsigned Op1, Op2, Op3, Op4, Op5; local 713 unsigned Op1, Op2, Op3; local 732 unsigned Op1, Op2, Op3; local [all...] |
/external/llvm/lib/Target/ARM/ |
H A D | ARMSelectionDAGInfo.h | 61 SDValue Op3, unsigned Align,
|
/external/llvm/lib/Target/X86/ |
H A D | X86CodeEmitter.cpp | 454 const MachineOperand &Op3 = MI.getOperand(Op+3); 459 if (Op3.isGlobal()) { 460 DispForReloc = &Op3; 461 } else if (Op3.isSymbol()) { 462 DispForReloc = &Op3; 463 } else if (Op3.isCPI()) { 465 DispForReloc = &Op3; 467 DispVal += MCE.getConstantPoolEntryAddress(Op3.getIndex()); 468 DispVal += Op3.getOffset(); 470 } else if (Op3 [all...] |
H A D | X86ISelDAGToDAG.cpp | 2785 SDValue Op0, Op1, Op2, Op3, Op4; local 2791 if (!SelectAddr(0, Op, Op0, Op1, Op2, Op3, Op4)) 2799 OutOps.push_back(Op3);
|
/external/llvm/include/llvm/CodeGen/ |
H A D | SelectionDAG.h | 767 SDValue Op3); 769 SDValue Op3, SDValue Op4); 771 SDValue Op3, SDValue Op4, SDValue Op5); 784 SDValue Op1, SDValue Op2, SDValue Op3); 800 EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3); 802 EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3); 823 SDValue Op1, SDValue Op2, SDValue Op3); 832 SDValue Op1, SDValue Op2, SDValue Op3); 839 SDValue Op3);
|
H A D | SelectionDAGNodes.h | 758 const SDValue &Op2, const SDValue &Op3) { 766 Ops[3].setInitial(Op3);
|
/external/llvm/lib/CodeGen/SelectionDAG/ |
H A D | SelectionDAG.cpp | 4986 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3) { argument 4987 SDValue Ops[] = { Op1, Op2, Op3 }; 4993 SDValue Op3, SDValue Op4) { 4994 SDValue Ops[] = { Op1, Op2, Op3, Op4 }; 5000 SDValue Op3, SDValue Op4, SDValue Op5) { 5001 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 }; 5079 SDValue Op2, SDValue Op3) { 5081 SDValue Ops[] = { Op1, Op2, Op3 }; 5138 SDValue Op3) { 5140 SDValue Ops[] = { Op1, Op2, Op3 }; 4992 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4) argument 4999 UpdateNodeOperands(SDNode *N, SDValue Op1, SDValue Op2, SDValue Op3, SDValue Op4, SDValue Op5) argument 5077 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5135 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5144 SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument 5299 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT, SDValue Op1, SDValue Op2, SDValue Op3) argument 5336 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, SDValue Op1, SDValue Op2, SDValue Op3) argument 5362 getMachineNode(unsigned Opcode, SDLoc dl, EVT VT1, EVT VT2, EVT VT3, SDValue Op1, SDValue Op2, SDValue Op3) argument [all...] |
H A D | SelectionDAGBuilder.cpp | 4491 SDValue Op3 = getValue(I.getArgOperand(2)); local 4496 DAG.setRoot(DAG.getMemcpy(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, false, 4509 SDValue Op3 = getValue(I.getArgOperand(2)); local 4514 DAG.setRoot(DAG.getMemset(getRoot(), sdl, Op1, Op2, Op3, Align, isVol, 4528 SDValue Op3 = getValue(I.getArgOperand(2)); local 4533 DAG.setRoot(DAG.getMemmove(getRoot(), sdl, Op1, Op2, Op3, Align, isVol,
|
H A D | LegalizeIntegerTypes.cpp | 195 SDValue Op3 = GetPromotedInteger(N->getOperand(3)); local 198 Op2, Op3, N->getMemOperand(), N->getOrdering(),
|
/external/llvm/include/llvm/Support/ |
H A D | PatternMatch.h | 1107 m_Intrinsic(const T0 &Op0, const T1 &Op1, const T2 &Op2, const T3 &Op3) { argument 1108 return m_CombineAnd(m_Intrinsic<IntrID>(Op0, Op1, Op2), m_Argument<3>(Op3));
|