1/*-
2 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $
27 */
28
29/*
30   Rewritten for Android.
31*/
32
33/* MIPS FPU floating point control register bits.
34 *
35 * 31-25  -> floating point conditions code bits set by FP compare
36 *           instructions
37 * 24     -> flush denormalized results to zero instead of
38 *           causing unimplemented operation exception.
39 * 23     -> Condition bit
40 * 22     -> In conjunction with FS detects denormalized
41 *           operands and replaces them internally with 0.
42 * 21     -> In conjunction with FS forces denormalized operands
43 *           to the closest normalized value.
44 * 20-18  -> reserved (read as 0, write with 0)
45 * 17     -> cause bit for unimplemented operation
46 * 16     -> cause bit for invalid exception
47 * 15     -> cause bit for division by zero exception
48 * 14     -> cause bit for overflow exception
49 * 13     -> cause bit for underflow exception
50 * 12     -> cause bit for inexact exception
51 * 11     -> enable exception for invalid exception
52 * 10     -> enable exception for division by zero exception
53 *  9     -> enable exception for overflow exception
54 *  8     -> enable exception for underflow exception
55 *  7     -> enable exception for inexact exception
56 *  6     -> flag invalid exception
57 *  5     -> flag division by zero exception
58 *  4     -> flag overflow exception
59 *  3     -> flag underflow exception
60 *  2     -> flag inexact exception
61 *  1-0   -> rounding control
62 *
63 *
64 * Rounding Control:
65 * 00 - rounding to nearest (RN)
66 * 01 - rounding toward zero (RZ)
67 * 10 - rounding (up) toward plus infinity (RP)
68 * 11 - rounding (down)toward minus infinity (RM)
69 */
70
71#ifndef _FENV_H_
72#define _FENV_H_
73
74#include <sys/types.h>
75
76__BEGIN_DECLS
77
78typedef __uint32_t    fenv_t;
79typedef __uint32_t    fexcept_t;
80
81/* Exception flags */
82#define FE_INVALID      0x40
83#define FE_DIVBYZERO    0x20
84#define FE_OVERFLOW     0x10
85#define FE_UNDERFLOW    0x08
86#define FE_INEXACT      0x04
87#define FE_ALL_EXCEPT   (FE_DIVBYZERO | FE_INEXACT | \
88                         FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
89#define _FCSR_CAUSE_SHIFT  10
90#define _ENABLE_SHIFT 5
91#define _FCSR_ENABLE_MASK (FE_ALL_EXCEPT << _ENABLE_SHIFT)
92
93/* Rounding modes */
94#define FE_TONEAREST    0x0000
95#define FE_TOWARDZERO   0x0001
96#define FE_UPWARD       0x0002
97#define FE_DOWNWARD     0x0003
98#define _FCSR_RMODE_SHIFT 0
99#define _FCSR_RMASK       0x3
100/* Default floating-point environment */
101extern const fenv_t    __fe_dfl_env;
102#define FE_DFL_ENV    (&__fe_dfl_env)
103
104static __inline int fegetenv(fenv_t* __envp) {
105   fenv_t _fcsr = 0;
106#ifdef  __mips_hard_float
107   __asm__ __volatile__("cfc1 %0,$31" : "=r" (_fcsr));
108#endif
109   *__envp = _fcsr;
110   return 0;
111}
112
113static __inline int fesetenv(const fenv_t* __envp) {
114  fenv_t _fcsr = *__envp;
115#ifdef  __mips_hard_float
116  __asm__ __volatile__("ctc1 %0,$31" : : "r" (_fcsr));
117#endif
118  return 0;
119}
120
121static __inline int feclearexcept(int __excepts) {
122  fexcept_t __fcsr;
123  fegetenv(&__fcsr);
124  __excepts &= FE_ALL_EXCEPT;
125  __fcsr &= ~(__excepts | (__excepts << _FCSR_CAUSE_SHIFT));
126  fesetenv(&__fcsr);
127  return 0;
128}
129
130static __inline int fegetexceptflag(fexcept_t* __flagp, int __excepts) {
131  fexcept_t __fcsr;
132  fegetenv(&__fcsr);
133  *__flagp = __fcsr & __excepts & FE_ALL_EXCEPT;
134  return 0;
135}
136
137static __inline int fesetexceptflag(const fexcept_t* __flagp, int __excepts) {
138  fexcept_t __fcsr;
139  fegetenv(&__fcsr);
140  /* Ensure that flags are all legal */
141  __excepts &= FE_ALL_EXCEPT;
142  __fcsr &= ~__excepts;
143  __fcsr |= *__flagp & __excepts;
144  fesetenv(&__fcsr);
145  return 0;
146}
147
148static __inline int feraiseexcept(int __excepts) {
149  fexcept_t __fcsr;
150  fegetenv(&__fcsr);
151  /* Ensure that flags are all legal */
152  __excepts &= FE_ALL_EXCEPT;
153  /* Cause bit needs to be set as well for generating the exception*/
154  __fcsr |= __excepts | (__excepts << _FCSR_CAUSE_SHIFT);
155  fesetenv(&__fcsr);
156  return 0;
157}
158
159static __inline int fetestexcept(int __excepts) {
160  fexcept_t __FCSR;
161  fegetenv(&__FCSR);
162  return (__FCSR & __excepts & FE_ALL_EXCEPT);
163}
164
165static __inline int fegetround(void) {
166  fenv_t _fcsr;
167  fegetenv(&_fcsr);
168  return (_fcsr & _FCSR_RMASK);
169}
170
171static __inline int fesetround(int __round) {
172  fenv_t _fcsr;
173  fegetenv(&_fcsr);
174  _fcsr &= ~_FCSR_RMASK;
175  _fcsr |= (__round & _FCSR_RMASK ) ;
176  fesetenv(&_fcsr);
177  return 0;
178}
179
180static __inline int feholdexcept(fenv_t* __envp) {
181  fenv_t __env;
182  fegetenv(&__env);
183  *__envp = __env;
184  __env &= ~(FE_ALL_EXCEPT | _FCSR_ENABLE_MASK);
185  fesetenv(&__env);
186  return 0;
187}
188
189static __inline int feupdateenv(const fenv_t* __envp) {
190  fexcept_t __fcsr;
191  fegetenv(&__fcsr);
192  fesetenv(__envp);
193  feraiseexcept(__fcsr & FE_ALL_EXCEPT);
194  return 0;
195}
196
197#if __BSD_VISIBLE
198
199static __inline int feenableexcept(int __mask) {
200  fenv_t __old_fcsr, __new_fcsr;
201  fegetenv(&__old_fcsr);
202  __new_fcsr = __old_fcsr | (__mask & FE_ALL_EXCEPT) << _ENABLE_SHIFT;
203  fesetenv(&__new_fcsr);
204  return ((__old_fcsr >> _ENABLE_SHIFT) & FE_ALL_EXCEPT);
205}
206
207static __inline int fedisableexcept(int __mask) {
208  fenv_t __old_fcsr, __new_fcsr;
209  fegetenv(&__old_fcsr);
210  __new_fcsr = __old_fcsr & ~((__mask & FE_ALL_EXCEPT) << _ENABLE_SHIFT);
211  fesetenv(&__new_fcsr);
212  return ((__old_fcsr >> _ENABLE_SHIFT) & FE_ALL_EXCEPT);
213}
214
215static __inline int fegetexcept(void) {
216  fenv_t __fcsr;
217  fegetenv(&__fcsr);
218  return ((__fcsr & _FCSR_ENABLE_MASK) >> _ENABLE_SHIFT);
219}
220
221#endif /* __BSD_VISIBLE */
222
223__END_DECLS
224
225#endif /* !_FENV_H_ */
226