1//===-- AArch64AsmBackend.cpp - AArch64 Assembler Backend -----------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains the AArch64 implementation of the MCAsmBackend class,
11// which is principally concerned with relaxation of the various fixup kinds.
12//
13//===----------------------------------------------------------------------===//
14
15#include "MCTargetDesc/AArch64FixupKinds.h"
16#include "MCTargetDesc/AArch64MCTargetDesc.h"
17#include "llvm/MC/MCAsmBackend.h"
18#include "llvm/MC/MCSubtargetInfo.h"
19#include "llvm/MC/MCELFObjectWriter.h"
20#include "llvm/MC/MCFixupKindInfo.h"
21#include "llvm/MC/MCObjectWriter.h"
22#include "llvm/Support/ELF.h"
23#include "llvm/Support/ErrorHandling.h"
24#include "llvm/Support/raw_ostream.h"
25using namespace llvm;
26
27namespace {
28class AArch64AsmBackend : public MCAsmBackend {
29  const MCSubtargetInfo* STI;
30public:
31  AArch64AsmBackend(const Target &T, const StringRef TT)
32    : MCAsmBackend(),
33      STI(AArch64_MC::createAArch64MCSubtargetInfo(TT, "", ""))
34    {}
35
36
37  ~AArch64AsmBackend() {
38    delete STI;
39  }
40
41  bool writeNopData(uint64_t Count, MCObjectWriter *OW) const;
42
43  virtual void processFixupValue(const MCAssembler &Asm,
44                                 const MCAsmLayout &Layout,
45                                 const MCFixup &Fixup, const MCFragment *DF,
46                                 MCValue &Target, uint64_t &Value,
47                                 bool &IsResolved);
48};
49} // end anonymous namespace
50
51void AArch64AsmBackend::processFixupValue(const MCAssembler &Asm,
52                                          const MCAsmLayout &Layout,
53                                          const MCFixup &Fixup,
54                                          const MCFragment *DF,
55                                          MCValue &Target, uint64_t &Value,
56                                          bool &IsResolved) {
57  // The ADRP instruction adds some multiple of 0x1000 to the current PC &
58  // ~0xfff. This means that the required offset to reach a symbol can vary by
59  // up to one step depending on where the ADRP is in memory. For example:
60  //
61  //     ADRP x0, there
62  //  there:
63  //
64  // If the ADRP occurs at address 0xffc then "there" will be at 0x1000 and
65  // we'll need that as an offset. At any other address "there" will be in the
66  // same page as the ADRP and the instruction should encode 0x0. Assuming the
67  // section isn't 0x1000-aligned, we therefore need to delegate this decision
68  // to the linker -- a relocation!
69  if ((uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_page ||
70      (uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_prel_got_page ||
71      (uint32_t)Fixup.getKind() == AArch64::fixup_a64_adr_gottprel_page ||
72      (uint32_t)Fixup.getKind() == AArch64::fixup_a64_tlsdesc_adr_page)
73    IsResolved = false;
74}
75
76
77static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value);
78
79namespace {
80
81class ELFAArch64AsmBackend : public AArch64AsmBackend {
82public:
83  uint8_t OSABI;
84  ELFAArch64AsmBackend(const Target &T, const StringRef TT,
85                       uint8_t _OSABI)
86    : AArch64AsmBackend(T, TT), OSABI(_OSABI) { }
87
88  bool fixupNeedsRelaxation(const MCFixup &Fixup,
89                            uint64_t Value,
90                            const MCRelaxableFragment *DF,
91                            const MCAsmLayout &Layout) const;
92
93  unsigned int getNumFixupKinds() const {
94    return AArch64::NumTargetFixupKinds;
95  }
96
97  const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const {
98    const static MCFixupKindInfo Infos[AArch64::NumTargetFixupKinds] = {
99// This table *must* be in the order that the fixup_* kinds are defined in
100// AArch64FixupKinds.h.
101//
102// Name                   Offset (bits)    Size (bits)    Flags
103{ "fixup_a64_ld_prel",               0,    32, MCFixupKindInfo::FKF_IsPCRel },
104{ "fixup_a64_adr_prel",              0,    32, MCFixupKindInfo::FKF_IsPCRel },
105{ "fixup_a64_adr_prel_page",         0,    32, MCFixupKindInfo::FKF_IsPCRel },
106{ "fixup_a64_add_lo12",              0,    32,             0 },
107{ "fixup_a64_ldst8_lo12",            0,    32,             0 },
108{ "fixup_a64_ldst16_lo12",           0,    32,             0 },
109{ "fixup_a64_ldst32_lo12",           0,    32,             0 },
110{ "fixup_a64_ldst64_lo12",           0,    32,             0 },
111{ "fixup_a64_ldst128_lo12",          0,    32,             0 },
112{ "fixup_a64_tstbr",                 0,    32, MCFixupKindInfo::FKF_IsPCRel },
113{ "fixup_a64_condbr",                0,    32, MCFixupKindInfo::FKF_IsPCRel },
114{ "fixup_a64_uncondbr",              0,    32, MCFixupKindInfo::FKF_IsPCRel },
115{ "fixup_a64_call",                  0,    32, MCFixupKindInfo::FKF_IsPCRel },
116{ "fixup_a64_movw_uabs_g0",          0,    32,             0 },
117{ "fixup_a64_movw_uabs_g0_nc",       0,    32,             0 },
118{ "fixup_a64_movw_uabs_g1",          0,    32,             0 },
119{ "fixup_a64_movw_uabs_g1_nc",       0,    32,             0 },
120{ "fixup_a64_movw_uabs_g2",          0,    32,             0 },
121{ "fixup_a64_movw_uabs_g2_nc",       0,    32,             0 },
122{ "fixup_a64_movw_uabs_g3",          0,    32,             0 },
123{ "fixup_a64_movw_sabs_g0",          0,    32,             0 },
124{ "fixup_a64_movw_sabs_g1",          0,    32,             0 },
125{ "fixup_a64_movw_sabs_g2",          0,    32,             0 },
126{ "fixup_a64_adr_prel_got_page",     0,    32, MCFixupKindInfo::FKF_IsPCRel },
127{ "fixup_a64_ld64_got_lo12_nc",      0,    32,             0 },
128{ "fixup_a64_movw_dtprel_g2",        0,    32,             0 },
129{ "fixup_a64_movw_dtprel_g1",        0,    32,             0 },
130{ "fixup_a64_movw_dtprel_g1_nc",     0,    32,             0 },
131{ "fixup_a64_movw_dtprel_g0",        0,    32,             0 },
132{ "fixup_a64_movw_dtprel_g0_nc",     0,    32,             0 },
133{ "fixup_a64_add_dtprel_hi12",       0,    32,             0 },
134{ "fixup_a64_add_dtprel_lo12",       0,    32,             0 },
135{ "fixup_a64_add_dtprel_lo12_nc",    0,    32,             0 },
136{ "fixup_a64_ldst8_dtprel_lo12",     0,    32,             0 },
137{ "fixup_a64_ldst8_dtprel_lo12_nc",  0,    32,             0 },
138{ "fixup_a64_ldst16_dtprel_lo12",    0,    32,             0 },
139{ "fixup_a64_ldst16_dtprel_lo12_nc", 0,    32,             0 },
140{ "fixup_a64_ldst32_dtprel_lo12",    0,    32,             0 },
141{ "fixup_a64_ldst32_dtprel_lo12_nc", 0,    32,             0 },
142{ "fixup_a64_ldst64_dtprel_lo12",    0,    32,             0 },
143{ "fixup_a64_ldst64_dtprel_lo12_nc", 0,    32,             0 },
144{ "fixup_a64_movw_gottprel_g1",      0,    32,             0 },
145{ "fixup_a64_movw_gottprel_g0_nc",   0,    32,             0 },
146{ "fixup_a64_adr_gottprel_page",     0,    32, MCFixupKindInfo::FKF_IsPCRel },
147{ "fixup_a64_ld64_gottprel_lo12_nc", 0,    32,             0 },
148{ "fixup_a64_ld_gottprel_prel19",    0,    32, MCFixupKindInfo::FKF_IsPCRel },
149{ "fixup_a64_movw_tprel_g2",         0,    32,             0 },
150{ "fixup_a64_movw_tprel_g1",         0,    32,             0 },
151{ "fixup_a64_movw_tprel_g1_nc",      0,    32,             0 },
152{ "fixup_a64_movw_tprel_g0",         0,    32,             0 },
153{ "fixup_a64_movw_tprel_g0_nc",      0,    32,             0 },
154{ "fixup_a64_add_tprel_hi12",        0,    32,             0 },
155{ "fixup_a64_add_tprel_lo12",        0,    32,             0 },
156{ "fixup_a64_add_tprel_lo12_nc",     0,    32,             0 },
157{ "fixup_a64_ldst8_tprel_lo12",      0,    32,             0 },
158{ "fixup_a64_ldst8_tprel_lo12_nc",   0,    32,             0 },
159{ "fixup_a64_ldst16_tprel_lo12",     0,    32,             0 },
160{ "fixup_a64_ldst16_tprel_lo12_nc",  0,    32,             0 },
161{ "fixup_a64_ldst32_tprel_lo12",     0,    32,             0 },
162{ "fixup_a64_ldst32_tprel_lo12_nc",  0,    32,             0 },
163{ "fixup_a64_ldst64_tprel_lo12",     0,    32,             0 },
164{ "fixup_a64_ldst64_tprel_lo12_nc",  0,    32,             0 },
165{ "fixup_a64_tlsdesc_adr_page",      0,    32, MCFixupKindInfo::FKF_IsPCRel },
166{ "fixup_a64_tlsdesc_ld64_lo12_nc",  0,    32,             0 },
167{ "fixup_a64_tlsdesc_add_lo12_nc",   0,    32,             0 },
168{ "fixup_a64_tlsdesc_call",          0,     0,             0 }
169    };
170    if (Kind < FirstTargetFixupKind)
171      return MCAsmBackend::getFixupKindInfo(Kind);
172
173    assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
174           "Invalid kind!");
175    return Infos[Kind - FirstTargetFixupKind];
176  }
177
178  void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize,
179                  uint64_t Value) const {
180    unsigned NumBytes = getFixupKindInfo(Fixup.getKind()).TargetSize / 8;
181    Value = adjustFixupValue(Fixup.getKind(), Value);
182    if (!Value) return;           // Doesn't change encoding.
183
184    unsigned Offset = Fixup.getOffset();
185    assert(Offset + NumBytes <= DataSize && "Invalid fixup offset!");
186
187    // For each byte of the fragment that the fixup touches, mask in the bits
188    // from the fixup value.
189    for (unsigned i = 0; i != NumBytes; ++i) {
190      Data[Offset + i] |= uint8_t((Value >> (i * 8)) & 0xff);
191    }
192  }
193
194  bool mayNeedRelaxation(const MCInst&) const {
195    return false;
196  }
197
198  void relaxInstruction(const MCInst&, llvm::MCInst&) const {
199    llvm_unreachable("Cannot relax instructions");
200  }
201
202  MCObjectWriter *createObjectWriter(raw_ostream &OS) const {
203    return createAArch64ELFObjectWriter(OS, OSABI);
204  }
205};
206
207} // end anonymous namespace
208
209bool
210ELFAArch64AsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
211                                           uint64_t Value,
212                                           const MCRelaxableFragment *DF,
213                                           const MCAsmLayout &Layout) const {
214  // Correct for now. With all instructions 32-bit only very low-level
215  // considerations could make you select something which may fail.
216  return false;
217}
218
219
220bool AArch64AsmBackend::writeNopData(uint64_t Count, MCObjectWriter *OW) const {
221  // Can't emit NOP with size not multiple of 32-bits
222  if (Count % 4 != 0)
223    return false;
224
225  uint64_t NumNops = Count / 4;
226  for (uint64_t i = 0; i != NumNops; ++i)
227    OW->Write32(0xd503201f);
228
229  return true;
230}
231
232static unsigned ADRImmBits(unsigned Value) {
233  unsigned lo2 = Value & 0x3;
234  unsigned hi19 = (Value & 0x1fffff) >> 2;
235
236  return (hi19 << 5) | (lo2 << 29);
237}
238
239static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) {
240  switch (Kind) {
241  default:
242    llvm_unreachable("Unknown fixup kind!");
243  case FK_Data_2:
244    assert((int64_t)Value >= -32768 &&
245           (int64_t)Value <= 65536 &&
246           "Out of range ABS16 fixup");
247    return Value;
248  case FK_Data_4:
249    assert((int64_t)Value >= -(1LL << 31) &&
250           (int64_t)Value <= (1LL << 32) - 1 &&
251           "Out of range ABS32 fixup");
252    return Value;
253  case FK_Data_8:
254    return Value;
255
256  case AArch64::fixup_a64_ld_gottprel_prel19:
257    // R_AARCH64_LD_GOTTPREL_PREL19: Set a load-literal immediate to bits 1F
258    // FFFC of G(TPREL(S+A)) - P; check -2^20 <= X < 2^20.
259  case AArch64::fixup_a64_ld_prel:
260    // R_AARCH64_LD_PREL_LO19: Sets a load-literal (immediate) value to bits
261    // 1F FFFC of S+A-P, checking that -2^20 <= S+A-P < 2^20.
262    assert((int64_t)Value >= -(1LL << 20) &&
263           (int64_t)Value < (1LL << 20) && "Out of range LDR (lit) fixup");
264    return (Value & 0x1ffffc) << 3;
265
266  case AArch64::fixup_a64_adr_prel:
267    // R_AARCH64_ADR_PREL_LO21: Sets an ADR immediate value to bits 1F FFFF of
268    // the result of S+A-P, checking that -2^20 <= S+A-P < 2^20.
269    assert((int64_t)Value >= -(1LL << 20) &&
270           (int64_t)Value < (1LL << 20) && "Out of range ADR fixup");
271    return ADRImmBits(Value & 0x1fffff);
272
273  case AArch64::fixup_a64_adr_prel_page:
274    // R_AARCH64_ADR_PREL_PG_HI21: Sets an ADRP immediate value to bits 1 FFFF
275    // F000 of the result of the operation, checking that -2^32 <= result <
276    // 2^32.
277    assert((int64_t)Value >= -(1LL << 32) &&
278           (int64_t)Value < (1LL << 32) && "Out of range ADRP fixup");
279    return ADRImmBits((Value & 0x1fffff000ULL) >> 12);
280
281  case AArch64::fixup_a64_add_dtprel_hi12:
282    // R_AARCH64_TLSLD_ADD_DTPREL_LO12: Set an ADD immediate field to bits
283    // FF F000 of DTPREL(S+A), check 0 <= X < 2^24.
284  case AArch64::fixup_a64_add_tprel_hi12:
285    // R_AARCH64_TLSLD_ADD_TPREL_LO12: Set an ADD immediate field to bits
286    // FF F000 of TPREL(S+A), check 0 <= X < 2^24.
287    assert((int64_t)Value >= 0 &&
288           (int64_t)Value < (1LL << 24) && "Out of range ADD fixup");
289    return (Value & 0xfff000) >> 2;
290
291  case AArch64::fixup_a64_add_dtprel_lo12:
292    // R_AARCH64_TLSLD_ADD_DTPREL_LO12: Set an ADD immediate field to bits
293    // FFF of DTPREL(S+A), check 0 <= X < 2^12.
294  case AArch64::fixup_a64_add_tprel_lo12:
295    // R_AARCH64_TLSLD_ADD_TPREL_LO12: Set an ADD immediate field to bits
296    // FFF of TPREL(S+A), check 0 <= X < 2^12.
297    assert((int64_t)Value >= 0 &&
298           (int64_t)Value < (1LL << 12) && "Out of range ADD fixup");
299    // ... fallthrough to no-checking versions ...
300  case AArch64::fixup_a64_add_dtprel_lo12_nc:
301    // R_AARCH64_TLSLD_ADD_DTPREL_LO12_NC: Set an ADD immediate field to bits
302    // FFF of DTPREL(S+A) with no overflow check.
303  case AArch64::fixup_a64_add_tprel_lo12_nc:
304    // R_AARCH64_TLSLD_ADD_TPREL_LO12_NC: Set an ADD immediate field to bits
305    // FFF of TPREL(S+A) with no overflow check.
306  case AArch64::fixup_a64_tlsdesc_add_lo12_nc:
307    // R_AARCH64_TLSDESC_ADD_LO12_NC: Set an ADD immediate field to bits
308    // FFF of G(TLSDESC(S+A)), with no overflow check.
309  case AArch64::fixup_a64_add_lo12:
310    // R_AARCH64_ADD_ABS_LO12_NC: Sets an ADD immediate value to bits FFF of
311    // S+A, with no overflow check.
312    return (Value & 0xfff) << 10;
313
314  case AArch64::fixup_a64_ldst8_dtprel_lo12:
315    // R_AARCH64_TLSLD_LDST8_DTPREL_LO12: Set an LD/ST offset field to bits FFF
316    // of DTPREL(S+A), check 0 <= X < 2^12.
317  case AArch64::fixup_a64_ldst8_tprel_lo12:
318    // R_AARCH64_TLSLE_LDST8_TPREL_LO12: Set an LD/ST offset field to bits FFF
319    // of DTPREL(S+A), check 0 <= X < 2^12.
320    assert((int64_t) Value >= 0 &&
321           (int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
322    // ... fallthrough to no-checking versions ...
323  case AArch64::fixup_a64_ldst8_dtprel_lo12_nc:
324    // R_AARCH64_TLSLD_LDST8_DTPREL_LO12: Set an LD/ST offset field to bits FFF
325    // of DTPREL(S+A), with no overflow check.
326  case AArch64::fixup_a64_ldst8_tprel_lo12_nc:
327    // R_AARCH64_TLSLD_LDST8_TPREL_LO12: Set an LD/ST offset field to bits FFF
328    // of TPREL(S+A), with no overflow check.
329  case AArch64::fixup_a64_ldst8_lo12:
330    // R_AARCH64_LDST8_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFF
331    // of S+A, with no overflow check.
332    return (Value & 0xfff) << 10;
333
334  case AArch64::fixup_a64_ldst16_dtprel_lo12:
335    // R_AARCH64_TLSLD_LDST16_DTPREL_LO12: Set an LD/ST offset field to bits FFE
336    // of DTPREL(S+A), check 0 <= X < 2^12.
337  case AArch64::fixup_a64_ldst16_tprel_lo12:
338    // R_AARCH64_TLSLE_LDST16_TPREL_LO12: Set an LD/ST offset field to bits FFE
339    // of DTPREL(S+A), check 0 <= X < 2^12.
340    assert((int64_t) Value >= 0 &&
341           (int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
342    // ... fallthrough to no-checking versions ...
343  case AArch64::fixup_a64_ldst16_dtprel_lo12_nc:
344    // R_AARCH64_TLSLD_LDST16_DTPREL_LO12: Set an LD/ST offset field to bits FFE
345    // of DTPREL(S+A), with no overflow check.
346  case AArch64::fixup_a64_ldst16_tprel_lo12_nc:
347    // R_AARCH64_TLSLD_LDST16_TPREL_LO12: Set an LD/ST offset field to bits FFE
348    // of TPREL(S+A), with no overflow check.
349  case AArch64::fixup_a64_ldst16_lo12:
350    // R_AARCH64_LDST16_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFE
351    // of S+A, with no overflow check.
352    return (Value & 0xffe) << 9;
353
354  case AArch64::fixup_a64_ldst32_dtprel_lo12:
355    // R_AARCH64_TLSLD_LDST32_DTPREL_LO12: Set an LD/ST offset field to bits FFC
356    // of DTPREL(S+A), check 0 <= X < 2^12.
357  case AArch64::fixup_a64_ldst32_tprel_lo12:
358    // R_AARCH64_TLSLE_LDST32_TPREL_LO12: Set an LD/ST offset field to bits FFC
359    // of DTPREL(S+A), check 0 <= X < 2^12.
360    assert((int64_t) Value >= 0 &&
361           (int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
362    // ... fallthrough to no-checking versions ...
363  case AArch64::fixup_a64_ldst32_dtprel_lo12_nc:
364    // R_AARCH64_TLSLD_LDST32_DTPREL_LO12: Set an LD/ST offset field to bits FFC
365    // of DTPREL(S+A), with no overflow check.
366  case AArch64::fixup_a64_ldst32_tprel_lo12_nc:
367    // R_AARCH64_TLSLD_LDST32_TPREL_LO12: Set an LD/ST offset field to bits FFC
368    // of TPREL(S+A), with no overflow check.
369  case AArch64::fixup_a64_ldst32_lo12:
370    // R_AARCH64_LDST32_ABS_LO12_NC: Sets an LD/ST immediate value to bits FFC
371    // of S+A, with no overflow check.
372    return (Value & 0xffc) << 8;
373
374  case AArch64::fixup_a64_ldst64_dtprel_lo12:
375    // R_AARCH64_TLSLD_LDST64_DTPREL_LO12: Set an LD/ST offset field to bits FF8
376    // of DTPREL(S+A), check 0 <= X < 2^12.
377  case AArch64::fixup_a64_ldst64_tprel_lo12:
378    // R_AARCH64_TLSLE_LDST64_TPREL_LO12: Set an LD/ST offset field to bits FF8
379    // of DTPREL(S+A), check 0 <= X < 2^12.
380    assert((int64_t) Value >= 0 &&
381           (int64_t) Value < (1LL << 12) && "Out of range LD/ST fixup");
382    // ... fallthrough to no-checking versions ...
383  case AArch64::fixup_a64_ldst64_dtprel_lo12_nc:
384    // R_AARCH64_TLSLD_LDST64_DTPREL_LO12: Set an LD/ST offset field to bits FF8
385    // of DTPREL(S+A), with no overflow check.
386  case AArch64::fixup_a64_ldst64_tprel_lo12_nc:
387    // R_AARCH64_TLSLD_LDST64_TPREL_LO12: Set an LD/ST offset field to bits FF8
388    // of TPREL(S+A), with no overflow check.
389  case AArch64::fixup_a64_ldst64_lo12:
390    // R_AARCH64_LDST64_ABS_LO12_NC: Sets an LD/ST immediate value to bits FF8
391    // of S+A, with no overflow check.
392    return (Value & 0xff8) << 7;
393
394  case AArch64::fixup_a64_ldst128_lo12:
395    // R_AARCH64_LDST128_ABS_LO12_NC: Sets an LD/ST immediate value to bits FF0
396    // of S+A, with no overflow check.
397    return (Value & 0xff0) << 6;
398
399  case AArch64::fixup_a64_movw_uabs_g0:
400    // R_AARCH64_MOVW_UABS_G0: Sets a MOVZ immediate field to bits FFFF of S+A
401    // with a check that S+A < 2^16
402    assert(Value <= 0xffff && "Out of range move wide fixup");
403    return (Value & 0xffff) << 5;
404
405  case AArch64::fixup_a64_movw_dtprel_g0_nc:
406    // R_AARCH64_TLSLD_MOVW_DTPREL_G0_NC: Sets a MOVK immediate field to bits
407    // FFFF of DTPREL(S+A) with no overflow check.
408  case AArch64::fixup_a64_movw_gottprel_g0_nc:
409    // R_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC: Sets a MOVK immediate field to bits
410    // FFFF of G(TPREL(S+A)) - GOT with no overflow check.
411  case AArch64::fixup_a64_movw_tprel_g0_nc:
412    // R_AARCH64_TLSLE_MOVW_TPREL_G0_NC: Sets a MOVK immediate field to bits
413    // FFFF of TPREL(S+A) with no overflow check.
414  case AArch64::fixup_a64_movw_uabs_g0_nc:
415    // R_AARCH64_MOVW_UABS_G0_NC: Sets a MOVK immediate field to bits FFFF of
416    // S+A with no overflow check.
417    return (Value & 0xffff) << 5;
418
419  case AArch64::fixup_a64_movw_uabs_g1:
420    // R_AARCH64_MOVW_UABS_G1: Sets a MOVZ immediate field to bits FFFF0000 of
421    // S+A with a check that S+A < 2^32
422    assert(Value <= 0xffffffffull && "Out of range move wide fixup");
423    return ((Value >> 16) & 0xffff) << 5;
424
425  case AArch64::fixup_a64_movw_dtprel_g1_nc:
426    // R_AARCH64_TLSLD_MOVW_DTPREL_G1_NC: Set a MOVK immediate field
427    // to bits FFFF0000 of DTPREL(S+A), with no overflow check.
428  case AArch64::fixup_a64_movw_tprel_g1_nc:
429    // R_AARCH64_TLSLD_MOVW_TPREL_G1_NC: Set a MOVK immediate field
430    // to bits FFFF0000 of TPREL(S+A), with no overflow check.
431  case AArch64::fixup_a64_movw_uabs_g1_nc:
432    // R_AARCH64_MOVW_UABS_G1_NC: Sets a MOVK immediate field to bits
433    // FFFF0000 of S+A with no overflow check.
434    return ((Value >> 16) & 0xffff) << 5;
435
436  case AArch64::fixup_a64_movw_uabs_g2:
437    // R_AARCH64_MOVW_UABS_G2: Sets a MOVZ immediate field to bits FFFF 0000
438    // 0000 of S+A with a check that S+A < 2^48
439    assert(Value <= 0xffffffffffffull && "Out of range move wide fixup");
440    return ((Value >> 32) & 0xffff) << 5;
441
442  case AArch64::fixup_a64_movw_uabs_g2_nc:
443    // R_AARCH64_MOVW_UABS_G2: Sets a MOVK immediate field to bits FFFF 0000
444    // 0000 of S+A with no overflow check.
445    return ((Value >> 32) & 0xffff) << 5;
446
447  case AArch64::fixup_a64_movw_uabs_g3:
448    // R_AARCH64_MOVW_UABS_G3: Sets a MOVZ immediate field to bits FFFF 0000
449    // 0000 0000 of S+A (no overflow check needed)
450    return ((Value >> 48) & 0xffff) << 5;
451
452  case AArch64::fixup_a64_movw_dtprel_g0:
453    // R_AARCH64_TLSLD_MOVW_DTPREL_G0: Set a MOV[NZ] immediate field
454    // to bits FFFF of DTPREL(S+A).
455  case AArch64::fixup_a64_movw_tprel_g0:
456    // R_AARCH64_TLSLE_MOVW_TPREL_G0: Set a MOV[NZ] immediate field to
457    // bits FFFF of TPREL(S+A).
458  case AArch64::fixup_a64_movw_sabs_g0: {
459    // R_AARCH64_MOVW_SABS_G0: Sets MOV[NZ] immediate field using bits FFFF of
460    // S+A (see notes below); check -2^16 <= S+A < 2^16. (notes say that we
461    // should convert between MOVN and MOVZ to achieve our goals).
462    int64_t Signed = Value;
463    assert(Signed >= -(1LL << 16) && Signed < (1LL << 16)
464           && "Out of range move wide fixup");
465    if (Signed >= 0) {
466      Value = (Value & 0xffff) << 5;
467      // Bit 30 converts the MOVN encoding into a MOVZ
468      Value |= 1 << 30;
469    } else {
470      // MCCodeEmitter should have encoded a MOVN, which is fine.
471      Value = (~Value & 0xffff) << 5;
472    }
473    return Value;
474  }
475
476  case AArch64::fixup_a64_movw_dtprel_g1:
477    // R_AARCH64_TLSLD_MOVW_DTPREL_G1: Set a MOV[NZ] immediate field
478    // to bits FFFF0000 of DTPREL(S+A).
479  case AArch64::fixup_a64_movw_gottprel_g1:
480    // R_AARCH64_TLSIE_MOVW_GOTTPREL_G1: Set a MOV[NZ] immediate field
481    // to bits FFFF0000 of G(TPREL(S+A)) - GOT.
482  case AArch64::fixup_a64_movw_tprel_g1:
483    // R_AARCH64_TLSLE_MOVW_TPREL_G1: Set a MOV[NZ] immediate field to
484    // bits FFFF0000 of TPREL(S+A).
485  case AArch64::fixup_a64_movw_sabs_g1: {
486    // R_AARCH64_MOVW_SABS_G1: Sets MOV[NZ] immediate field using bits FFFF 0000
487    // of S+A (see notes below); check -2^32 <= S+A < 2^32. (notes say that we
488    // should convert between MOVN and MOVZ to achieve our goals).
489    int64_t Signed = Value;
490    assert(Signed >= -(1LL << 32) && Signed < (1LL << 32)
491           && "Out of range move wide fixup");
492    if (Signed >= 0) {
493      Value = ((Value >> 16) & 0xffff) << 5;
494      // Bit 30 converts the MOVN encoding into a MOVZ
495      Value |= 1 << 30;
496    } else {
497      Value = ((~Value >> 16) & 0xffff) << 5;
498    }
499    return Value;
500  }
501
502  case AArch64::fixup_a64_movw_dtprel_g2:
503    // R_AARCH64_TLSLD_MOVW_DTPREL_G2: Set a MOV[NZ] immediate field
504    // to bits FFFF 0000 0000 of DTPREL(S+A).
505  case AArch64::fixup_a64_movw_tprel_g2:
506    // R_AARCH64_TLSLE_MOVW_TPREL_G2: Set a MOV[NZ] immediate field to
507    // bits FFFF 0000 0000 of TPREL(S+A).
508  case AArch64::fixup_a64_movw_sabs_g2: {
509    // R_AARCH64_MOVW_SABS_G2: Sets MOV[NZ] immediate field using bits FFFF 0000
510    // 0000 of S+A (see notes below); check -2^48 <= S+A < 2^48. (notes say that
511    // we should convert between MOVN and MOVZ to achieve our goals).
512    int64_t Signed = Value;
513    assert(Signed >= -(1LL << 48) && Signed < (1LL << 48)
514           && "Out of range move wide fixup");
515    if (Signed >= 0) {
516      Value = ((Value >> 32) & 0xffff) << 5;
517      // Bit 30 converts the MOVN encoding into a MOVZ
518      Value |= 1 << 30;
519    } else {
520      Value = ((~Value >> 32) & 0xffff) << 5;
521    }
522    return Value;
523  }
524
525  case AArch64::fixup_a64_tstbr:
526    // R_AARCH64_TSTBR14: Sets the immediate field of a TBZ/TBNZ instruction to
527    // bits FFFC of S+A-P, checking -2^15 <= S+A-P < 2^15.
528    assert((int64_t)Value >= -(1LL << 15) &&
529           (int64_t)Value < (1LL << 15) && "Out of range TBZ/TBNZ fixup");
530    return (Value & 0xfffc) << (5 - 2);
531
532  case AArch64::fixup_a64_condbr:
533    // R_AARCH64_CONDBR19: Sets the immediate field of a conditional branch
534    // instruction to bits 1FFFFC of S+A-P, checking -2^20 <= S+A-P < 2^20.
535    assert((int64_t)Value >= -(1LL << 20) &&
536           (int64_t)Value < (1LL << 20) && "Out of range B.cond fixup");
537    return (Value & 0x1ffffc) << (5 - 2);
538
539  case AArch64::fixup_a64_uncondbr:
540    // R_AARCH64_JUMP26 same as below (except to a linker, possibly).
541  case AArch64::fixup_a64_call:
542    // R_AARCH64_CALL26: Sets a CALL immediate field to bits FFFFFFC of S+A-P,
543    // checking that -2^27 <= S+A-P < 2^27.
544    assert((int64_t)Value >= -(1LL << 27) &&
545           (int64_t)Value < (1LL << 27) && "Out of range branch fixup");
546    return (Value & 0xffffffc) >> 2;
547
548  case AArch64::fixup_a64_adr_gottprel_page:
549    // R_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21: Set an ADRP immediate field to bits
550    // 1FFFFF000 of Page(G(TPREL(S+A))) - Page(P); check -2^32 <= X < 2^32.
551  case AArch64::fixup_a64_tlsdesc_adr_page:
552    // R_AARCH64_TLSDESC_ADR_PAGE: Set an ADRP immediate field to bits 1FFFFF000
553    // of Page(G(TLSDESC(S+A))) - Page(P); check -2^32 <= X < 2^32.
554  case AArch64::fixup_a64_adr_prel_got_page:
555    // R_AARCH64_ADR_GOT_PAGE: Sets the immediate value of an ADRP to bits
556    // 1FFFFF000 of the operation, checking that -2^32 < Page(G(S))-Page(GOT) <
557    // 2^32.
558    assert((int64_t)Value >= -(1LL << 32) &&
559           (int64_t)Value < (1LL << 32) && "Out of range ADRP fixup");
560    return ADRImmBits((Value & 0x1fffff000ULL) >> 12);
561
562  case AArch64::fixup_a64_ld64_gottprel_lo12_nc:
563    // R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC: Set an LD offset field to bits FF8
564    // of X, with no overflow check. Check that X & 7 == 0.
565  case AArch64::fixup_a64_tlsdesc_ld64_lo12_nc:
566    // R_AARCH64_TLSDESC_LD64_LO12_NC: Set an LD offset field to bits FF8 of
567    // G(TLSDESC(S+A)), with no overflow check. Check that X & 7 == 0.
568  case AArch64::fixup_a64_ld64_got_lo12_nc:
569    // R_AARCH64_LD64_GOT_LO12_NC: Sets the LD/ST immediate field to bits FF8 of
570    // G(S) with no overflow check. Check X & 7 == 0
571    assert(((int64_t)Value & 7) == 0 && "Misaligned fixup");
572    return (Value & 0xff8) << 7;
573
574  case AArch64::fixup_a64_tlsdesc_call:
575    // R_AARCH64_TLSDESC_CALL: For relaxation only.
576    return 0;
577  }
578}
579
580MCAsmBackend *
581llvm::createAArch64AsmBackend(const Target &T, StringRef TT, StringRef CPU) {
582  Triple TheTriple(TT);
583
584  return new ELFAArch64AsmBackend(T, TT, TheTriple.getOS());
585}
586