Thumb2SizeReduction.cpp revision 7503fcb890155ac1b62542550c7248db4df890f8
1//===-- Thumb2SizeReduction.cpp - Thumb2 code size reduction pass -*- C++ -*-=// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9 10#define DEBUG_TYPE "t2-reduce-size" 11#include "ARM.h" 12#include "ARMAddressingModes.h" 13#include "ARMBaseRegisterInfo.h" 14#include "ARMBaseInstrInfo.h" 15#include "Thumb2InstrInfo.h" 16#include "llvm/CodeGen/MachineInstr.h" 17#include "llvm/CodeGen/MachineInstrBuilder.h" 18#include "llvm/CodeGen/MachineFunctionPass.h" 19#include "llvm/Support/CommandLine.h" 20#include "llvm/Support/Debug.h" 21#include "llvm/Support/raw_ostream.h" 22#include "llvm/ADT/DenseMap.h" 23#include "llvm/ADT/Statistic.h" 24using namespace llvm; 25 26STATISTIC(NumNarrows, "Number of 32-bit instrs reduced to 16-bit ones"); 27STATISTIC(Num2Addrs, "Number of 32-bit instrs reduced to 2addr 16-bit ones"); 28STATISTIC(NumLdSts, "Number of 32-bit load / store reduced to 16-bit ones"); 29 30static cl::opt<int> ReduceLimit("t2-reduce-limit", 31 cl::init(-1), cl::Hidden); 32static cl::opt<int> ReduceLimit2Addr("t2-reduce-limit2", 33 cl::init(-1), cl::Hidden); 34static cl::opt<int> ReduceLimitLdSt("t2-reduce-limit3", 35 cl::init(-1), cl::Hidden); 36 37namespace { 38 /// ReduceTable - A static table with information on mapping from wide 39 /// opcodes to narrow 40 struct ReduceEntry { 41 unsigned WideOpc; // Wide opcode 42 unsigned NarrowOpc1; // Narrow opcode to transform to 43 unsigned NarrowOpc2; // Narrow opcode when it's two-address 44 uint8_t Imm1Limit; // Limit of immediate field (bits) 45 uint8_t Imm2Limit; // Limit of immediate field when it's two-address 46 unsigned LowRegs1 : 1; // Only possible if low-registers are used 47 unsigned LowRegs2 : 1; // Only possible if low-registers are used (2addr) 48 unsigned PredCC1 : 2; // 0 - If predicated, cc is on and vice versa. 49 // 1 - No cc field. 50 // 2 - Always set CPSR. 51 unsigned PredCC2 : 2; 52 unsigned Special : 1; // Needs to be dealt with specially 53 }; 54 55 static const ReduceEntry ReduceTable[] = { 56 // Wide, Narrow1, Narrow2, imm1,imm2, lo1, lo2, P/C, S 57 { ARM::t2ADCrr, 0, ARM::tADC, 0, 0, 0, 1, 0,0, 0 }, 58 { ARM::t2ADDri, ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 0,0, 0 }, 59 { ARM::t2ADDrr, ARM::tADDrr, ARM::tADDhirr, 0, 0, 1, 0, 0,1, 0 }, 60 // Note: immediate scale is 4. 61 { ARM::t2ADDrSPi,ARM::tADDrSPi,0, 8, 0, 1, 0, 1,0, 1 }, 62 { ARM::t2ADDSri,ARM::tADDi3, ARM::tADDi8, 3, 8, 1, 1, 2,2, 1 }, 63 { ARM::t2ADDSrr,ARM::tADDrr, 0, 0, 0, 1, 0, 2,0, 1 }, 64 { ARM::t2ANDrr, 0, ARM::tAND, 0, 0, 0, 1, 0,0, 0 }, 65 { ARM::t2ASRri, ARM::tASRri, 0, 5, 0, 1, 0, 0,0, 0 }, 66 { ARM::t2ASRrr, 0, ARM::tASRrr, 0, 0, 0, 1, 0,0, 0 }, 67 { ARM::t2BICrr, 0, ARM::tBIC, 0, 0, 0, 1, 0,0, 0 }, 68 //FIXME: Disable CMN, as CCodes are backwards from compare expectations 69 //{ ARM::t2CMNrr, ARM::tCMN, 0, 0, 0, 1, 0, 2,0, 0 }, 70 { ARM::t2CMPri, ARM::tCMPi8, 0, 8, 0, 1, 0, 2,0, 0 }, 71 { ARM::t2CMPrr, ARM::tCMPhir, 0, 0, 0, 0, 0, 2,0, 1 }, 72 { ARM::t2EORrr, 0, ARM::tEOR, 0, 0, 0, 1, 0,0, 0 }, 73 // FIXME: adr.n immediate offset must be multiple of 4. 74 //{ ARM::t2LEApcrelJT,ARM::tLEApcrelJT, 0, 0, 0, 1, 0, 1,0, 0 }, 75 { ARM::t2LSLri, ARM::tLSLri, 0, 5, 0, 1, 0, 0,0, 0 }, 76 { ARM::t2LSLrr, 0, ARM::tLSLrr, 0, 0, 0, 1, 0,0, 0 }, 77 { ARM::t2LSRri, ARM::tLSRri, 0, 5, 0, 1, 0, 0,0, 0 }, 78 { ARM::t2LSRrr, 0, ARM::tLSRrr, 0, 0, 0, 1, 0,0, 0 }, 79 { ARM::t2MOVi, ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 0 }, 80 { ARM::t2MOVi16,ARM::tMOVi8, 0, 8, 0, 1, 0, 0,0, 1 }, 81 // FIXME: Do we need the 16-bit 'S' variant? 82 { ARM::t2MOVr,ARM::tMOVgpr2gpr,0, 0, 0, 0, 0, 1,0, 0 }, 83 { ARM::t2MOVCCr,0, ARM::tMOVCCr, 0, 0, 0, 0, 0,1, 0 }, 84 { ARM::t2MOVCCi,0, ARM::tMOVCCi, 0, 8, 0, 1, 0,1, 0 }, 85 { ARM::t2MUL, 0, ARM::tMUL, 0, 0, 0, 1, 0,0, 0 }, 86 { ARM::t2MVNr, ARM::tMVN, 0, 0, 0, 1, 0, 0,0, 0 }, 87 { ARM::t2ORRrr, 0, ARM::tORR, 0, 0, 0, 1, 0,0, 0 }, 88 { ARM::t2REV, ARM::tREV, 0, 0, 0, 1, 0, 1,0, 0 }, 89 { ARM::t2REV16, ARM::tREV16, 0, 0, 0, 1, 0, 1,0, 0 }, 90 { ARM::t2REVSH, ARM::tREVSH, 0, 0, 0, 1, 0, 1,0, 0 }, 91 { ARM::t2RORrr, 0, ARM::tROR, 0, 0, 0, 1, 0,0, 0 }, 92 { ARM::t2RSBri, ARM::tRSB, 0, 0, 0, 1, 0, 0,0, 1 }, 93 { ARM::t2RSBSri,ARM::tRSB, 0, 0, 0, 1, 0, 2,0, 1 }, 94 { ARM::t2SBCrr, 0, ARM::tSBC, 0, 0, 0, 1, 0,0, 0 }, 95 { ARM::t2SUBri, ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 0,0, 0 }, 96 { ARM::t2SUBrr, ARM::tSUBrr, 0, 0, 0, 1, 0, 0,0, 0 }, 97 { ARM::t2SUBSri,ARM::tSUBi3, ARM::tSUBi8, 3, 8, 1, 1, 2,2, 0 }, 98 { ARM::t2SUBSrr,ARM::tSUBrr, 0, 0, 0, 1, 0, 2,0, 0 }, 99 { ARM::t2SXTBr, ARM::tSXTB, 0, 0, 0, 1, 0, 1,0, 0 }, 100 { ARM::t2SXTHr, ARM::tSXTH, 0, 0, 0, 1, 0, 1,0, 0 }, 101 { ARM::t2TSTrr, ARM::tTST, 0, 0, 0, 1, 0, 2,0, 0 }, 102 { ARM::t2UXTBr, ARM::tUXTB, 0, 0, 0, 1, 0, 1,0, 0 }, 103 { ARM::t2UXTHr, ARM::tUXTH, 0, 0, 0, 1, 0, 1,0, 0 }, 104 105 // FIXME: Clean this up after splitting each Thumb load / store opcode 106 // into multiple ones. 107 { ARM::t2LDRi12,ARM::tLDRi, ARM::tLDRspi, 5, 8, 1, 0, 0,0, 1 }, 108 { ARM::t2LDRs, ARM::tLDRr, 0, 0, 0, 1, 0, 0,0, 1 }, 109 { ARM::t2LDRBi12,ARM::tLDRBi, 0, 5, 0, 1, 0, 0,0, 1 }, 110 { ARM::t2LDRBs, ARM::tLDRBr, 0, 0, 0, 1, 0, 0,0, 1 }, 111 { ARM::t2LDRHi12,ARM::tLDRHi, 0, 5, 0, 1, 0, 0,0, 1 }, 112 { ARM::t2LDRHs, ARM::tLDRHr, 0, 0, 0, 1, 0, 0,0, 1 }, 113 { ARM::t2LDRSBs,ARM::tLDRSB, 0, 0, 0, 1, 0, 0,0, 1 }, 114 { ARM::t2LDRSHs,ARM::tLDRSH, 0, 0, 0, 1, 0, 0,0, 1 }, 115 { ARM::t2STRi12,ARM::tSTRi, ARM::tSTRspi, 5, 8, 1, 0, 0,0, 1 }, 116 { ARM::t2STRs, ARM::tSTRr, 0, 0, 0, 1, 0, 0,0, 1 }, 117 { ARM::t2STRBi12,ARM::tSTRBi, 0, 5, 0, 1, 0, 0,0, 1 }, 118 { ARM::t2STRBs, ARM::tSTRBr, 0, 0, 0, 1, 0, 0,0, 1 }, 119 { ARM::t2STRHi12,ARM::tSTRHi, 0, 5, 0, 1, 0, 0,0, 1 }, 120 { ARM::t2STRHs, ARM::tSTRHr, 0, 0, 0, 1, 0, 0,0, 1 }, 121 122 { ARM::t2LDMIA, ARM::tLDMIA, 0, 0, 0, 1, 1, 1,1, 1 }, 123 { ARM::t2LDMIA_RET,0, ARM::tPOP_RET, 0, 0, 1, 1, 1,1, 1 }, 124 { ARM::t2LDMIA_UPD,ARM::tLDMIA_UPD,ARM::tPOP,0, 0, 1, 1, 1,1, 1 }, 125 // ARM::t2STM (with no basereg writeback) has no Thumb1 equivalent 126 { ARM::t2STMIA_UPD,ARM::tSTMIA_UPD, 0, 0, 0, 1, 1, 1,1, 1 }, 127 { ARM::t2STMDB_UPD, 0, ARM::tPUSH, 0, 0, 1, 1, 1,1, 1 }, 128 }; 129 130 class Thumb2SizeReduce : public MachineFunctionPass { 131 public: 132 static char ID; 133 Thumb2SizeReduce(); 134 135 const Thumb2InstrInfo *TII; 136 137 virtual bool runOnMachineFunction(MachineFunction &MF); 138 139 virtual const char *getPassName() const { 140 return "Thumb2 instruction size reduction pass"; 141 } 142 143 private: 144 /// ReduceOpcodeMap - Maps wide opcode to index of entry in ReduceTable. 145 DenseMap<unsigned, unsigned> ReduceOpcodeMap; 146 147 bool VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry, 148 bool is2Addr, ARMCC::CondCodes Pred, 149 bool LiveCPSR, bool &HasCC, bool &CCDead); 150 151 bool ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, 152 const ReduceEntry &Entry); 153 154 bool ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, 155 const ReduceEntry &Entry, bool LiveCPSR); 156 157 /// ReduceTo2Addr - Reduce a 32-bit instruction to a 16-bit two-address 158 /// instruction. 159 bool ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI, 160 const ReduceEntry &Entry, 161 bool LiveCPSR); 162 163 /// ReduceToNarrow - Reduce a 32-bit instruction to a 16-bit 164 /// non-two-address instruction. 165 bool ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI, 166 const ReduceEntry &Entry, 167 bool LiveCPSR); 168 169 /// ReduceMBB - Reduce width of instructions in the specified basic block. 170 bool ReduceMBB(MachineBasicBlock &MBB); 171 }; 172 char Thumb2SizeReduce::ID = 0; 173} 174 175Thumb2SizeReduce::Thumb2SizeReduce() : MachineFunctionPass(ID) { 176 for (unsigned i = 0, e = array_lengthof(ReduceTable); i != e; ++i) { 177 unsigned FromOpc = ReduceTable[i].WideOpc; 178 if (!ReduceOpcodeMap.insert(std::make_pair(FromOpc, i)).second) 179 assert(false && "Duplicated entries?"); 180 } 181} 182 183static bool HasImplicitCPSRDef(const TargetInstrDesc &TID) { 184 for (const unsigned *Regs = TID.ImplicitDefs; *Regs; ++Regs) 185 if (*Regs == ARM::CPSR) 186 return true; 187 return false; 188} 189 190bool 191Thumb2SizeReduce::VerifyPredAndCC(MachineInstr *MI, const ReduceEntry &Entry, 192 bool is2Addr, ARMCC::CondCodes Pred, 193 bool LiveCPSR, bool &HasCC, bool &CCDead) { 194 if ((is2Addr && Entry.PredCC2 == 0) || 195 (!is2Addr && Entry.PredCC1 == 0)) { 196 if (Pred == ARMCC::AL) { 197 // Not predicated, must set CPSR. 198 if (!HasCC) { 199 // Original instruction was not setting CPSR, but CPSR is not 200 // currently live anyway. It's ok to set it. The CPSR def is 201 // dead though. 202 if (!LiveCPSR) { 203 HasCC = true; 204 CCDead = true; 205 return true; 206 } 207 return false; 208 } 209 } else { 210 // Predicated, must not set CPSR. 211 if (HasCC) 212 return false; 213 } 214 } else if ((is2Addr && Entry.PredCC2 == 2) || 215 (!is2Addr && Entry.PredCC1 == 2)) { 216 /// Old opcode has an optional def of CPSR. 217 if (HasCC) 218 return true; 219 // If old opcode does not implicitly define CPSR, then it's not ok since 220 // these new opcodes' CPSR def is not meant to be thrown away. e.g. CMP. 221 if (!HasImplicitCPSRDef(MI->getDesc())) 222 return false; 223 HasCC = true; 224 } else { 225 // 16-bit instruction does not set CPSR. 226 if (HasCC) 227 return false; 228 } 229 230 return true; 231} 232 233static bool VerifyLowRegs(MachineInstr *MI) { 234 unsigned Opc = MI->getOpcode(); 235 bool isPCOk = (Opc == ARM::t2LDMIA_RET || Opc == ARM::t2LDMIA || 236 Opc == ARM::t2LDMDB || Opc == ARM::t2LDMIA_UPD || 237 Opc == ARM::t2LDMDB_UPD); 238 bool isLROk = (Opc == ARM::t2STMIA_UPD || Opc == ARM::t2STMDB_UPD); 239 bool isSPOk = isPCOk || isLROk || (Opc == ARM::t2ADDrSPi); 240 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) { 241 const MachineOperand &MO = MI->getOperand(i); 242 if (!MO.isReg() || MO.isImplicit()) 243 continue; 244 unsigned Reg = MO.getReg(); 245 if (Reg == 0 || Reg == ARM::CPSR) 246 continue; 247 if (isPCOk && Reg == ARM::PC) 248 continue; 249 if (isLROk && Reg == ARM::LR) 250 continue; 251 if (Reg == ARM::SP) { 252 if (isSPOk) 253 continue; 254 if (i == 1 && (Opc == ARM::t2LDRi12 || Opc == ARM::t2STRi12)) 255 // Special case for these ldr / str with sp as base register. 256 continue; 257 } 258 if (!isARMLowRegister(Reg)) 259 return false; 260 } 261 return true; 262} 263 264bool 265Thumb2SizeReduce::ReduceLoadStore(MachineBasicBlock &MBB, MachineInstr *MI, 266 const ReduceEntry &Entry) { 267 if (ReduceLimitLdSt != -1 && ((int)NumLdSts >= ReduceLimitLdSt)) 268 return false; 269 270 unsigned Scale = 1; 271 bool HasImmOffset = false; 272 bool HasShift = false; 273 bool HasOffReg = true; 274 bool isLdStMul = false; 275 unsigned Opc = Entry.NarrowOpc1; 276 unsigned OpNum = 3; // First 'rest' of operands. 277 uint8_t ImmLimit = Entry.Imm1Limit; 278 279 switch (Entry.WideOpc) { 280 default: 281 llvm_unreachable("Unexpected Thumb2 load / store opcode!"); 282 case ARM::t2LDRi12: 283 case ARM::t2STRi12: 284 if (MI->getOperand(1).getReg() == ARM::SP) { 285 Opc = Entry.NarrowOpc2; 286 ImmLimit = Entry.Imm2Limit; 287 HasOffReg = false; 288 } 289 290 Scale = 4; 291 HasImmOffset = true; 292 HasOffReg = false; 293 break; 294 case ARM::t2LDRBi12: 295 case ARM::t2STRBi12: 296 HasImmOffset = true; 297 HasOffReg = false; 298 break; 299 case ARM::t2LDRHi12: 300 case ARM::t2STRHi12: 301 Scale = 2; 302 HasImmOffset = true; 303 HasOffReg = false; 304 break; 305 case ARM::t2LDRs: 306 case ARM::t2LDRBs: 307 case ARM::t2LDRHs: 308 case ARM::t2LDRSBs: 309 case ARM::t2LDRSHs: 310 case ARM::t2STRs: 311 case ARM::t2STRBs: 312 case ARM::t2STRHs: 313 HasShift = true; 314 OpNum = 4; 315 break; 316 case ARM::t2LDMIA: 317 case ARM::t2LDMDB: { 318 unsigned BaseReg = MI->getOperand(0).getReg(); 319 if (!isARMLowRegister(BaseReg) || Entry.WideOpc != ARM::t2LDMIA) 320 return false; 321 322 // For the non-writeback version (this one), the base register must be 323 // one of the registers being loaded. 324 bool isOK = false; 325 for (unsigned i = 4; i < MI->getNumOperands(); ++i) { 326 if (MI->getOperand(i).getReg() == BaseReg) { 327 isOK = true; 328 break; 329 } 330 } 331 332 if (!isOK) 333 return false; 334 335 OpNum = 0; 336 isLdStMul = true; 337 break; 338 } 339 case ARM::t2LDMIA_RET: { 340 unsigned BaseReg = MI->getOperand(1).getReg(); 341 if (BaseReg != ARM::SP) 342 return false; 343 Opc = Entry.NarrowOpc2; // tPOP_RET 344 OpNum = 2; 345 isLdStMul = true; 346 break; 347 } 348 case ARM::t2LDMIA_UPD: 349 case ARM::t2LDMDB_UPD: 350 case ARM::t2STMIA_UPD: 351 case ARM::t2STMDB_UPD: { 352 OpNum = 0; 353 354 unsigned BaseReg = MI->getOperand(1).getReg(); 355 if (BaseReg == ARM::SP && 356 (Entry.WideOpc == ARM::t2LDMIA_UPD || 357 Entry.WideOpc == ARM::t2STMDB_UPD)) { 358 Opc = Entry.NarrowOpc2; // tPOP or tPUSH 359 OpNum = 2; 360 } else if (!isARMLowRegister(BaseReg) || 361 (Entry.WideOpc != ARM::t2LDMIA_UPD && 362 Entry.WideOpc != ARM::t2STMIA_UPD)) { 363 return false; 364 } 365 366 isLdStMul = true; 367 break; 368 } 369 } 370 371 unsigned OffsetReg = 0; 372 bool OffsetKill = false; 373 if (HasShift) { 374 OffsetReg = MI->getOperand(2).getReg(); 375 OffsetKill = MI->getOperand(2).isKill(); 376 377 if (MI->getOperand(3).getImm()) 378 // Thumb1 addressing mode doesn't support shift. 379 return false; 380 } 381 382 unsigned OffsetImm = 0; 383 if (HasImmOffset) { 384 OffsetImm = MI->getOperand(2).getImm(); 385 unsigned MaxOffset = ((1 << ImmLimit) - 1) * Scale; 386 387 if ((OffsetImm & (Scale - 1)) || OffsetImm > MaxOffset) 388 // Make sure the immediate field fits. 389 return false; 390 } 391 392 // Add the 16-bit load / store instruction. 393 DebugLoc dl = MI->getDebugLoc(); 394 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, TII->get(Opc)); 395 if (!isLdStMul) { 396 MIB.addOperand(MI->getOperand(0)); 397 MIB.addOperand(MI->getOperand(1)); 398 399 if (HasImmOffset) 400 MIB.addImm(OffsetImm / Scale); 401 402 assert((!HasShift || OffsetReg) && "Invalid so_reg load / store address!"); 403 404 if (HasOffReg) 405 MIB.addReg(OffsetReg, getKillRegState(OffsetKill)); 406 } 407 408 // Transfer the rest of operands. 409 for (unsigned e = MI->getNumOperands(); OpNum != e; ++OpNum) 410 MIB.addOperand(MI->getOperand(OpNum)); 411 412 // Transfer memoperands. 413 (*MIB).setMemRefs(MI->memoperands_begin(), MI->memoperands_end()); 414 415 // Transfer MI flags. 416 MIB.setMIFlags(MI->getFlags()); 417 418 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); 419 420 MBB.erase(MI); 421 ++NumLdSts; 422 return true; 423} 424 425bool 426Thumb2SizeReduce::ReduceSpecial(MachineBasicBlock &MBB, MachineInstr *MI, 427 const ReduceEntry &Entry, 428 bool LiveCPSR) { 429 if (Entry.LowRegs1 && !VerifyLowRegs(MI)) 430 return false; 431 432 const TargetInstrDesc &TID = MI->getDesc(); 433 if (TID.mayLoad() || TID.mayStore()) 434 return ReduceLoadStore(MBB, MI, Entry); 435 436 unsigned Opc = MI->getOpcode(); 437 switch (Opc) { 438 default: break; 439 case ARM::t2ADDSri: 440 case ARM::t2ADDSrr: { 441 unsigned PredReg = 0; 442 if (getInstrPredicate(MI, PredReg) == ARMCC::AL) { 443 switch (Opc) { 444 default: break; 445 case ARM::t2ADDSri: { 446 if (ReduceTo2Addr(MBB, MI, Entry, LiveCPSR)) 447 return true; 448 // fallthrough 449 } 450 case ARM::t2ADDSrr: 451 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR); 452 } 453 } 454 break; 455 } 456 case ARM::t2RSBri: 457 case ARM::t2RSBSri: 458 if (MI->getOperand(2).getImm() == 0) 459 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR); 460 break; 461 case ARM::t2MOVi16: 462 // Can convert only 'pure' immediate operands, not immediates obtained as 463 // globals' addresses. 464 if (MI->getOperand(1).isImm()) 465 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR); 466 break; 467 case ARM::t2CMPrr: { 468 // Try to reduce to the lo-reg only version first. Why there are two 469 // versions of the instruction is a mystery. 470 // It would be nice to just have two entries in the master table that 471 // are prioritized, but the table assumes a unique entry for each 472 // source insn opcode. So for now, we hack a local entry record to use. 473 static const ReduceEntry NarrowEntry = 474 { ARM::t2CMPrr,ARM::tCMPr, 0, 0, 0, 1, 1,2, 0, 1 }; 475 if (ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR)) 476 return true; 477 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR); 478 } 479 case ARM::t2ADDrSPi: { 480 static const ReduceEntry NarrowEntry = 481 { ARM::t2ADDrSPi,ARM::tADDspi, 0, 7, 0, 1, 0, 1, 0, 1 }; 482 if (MI->getOperand(0).getReg() == ARM::SP) 483 return ReduceToNarrow(MBB, MI, NarrowEntry, LiveCPSR); 484 return ReduceToNarrow(MBB, MI, Entry, LiveCPSR); 485 } 486 } 487 return false; 488} 489 490bool 491Thumb2SizeReduce::ReduceTo2Addr(MachineBasicBlock &MBB, MachineInstr *MI, 492 const ReduceEntry &Entry, 493 bool LiveCPSR) { 494 495 if (ReduceLimit2Addr != -1 && ((int)Num2Addrs >= ReduceLimit2Addr)) 496 return false; 497 498 unsigned Reg0 = MI->getOperand(0).getReg(); 499 unsigned Reg1 = MI->getOperand(1).getReg(); 500 if (Reg0 != Reg1) { 501 // Try to commute the operands to make it a 2-address instruction. 502 unsigned CommOpIdx1, CommOpIdx2; 503 if (!TII->findCommutedOpIndices(MI, CommOpIdx1, CommOpIdx2) || 504 CommOpIdx1 != 1 || MI->getOperand(CommOpIdx2).getReg() != Reg0) 505 return false; 506 MachineInstr *CommutedMI = TII->commuteInstruction(MI); 507 if (!CommutedMI) 508 return false; 509 } 510 if (Entry.LowRegs2 && !isARMLowRegister(Reg0)) 511 return false; 512 if (Entry.Imm2Limit) { 513 unsigned Imm = MI->getOperand(2).getImm(); 514 unsigned Limit = (1 << Entry.Imm2Limit) - 1; 515 if (Imm > Limit) 516 return false; 517 } else { 518 unsigned Reg2 = MI->getOperand(2).getReg(); 519 if (Entry.LowRegs2 && !isARMLowRegister(Reg2)) 520 return false; 521 } 522 523 // Check if it's possible / necessary to transfer the predicate. 524 const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc2); 525 unsigned PredReg = 0; 526 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 527 bool SkipPred = false; 528 if (Pred != ARMCC::AL) { 529 if (!NewTID.isPredicable()) 530 // Can't transfer predicate, fail. 531 return false; 532 } else { 533 SkipPred = !NewTID.isPredicable(); 534 } 535 536 bool HasCC = false; 537 bool CCDead = false; 538 const TargetInstrDesc &TID = MI->getDesc(); 539 if (TID.hasOptionalDef()) { 540 unsigned NumOps = TID.getNumOperands(); 541 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); 542 if (HasCC && MI->getOperand(NumOps-1).isDead()) 543 CCDead = true; 544 } 545 if (!VerifyPredAndCC(MI, Entry, true, Pred, LiveCPSR, HasCC, CCDead)) 546 return false; 547 548 // Add the 16-bit instruction. 549 DebugLoc dl = MI->getDebugLoc(); 550 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID); 551 MIB.addOperand(MI->getOperand(0)); 552 if (NewTID.hasOptionalDef()) { 553 if (HasCC) 554 AddDefaultT1CC(MIB, CCDead); 555 else 556 AddNoT1CC(MIB); 557 } 558 559 // Transfer the rest of operands. 560 unsigned NumOps = TID.getNumOperands(); 561 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 562 if (i < NumOps && TID.OpInfo[i].isOptionalDef()) 563 continue; 564 if (SkipPred && TID.OpInfo[i].isPredicate()) 565 continue; 566 MIB.addOperand(MI->getOperand(i)); 567 } 568 569 // Transfer MI flags. 570 MIB.setMIFlags(MI->getFlags()); 571 572 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); 573 574 MBB.erase(MI); 575 ++Num2Addrs; 576 return true; 577} 578 579bool 580Thumb2SizeReduce::ReduceToNarrow(MachineBasicBlock &MBB, MachineInstr *MI, 581 const ReduceEntry &Entry, 582 bool LiveCPSR) { 583 if (ReduceLimit != -1 && ((int)NumNarrows >= ReduceLimit)) 584 return false; 585 586 unsigned Limit = ~0U; 587 unsigned Scale = (Entry.WideOpc == ARM::t2ADDrSPi) ? 4 : 1; 588 if (Entry.Imm1Limit) 589 Limit = ((1 << Entry.Imm1Limit) - 1) * Scale; 590 591 const TargetInstrDesc &TID = MI->getDesc(); 592 for (unsigned i = 0, e = TID.getNumOperands(); i != e; ++i) { 593 if (TID.OpInfo[i].isPredicate()) 594 continue; 595 const MachineOperand &MO = MI->getOperand(i); 596 if (MO.isReg()) { 597 unsigned Reg = MO.getReg(); 598 if (!Reg || Reg == ARM::CPSR) 599 continue; 600 if (Entry.WideOpc == ARM::t2ADDrSPi && Reg == ARM::SP) 601 continue; 602 if (Entry.LowRegs1 && !isARMLowRegister(Reg)) 603 return false; 604 } else if (MO.isImm() && 605 !TID.OpInfo[i].isPredicate()) { 606 if (((unsigned)MO.getImm()) > Limit || (MO.getImm() & (Scale-1)) != 0) 607 return false; 608 } 609 } 610 611 // Check if it's possible / necessary to transfer the predicate. 612 const TargetInstrDesc &NewTID = TII->get(Entry.NarrowOpc1); 613 unsigned PredReg = 0; 614 ARMCC::CondCodes Pred = getInstrPredicate(MI, PredReg); 615 bool SkipPred = false; 616 if (Pred != ARMCC::AL) { 617 if (!NewTID.isPredicable()) 618 // Can't transfer predicate, fail. 619 return false; 620 } else { 621 SkipPred = !NewTID.isPredicable(); 622 } 623 624 bool HasCC = false; 625 bool CCDead = false; 626 if (TID.hasOptionalDef()) { 627 unsigned NumOps = TID.getNumOperands(); 628 HasCC = (MI->getOperand(NumOps-1).getReg() == ARM::CPSR); 629 if (HasCC && MI->getOperand(NumOps-1).isDead()) 630 CCDead = true; 631 } 632 if (!VerifyPredAndCC(MI, Entry, false, Pred, LiveCPSR, HasCC, CCDead)) 633 return false; 634 635 // Add the 16-bit instruction. 636 DebugLoc dl = MI->getDebugLoc(); 637 MachineInstrBuilder MIB = BuildMI(MBB, *MI, dl, NewTID); 638 MIB.addOperand(MI->getOperand(0)); 639 if (NewTID.hasOptionalDef()) { 640 if (HasCC) 641 AddDefaultT1CC(MIB, CCDead); 642 else 643 AddNoT1CC(MIB); 644 } 645 646 // Transfer the rest of operands. 647 unsigned NumOps = TID.getNumOperands(); 648 for (unsigned i = 1, e = MI->getNumOperands(); i != e; ++i) { 649 if (i < NumOps && TID.OpInfo[i].isOptionalDef()) 650 continue; 651 if ((TID.getOpcode() == ARM::t2RSBSri || 652 TID.getOpcode() == ARM::t2RSBri) && i == 2) 653 // Skip the zero immediate operand, it's now implicit. 654 continue; 655 bool isPred = (i < NumOps && TID.OpInfo[i].isPredicate()); 656 if (SkipPred && isPred) 657 continue; 658 const MachineOperand &MO = MI->getOperand(i); 659 if (Scale > 1 && !isPred && MO.isImm()) 660 MIB.addImm(MO.getImm() / Scale); 661 else { 662 if (MO.isReg() && MO.isImplicit() && MO.getReg() == ARM::CPSR) 663 // Skip implicit def of CPSR. Either it's modeled as an optional 664 // def now or it's already an implicit def on the new instruction. 665 continue; 666 MIB.addOperand(MO); 667 } 668 } 669 if (!TID.isPredicable() && NewTID.isPredicable()) 670 AddDefaultPred(MIB); 671 672 // Transfer MI flags. 673 MIB.setMIFlags(MI->getFlags()); 674 675 DEBUG(errs() << "Converted 32-bit: " << *MI << " to 16-bit: " << *MIB); 676 677 MBB.erase(MI); 678 ++NumNarrows; 679 return true; 680} 681 682static bool UpdateCPSRDef(MachineInstr &MI, bool LiveCPSR) { 683 bool HasDef = false; 684 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 685 const MachineOperand &MO = MI.getOperand(i); 686 if (!MO.isReg() || MO.isUndef() || MO.isUse()) 687 continue; 688 if (MO.getReg() != ARM::CPSR) 689 continue; 690 if (!MO.isDead()) 691 HasDef = true; 692 } 693 694 return HasDef || LiveCPSR; 695} 696 697static bool UpdateCPSRUse(MachineInstr &MI, bool LiveCPSR) { 698 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) { 699 const MachineOperand &MO = MI.getOperand(i); 700 if (!MO.isReg() || MO.isUndef() || MO.isDef()) 701 continue; 702 if (MO.getReg() != ARM::CPSR) 703 continue; 704 assert(LiveCPSR && "CPSR liveness tracking is wrong!"); 705 if (MO.isKill()) { 706 LiveCPSR = false; 707 break; 708 } 709 } 710 711 return LiveCPSR; 712} 713 714bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB) { 715 bool Modified = false; 716 717 // Yes, CPSR could be livein. 718 bool LiveCPSR = MBB.isLiveIn(ARM::CPSR); 719 720 MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end(); 721 MachineBasicBlock::iterator NextMII; 722 for (; MII != E; MII = NextMII) { 723 NextMII = llvm::next(MII); 724 725 MachineInstr *MI = &*MII; 726 LiveCPSR = UpdateCPSRUse(*MI, LiveCPSR); 727 728 unsigned Opcode = MI->getOpcode(); 729 DenseMap<unsigned, unsigned>::iterator OPI = ReduceOpcodeMap.find(Opcode); 730 if (OPI != ReduceOpcodeMap.end()) { 731 const ReduceEntry &Entry = ReduceTable[OPI->second]; 732 // Ignore "special" cases for now. 733 if (Entry.Special) { 734 if (ReduceSpecial(MBB, MI, Entry, LiveCPSR)) { 735 Modified = true; 736 MachineBasicBlock::iterator I = prior(NextMII); 737 MI = &*I; 738 } 739 goto ProcessNext; 740 } 741 742 // Try to transform to a 16-bit two-address instruction. 743 if (Entry.NarrowOpc2 && ReduceTo2Addr(MBB, MI, Entry, LiveCPSR)) { 744 Modified = true; 745 MachineBasicBlock::iterator I = prior(NextMII); 746 MI = &*I; 747 goto ProcessNext; 748 } 749 750 // Try to transform to a 16-bit non-two-address instruction. 751 if (Entry.NarrowOpc1 && ReduceToNarrow(MBB, MI, Entry, LiveCPSR)) { 752 Modified = true; 753 MachineBasicBlock::iterator I = prior(NextMII); 754 MI = &*I; 755 } 756 } 757 758 ProcessNext: 759 LiveCPSR = UpdateCPSRDef(*MI, LiveCPSR); 760 } 761 762 return Modified; 763} 764 765bool Thumb2SizeReduce::runOnMachineFunction(MachineFunction &MF) { 766 const TargetMachine &TM = MF.getTarget(); 767 TII = static_cast<const Thumb2InstrInfo*>(TM.getInstrInfo()); 768 769 bool Modified = false; 770 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I) 771 Modified |= ReduceMBB(*I); 772 return Modified; 773} 774 775/// createThumb2SizeReductionPass - Returns an instance of the Thumb2 size 776/// reduction pass. 777FunctionPass *llvm::createThumb2SizeReductionPass() { 778 return new Thumb2SizeReduce(); 779} 780