History log of /external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
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7fba6cd3d0a9565e86f50bd3d6ac403eadbcb00c 08-Apr-2013 Benjamin Kramer <benny.kra@googlemail.com> ARM: Remove unused variable.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
ee27cac9fac622d3198d4a53130f04653ad09d37 04-Apr-2013 Jakob Stoklund Olesen <stoklund@2pi.dk> Avoid high-latency false CPSR dependencies even for tMOVSi.

The Thumb2SizeReduction pass avoids false CPSR dependencies, except it
still aggressively creates tMOVi8 instructions because they are so
common.

Avoid creating false CPSR dependencies even for tMOVi8 instructions when
the the CPSR flags are known to have high latency. This allows integer
computation to overlap floating point computations.

Also process blocks in a reverse post-order and propagate high-latency
flags to successors.

<rdar://problem/13468102>

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
0b8c9a80f20772c3793201ab5b251d3520b9cea3 02-Jan-2013 Chandler Carruth <chandlerc@gmail.com> Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
58a2cbef4aac9ee7d530dfb690c78d6fc11a2371 02-Jan-2013 Chandler Carruth <chandlerc@gmail.com> Resort the #include lines in include/... and lib/... with the
utils/sort_includes.py script.

Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
831737d329a727f53a1fb0572f7b7a8127208881 30-Dec-2012 Bill Wendling <isanbard@gmail.com> Remove the Function::getFnAttributes method in favor of using the AttributeSet
directly.

This is in preparation for removing the use of the 'Attribute' class as a
collection of attributes. That will shift to the AttributeSet class instead.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
139e407d526193017d42473c8d4892933de78f14 20-Dec-2012 Evan Cheng <evan.cheng@apple.com> On some ARM cpus, flags setting movs with shifter operand, i.e. lsl, lsr, asr,
are more expensive than the non-flag setting variant. Teach thumb2 size
reduction pass to avoid generating them unless we are optimizing for size.

rdar://12892707


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
034b94b17006f51722886b0f2283fb6fb19aca1f 19-Dec-2012 Bill Wendling <isanbard@gmail.com> Rename the 'Attributes' class to 'Attribute'. It's going to represent a single attribute in the future.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
b519351b87204966d6548b198b88f2ab0f4d0b4b 18-Dec-2012 Quentin Colombet <qcolombet@apple.com> Disable ARM partial flag dependency optimization at -Oz

To not over constrain the scheduler for ARM in thumb mode, some optimizations for code size reduction, specific to ARM thumb, are blocked when they add a dependency (like write after read dependency).

Disables this check when code size is the priority, i.e., code is compiled with -Oz.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
bcc9a89c16269cead71ba1f7063a8fb83fb8f57f 18-Dec-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Repair bundles that were broken by removing and reinserting the first
instruction.

This isn't strictly necessary at the moment because Thumb2SizeReduction
also copies all MI flags from the old instruction to the new. However, a
future patch will make that kind of direct flag tampering illegal.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
8413d2c70fe9c6b6edc1037c4bab3c42fe4b0f5d 18-Dec-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Extract a method, no functional change intended.

Sadly, this costs us a perfectly good opportunity to use 'goto'.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
d04a8d4b33ff316ca4cf961e06c9e312eff8e64f 03-Dec-2012 Chandler Carruth <chandlerc@gmail.com> Use the new script to sort the includes of every file under lib.

Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
cff9baa95273bc279bf5fadb9e27afbd25cca20b 28-Aug-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Revert r162713: "Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM."

This wasn't the right way to enforce ordering of atomics.

We are already setting the isVolatile bit on memory operands of atomic
operations which is good enough to enforce the correct ordering.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
dd364419ee64cd5bb234af006ce0cb285e4a84ca 28-Aug-2012 Jakob Stoklund Olesen <stoklund@2pi.dk> Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.

It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.

Atomic loads are also prevented from participating in rematerialization
and load folding.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
2c7e5c714c8675f757c4936a3a2132c2466a626c 04-May-2012 Sebastian Pop <spop@codeaurora.org> Added missing CMN case in Thumb2SizeReduction pass so that LLVM emits 16-bits encoding of CMN instructions.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
d4f020a3af325630973df8d3a084d0b0e3b68ebc 07-Apr-2012 Jim Grosbach <grosbach@apple.com> Tidy up. 80 columns.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
b78ca423844f19f4a838abb49b4b4fa7ae499707 11-Mar-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t to store registers and opcode in static tables in the target specific backends.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
fac259814923d091942b230e7bd002a8d1130bc3 08-Mar-2012 Craig Topper <craig.topper@gmail.com> Use uint16_t to store instruction implicit uses and defs. Reduces static data.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
d1b220a33b16d97ef4194b4da625ba1c57974dee 24-Feb-2012 Jim Grosbach <grosbach@apple.com> Make sure the regs are low regs for tMUL size reduction.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
fdf7c850321bba542e181ae035507d9c71d95364 24-Feb-2012 Jim Grosbach <grosbach@apple.com> Thumb2 size reduction fix for tied operands of tMUL.

The tied source operand of tMUL is the second source operand, not the
first like every other two-address thumb instruction. Special case it
in the size reduction pass to make sure we create the tMUL instruction
properly.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
b16db8171970f7390895f1e36d5887e6baa9abc3 17-Dec-2011 Evan Cheng <evan.cheng@apple.com> Fix a CPSR liveness tracking bug introduced when I converted IT block to bundle.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
ddfd1377d2e4154d44dc3ad217735adc15af2e3f 14-Dec-2011 Evan Cheng <evan.cheng@apple.com> - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
prevent IT blocks from being broken apart.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
5a96b3dad2f634c9081c8b2b6c2575441dc5a2bd 07-Dec-2011 Evan Cheng <evan.cheng@apple.com> Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
824a70a384988aebbe3b46254a3631e81a8f0690 27-Oct-2011 Evan Cheng <evan.cheng@apple.com> Avoid partial CPSR dependency from loop backedges. rdar://10357570

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
5b81584f7403ffdb9cc6babaaeb0411c080e0f81 24-Aug-2011 Jim Grosbach <grosbach@apple.com> Thumb1 ADD/SUB SP instructions are predicable in Thumb2 mode.

Add the predicate operand to the instructions. Update the back end
accordingly where the instructions are used. Restrict the SP operands
to actually only be SP, as otherwise these break assembly parsing for the
normal instruction variants.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
c5a8c861c9f008d777f5da6a77c253fea2bfe2f1 27-Jul-2011 Jim Grosbach <grosbach@apple.com> ARM extend instructions simplification.

Refactor the SXTB, SXTH, SXTB16, UXTB, UXTH, and UXTB16 instructions to not
have an 'r' and an 'r_rot' version, but just a single version with a rotate
that can be zero. Use plain Pat<>'s for the ISel of the non-rotated version.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
ee04a6d3a40c3017124e3fd89a0db473a2824498 21-Jul-2011 Evan Cheng <evan.cheng@apple.com> Sink ARMMCExpr and ARMAddressingModes into MC layer. First step to separate ARM MC code from target.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
eb03c3b22861e5fb6459aa055378e852df29b621 01-Jul-2011 Jim Grosbach <grosbach@apple.com> Fix off-by-one error.

(low two bits always zero, so off by one bit of encoded value).

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
efeedceb41cc0c5ff7918cad870d5820de84b03d 01-Jul-2011 Jim Grosbach <grosbach@apple.com> Pseudo-ize t2MOVCC[ri].

t2MOVCC[ri] are just t2MOV[ri] instructions, so properly pseudo-ize them.
The Thumb1 versions, tMOVCC[ri] were only present for use by the size-
reduction pass, so they're no longer necessary at all and can be deleted.



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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
2a7b41ba4d3eb3c6003f6768dc20b28d83eac265 01-Jul-2011 Jim Grosbach <grosbach@apple.com> Refact ARM Thumb1 tMOVr instruction family.

Merge the tMOVr, tMOVgpr2tgpr, tMOVtgpr2gpr, and tMOVgpr2gpr instructions
into tMOVr. There's no need to keep them separate. Giving the tMOVr
instruction the proper GPR register class for its operands is sufficient
to give the register allocator enough information to do the right thing
directly.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
41ca4b7b62fc40b3207eff0526171653605efa19 30-Jun-2011 Jim Grosbach <grosbach@apple.com> Size reducing SP adjusting t2ADDri needs to check predication.

tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the
predicate is anything other than "always."



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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
f6fd90910a552ad9883f031350ae517e26dfdb44 30-Jun-2011 Jim Grosbach <grosbach@apple.com> Remove redundant Thumb2 ADD/SUB SP instruction definitions.

Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the
stack pointer. It can just use the normal add-register-immediate encoding
since it can use all registers as a source, not just R0-R7. The extra
instruction definitions are just duplicates of the normal instructions with
the (not well enforced) constraint that the source register was SP.



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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
e837dead3c8dc3445ef6a0e2322179c57e264a13 28-Jun-2011 Evan Cheng <evan.cheng@apple.com> - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo and
sink them into MC layer.
- Added MCInstrInfo, which captures the tablegen generated static data. Chang
TargetInstrInfo so it's based off MCInstrInfo.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
d7d030a44796adc73a6eaa939cd17e52047734c1 29-Apr-2011 Chris Lattner <sabre@nondot.org> use the MachineInstrBuilder operator-> to simplify some code.
There are probably more instances of this floating around.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
5dde893c2bac9e1569c38429f756c1d723e8edf2 19-Apr-2011 Bob Wilson <bob.wilson@apple.com> Avoid some 's' 16-bit instruction which partially update CPSR
(and add false dependency) when it isn't dependent on last CPSR defining
instruction. rdar://8928208

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
7503fcb890155ac1b62542550c7248db4df890f8 05-Mar-2011 Anton Korobeynikov <asl@math.spbu.ru> Handle MI flags inside Thumb2SizeReduction pass.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
971b83b67a9812556cdb97bb58aa96fb37af458d 08-Feb-2011 Owen Anderson <resistor@mac.com> Revert both r121082 (which broke a bunch of constant pool stuff) and r125074 (which worked around it). This should get us back to the old, correct behavior, though it will make the integrated assembler unhappy for the time being.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
75396a998887220074b90f176e29054a35b6c0ed 08-Feb-2011 Evan Cheng <evan.cheng@apple.com> Temporary workaround for a bad bug introduced by r121082 which replaced
t2LDRpci with t2LDRi12.
There are a couple of problems with this.
1. The encoding for the literal and immediate constant are different.
Note bit 7 of the literal case is 'U' so it can be negative.
2. t2LDRi12 is now narrowed to tLDRpci before constant island pass is run.
So we end up never using the Thumb2 instruction, which ends up creating a
lot more constant islands.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
f4caf69720d807573c50d41aa06bcec1c99bdbbd 14-Dec-2010 Bill Wendling <isanbard@gmail.com> The tLDR et al instructions were emitting either a reg/reg or reg/imm
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
97a884d602538705644e296a57a039959cdb6f6e 07-Dec-2010 Jim Grosbach <grosbach@apple.com> Refactor the ARM CMPz* patterns to just use the normal CMP instructions when
possible. They were duplicates for everything exception the source pattern
before.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
eb6779c5b98383e33542207f062102e79263df16 07-Dec-2010 Owen Anderson <resistor@mac.com> Second attempt at converting Thumb2's LDRpci, including updating the gazillion places that need to know about it.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
c24130bade8c348d0d437644b01ebdd3c65e6681 04-Dec-2010 Bob Wilson <bob.wilson@apple.com> The Thumb tADDrSPi instruction is not valid when the destination is SP.
Check for that and try narrowing it to tADDspi instead. Radar 8724703.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
ed09087dd30c3150a228b14fb224a3491dd6af62 04-Dec-2010 Jim Grosbach <grosbach@apple.com> Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.
tCMPzhir has undefined behavior when both source registers are low registers.
rdar://8728577

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
6e572981270cd6485973f3d493e5403514206a57 03-Dec-2010 Jim Grosbach <grosbach@apple.com> Reduce t2 ldr/str instructions to the correct t1 versions when there's an
immediate offset.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
2c971ab9d9a52b3402d708e9a83586f04116a6ac 03-Dec-2010 Jim Grosbach <grosbach@apple.com> Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
73fe34a3ee866867d5028f4a9afa2c3b8efebcba 16-Nov-2010 Bill Wendling <isanbard@gmail.com> Encode the multi-load/store instructions with their respective modes ('ia',
'db', 'ib', 'da') instead of having that mode as a separate field in the
instruction. It's more convenient for the asm parser and much more readable for
humans.
<rdar://problem/8654088>


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
9854f197f3385713c77df8cea0e39a231b91a650 14-Sep-2010 Jim Grosbach <grosbach@apple.com> Clarify comment

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
447e7ac913181ec3eae7c56a73c059df5382c029 08-Sep-2010 Jim Grosbach <grosbach@apple.com> To shrink a t2LDM instruction to the 16-bit wide tLDM instruction, the base
register must be one of the destination registers for the load. Otherwise,
the tLDM instruction will write-back to the base register, which isn't what's
desired (otherwise, we'd have a t2LDM_UPD instead).

rdar://8394087



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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
90c579de5a383cee278acc3f7e7b9d0a656e6a35 06-Aug-2010 Owen Anderson <resistor@mac.com> Reapply r110396, with fixes to appease the Linux buildbot gods.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
1f74590e9d1b9cf0f1f81a156efea73f76546e05 06-Aug-2010 Owen Anderson <resistor@mac.com> Revert r110396 to fix buildbots.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
9ccaf53ada99c63737547c0235baeb8454b04e80 06-Aug-2010 Owen Anderson <resistor@mac.com> Don't use PassInfo* as a type identifier for passes. Instead, use the address of the static
ID member as the sole unique type identifier. Clean up APIs related to this change.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
789fef987f9c3dd14743731e3a6733f2f90c9778 24-Jun-2010 Bob Wilson <bob.wilson@apple.com> PR7458: Try commuting Thumb2 instruction operands to put them into 2-address
form so they can be narrowed to 16-bit instructions.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
b84adb3b80c5b17befffd4f1d31ec5331ddcb792 08-Jun-2010 Jim Grosbach <grosbach@apple.com> fix typo

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
c5e43c958e4a599aef0162cd71f864712b740ab5 13-Apr-2010 Dan Gohman <gohman@apple.com> Use MachineBasicBlock::isLiveIn.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
e17245dbe970faf29af408056f43ee543724d7fc 13-Mar-2010 Benjamin Kramer <benny.kra@googlemail.com> Fix another warning. There is a functionality change but I believe it's correct.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
815baebe1c8dc02accf128ae10dff9a1742d3244 13-Mar-2010 Bob Wilson <bob.wilson@apple.com> Change ARM ld/st multiple instructions to have variant instructions for
writebacks to the address register. This gets rid of the hack that the
first register on the list was the magic writeback register operand. There
was an implicit constraint that if that operand was not reg0 it had to match
the base register operand. The post-RA scheduler's antidependency breaker
did not understand that constraint and sometimes changed one without the
other. This also fixes Radar 7495976 and should help the verifier work
better for ARM code.

There are now new ld/st instructions explicit writeback operands and explicit
constraints that tie those registers together.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
4152778605dcab9e650b2cd03e2d8dc12f20aff6 09-Feb-2010 Jim Grosbach <grosbach@apple.com> Radar 7417921

tMOVCCi pattern only valid for low registers, as the Thumb1 mov immediate to
register instruction only works with low registers. Allowing high registers
for the instruction resulted in the assembler choosing the wide (32-bit)
encoding for the mov, but LLVM though the instruction was only 16 bits wide,
so offset calculations for constant pools became incorrect, leading to
out of range constant pool entries.



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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
d5d2baec2609da3ade9ca205e87c88d35e9e6976 22-Jan-2010 Jim Grosbach <grosbach@apple.com> Fix PR5694. The CMN instructions set the flags differently from CMP, so they
cannot be directly interchanged for comparisons against negated values.
Disable the CMN instructions for the time being.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
7896c9f436a4eda5ec15e882a7505ba482a2fcd0 03-Dec-2009 Chris Lattner <sabre@nondot.org> improve portability to avoid conflicting with std::next in c++'0x.
Patch by Howard Hinnant!


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
5cdc3a949af0cef7f2163f8a7acbf3049c226321 24-Nov-2009 Anton Korobeynikov <asl@math.spbu.ru> Materialize global addresses via movt/movw pair, this is always better
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
5b397c93a50a44e3bfc58bd8fd95357c0cba3f1e 19-Nov-2009 Evan Cheng <evan.cheng@apple.com> Shrink ldr / str [sp, imm0-1024] to 16-bit instructions.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
f5a86f45e75ec744c203270ffa03659eb0a220c1 25-Oct-2009 Nick Lewycky <nicholas@mxc.ca> Remove includes of Support/Compiler.h that are no longer needed after the
VISIBILITY_HIDDEN removal.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
6726b6d75a8b679068a58cb954ba97cf9d1690ba 25-Oct-2009 Nick Lewycky <nicholas@mxc.ca> Remove VISIBILITY_HIDDEN from class/struct found inside anonymous namespaces.
Chris claims we should never have visibility_hidden inside any .cpp file but
that's still not true even after this commit.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
5adb66a646e2ec32265263739f5b01c3f50c176a 28-Sep-2009 Evan Cheng <evan.cheng@apple.com> Make ARM and Thumb2 32-bit immediate materialization into a single 32-bit pseudo
instruction. This makes it re-materializable.

Thumb2 will split it back out into two instructions so IT pass will generate the
right mask. Also, this expose opportunies to optimize the movw to a 16-bit move.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
28d63b169938fa95cf481b64ef6e4bc1849dabef 09-Sep-2009 Evan Cheng <evan.cheng@apple.com> Cast MO.getImm() to unsigned before comparing with an unsigned limit.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
c2d98bc0d682419f09659d94afefd6a6266dd6ee 06-Sep-2009 Duncan Sands <baldrick@free.fr> Remove some not-really-used variables, as warned
about by icc (#593, partial). Patch by Erick Tryzelaar.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
705e07f578e2b3af47ddab610feb4e7f2d3063a5 23-Aug-2009 Chris Lattner <sabre@nondot.org> remove various std::ostream version of printing methods from
MachineInstr and MachineOperand. This required eliminating a
bunch of stuff that was using DOUT, I hope that bill doesn't
mind me stealing his fun. ;-)


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
9ae7d44d95de16be5ed7bea7e1117160d9e2d5ce 16-Aug-2009 Benjamin Kramer <benny.kra@googlemail.com> Fix use after free in Thumb2SizeReduction (PR4707). A MachineInstr was used after erasure.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
bc9b754091ea281e769e487f396b40f6675b9edb 15-Aug-2009 Evan Cheng <evan.cheng@apple.com> Turn on if-conversion for thumb2.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
a1efbbdbf3217598f334a6f39dab84ca06f5de41 14-Aug-2009 Evan Cheng <evan.cheng@apple.com> Shrink ADR and LDR from constantpool late during constantpool island pass.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
3aaccffbce9146aad97929d5812fb6271a7443ef 12-Aug-2009 Evan Cheng <evan.cheng@apple.com> PredCC is meant to be 2 bits wide, like PredCC1.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
007ea274f4ab85bfc7698240eb5afd5a779ec330 12-Aug-2009 Evan Cheng <evan.cheng@apple.com> Shrink Thumb2 movcc instructions.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
05c269c64593d8cc6aeb0780a5a8afbb86da5691 12-Aug-2009 Evan Cheng <evan.cheng@apple.com> Shrink ADDS, ADC, RSB, and SUBS.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
b89030ab6554d84de4331c2853edac4dbf8da9b9 12-Aug-2009 Evan Cheng <evan.cheng@apple.com> Shrinkify Thumb2 r = add sp, imm.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
4b322e58b77d16f103d88a3af3a4ebd2675245a0 11-Aug-2009 Evan Cheng <evan.cheng@apple.com> Shrinkify Thumb2 load / store multiple instructions.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
195c71b472d3f83c1051d2b87f4e93cc928b6ec9 11-Aug-2009 Evan Cheng <evan.cheng@apple.com> Fix the previous accidental commit. Now shrinking common Thumb2 load / store instructions.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
3a21425dbe09c7ac85e6b156f82184dd6132435a 11-Aug-2009 Evan Cheng <evan.cheng@apple.com> Fix Thumb2 load / store addressing mode matching code. Do not use so_reg form to
match base only address, i.e. [r] since Thumb2 requires a offset register field.
For those, use [r + imm12] where the immediate is zero.
Note the generated assembly code does not look any different after the patch.
But the bug would have broken the JIT (if there is Thumb2 support) and it can
break later passes which expect the address mode to be well-formed.


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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
65f2e7887a8b70b3ee63ef535a6bcfe8a170c074 10-Aug-2009 Evan Cheng <evan.cheng@apple.com> Watch out for empty BB.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
8442d00a0ea750200b34a7fa94b5b72033da65b3 10-Aug-2009 Evan Cheng <evan.cheng@apple.com> rev, rev16, and revsh do not set CPSR.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
0d3007bb32c9085e6d45264133248a98379e2d8a 10-Aug-2009 Evan Cheng <evan.cheng@apple.com> Duh. Most 16-bit Thumb rr instructions are two-address. Fix table.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
26cc252a43c20eccbd49ae92dea8b5a1bb02cdc2 10-Aug-2009 Evan Cheng <evan.cheng@apple.com> CPSR can be livein; transfer predicate operands correctly; tMUL is two-address.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
e8af1f9afe5e70e1d4ec4d00a6870428dba88692 10-Aug-2009 Evan Cheng <evan.cheng@apple.com> Add support to reduce most of 32-bit Thumb2 arithmetic instructions.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
a56c57e5f0876e7c47adbdaa59248fee3131d3be 09-Aug-2009 Evan Cheng <evan.cheng@apple.com> Add support to convert 32-bit instructions to 16-bit non-two-address ones.

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/external/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp
3eff16e27a4b0e9dfb8c0061faf10fdce9f4df4e 08-Aug-2009 Evan Cheng <evan.cheng@apple.com> Add a skeleton Thumb2 instruction size reduction pass.

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