PPCInstr64Bit.td revision 25b9bbae69befa03cc48d4be73b741eff8e523bc
1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getImm16Encoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let EncoderMethod = "getImm16Encoding"; 26 let ParserMatchClass = PPCU16ImmAsmOperand; 27} 28def s17imm64 : Operand<i64> { 29 // This operand type is used for addis/lis to allow the assembler parser 30 // to accept immediates in the range -65536..65535 for compatibility with 31 // the GNU assembler. The operand is treated as 16-bit otherwise. 32 let PrintMethod = "printS16ImmOperand"; 33 let EncoderMethod = "getImm16Encoding"; 34 let ParserMatchClass = PPCS17ImmAsmOperand; 35} 36def tocentry : Operand<iPTR> { 37 let MIOperandInfo = (ops i64imm:$imm); 38} 39def tlsreg : Operand<i64> { 40 let EncoderMethod = "getTLSRegEncoding"; 41} 42def tlsgd : Operand<i64> {} 43def tlscall : Operand<i64> { 44 let PrintMethod = "printTLSCall"; 45 let MIOperandInfo = (ops calltarget:$func, tlsgd:$sym); 46 let EncoderMethod = "getTLSCallEncoding"; 47} 48 49//===----------------------------------------------------------------------===// 50// 64-bit transformation functions. 51// 52 53def SHL64 : SDNodeXForm<imm, [{ 54 // Transformation function: 63 - imm 55 return getI32Imm(63 - N->getZExtValue()); 56}]>; 57 58def SRL64 : SDNodeXForm<imm, [{ 59 // Transformation function: 64 - imm 60 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 61}]>; 62 63def HI32_48 : SDNodeXForm<imm, [{ 64 // Transformation function: shift the immediate value down into the low bits. 65 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 66}]>; 67 68def HI48_64 : SDNodeXForm<imm, [{ 69 // Transformation function: shift the immediate value down into the low bits. 70 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 71}]>; 72 73 74//===----------------------------------------------------------------------===// 75// Calls. 76// 77 78let Interpretation64Bit = 1 in { 79let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 80 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 81 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 82 Requires<[In64BitMode]>; 83 84 let isCodeGenOnly = 1 in 85 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 86 "b${cond:cc}ctr${cond:pm} ${cond:reg}", BrB, []>, 87 Requires<[In64BitMode]>; 88 } 89} 90 91let Defs = [LR8] in 92 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 93 PPC970_Unit_BRU; 94 95let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 96 let Defs = [CTR8], Uses = [CTR8] in { 97 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 98 "bdz $dst">; 99 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 100 "bdnz $dst">; 101 } 102 103 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 104 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 105 "bdzlr", BrB, []>; 106 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 107 "bdnzlr", BrB, []>; 108 } 109} 110 111 112 113let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 114 // Convenient aliases for call instructions 115 let Uses = [RM] in { 116 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 117 "bl $func", BrB, []>; // See Pat patterns below. 118 119 def BL8_TLS : IForm<18, 0, 1, (outs), (ins tlscall:$func), 120 "bl $func", BrB, []>; 121 122 def BLA8 : IForm<18, 1, 1, (outs), (ins abscalltarget:$func), 123 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>; 124 } 125 let Uses = [RM], isCodeGenOnly = 1 in { 126 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 127 (outs), (ins calltarget:$func), 128 "bl $func\n\tnop", BrB, []>; 129 130 def BL8_NOP_TLS : IForm_and_DForm_4_zero<18, 0, 1, 24, 131 (outs), (ins tlscall:$func), 132 "bl $func\n\tnop", BrB, []>; 133 134 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 135 (outs), (ins abscalltarget:$func), 136 "bla $func\n\tnop", BrB, 137 [(PPCcall_nop (i64 imm:$func))]>; 138 } 139 let Uses = [CTR8, RM] in { 140 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 141 "bctrl", BrB, [(PPCbctrl)]>, 142 Requires<[In64BitMode]>; 143 144 let isCodeGenOnly = 1 in 145 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 146 "b${cond:cc}ctrl${cond:pm} ${cond:reg}", BrB, []>, 147 Requires<[In64BitMode]>; 148 } 149} 150} // Interpretation64Bit 151 152// Calls 153def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 154 (BL8 tglobaladdr:$dst)>; 155def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 156 (BL8_NOP tglobaladdr:$dst)>; 157 158def : Pat<(PPCcall (i64 texternalsym:$dst)), 159 (BL8 texternalsym:$dst)>; 160def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 161 (BL8_NOP texternalsym:$dst)>; 162 163// Atomic operations 164let usesCustomInserter = 1 in { 165 let Defs = [CR0] in { 166 def ATOMIC_LOAD_ADD_I64 : Pseudo< 167 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 168 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 169 def ATOMIC_LOAD_SUB_I64 : Pseudo< 170 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 171 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 172 def ATOMIC_LOAD_OR_I64 : Pseudo< 173 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 174 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 175 def ATOMIC_LOAD_XOR_I64 : Pseudo< 176 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 177 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 178 def ATOMIC_LOAD_AND_I64 : Pseudo< 179 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 180 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 181 def ATOMIC_LOAD_NAND_I64 : Pseudo< 182 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 183 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 184 185 def ATOMIC_CMP_SWAP_I64 : Pseudo< 186 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 187 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 188 189 def ATOMIC_SWAP_I64 : Pseudo< 190 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 191 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 192 } 193} 194 195// Instructions to support atomic operations 196def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 197 "ldarx $rD, $ptr", LdStLDARX, 198 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>; 199 200let Defs = [CR0] in 201def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 202 "stdcx. $rS, $dst", LdStSTDCX, 203 [(PPCstcx i64:$rS, xoaddr:$dst)]>, 204 isDOT; 205 206let Interpretation64Bit = 1 in { 207let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 208def TCRETURNdi8 :Pseudo< (outs), 209 (ins calltarget:$dst, i32imm:$offset), 210 "#TC_RETURNd8 $dst $offset", 211 []>; 212 213let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 214def TCRETURNai8 :Pseudo<(outs), (ins abscalltarget:$func, i32imm:$offset), 215 "#TC_RETURNa8 $func $offset", 216 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 217 218let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 219def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 220 "#TC_RETURNr8 $dst $offset", 221 []>; 222 223let isCodeGenOnly = 1 in { 224 225let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 226 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 227def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 228 Requires<[In64BitMode]>; 229 230 231let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 232 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 233def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 234 "b $dst", BrB, 235 []>; 236 237 238let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 239 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 240def TAILBA8 : IForm<18, 0, 0, (outs), (ins abscalltarget:$dst), 241 "ba $dst", BrB, 242 []>; 243 244} 245} // Interpretation64Bit 246 247def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 248 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 249 250def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 251 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 252 253def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 254 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 255 256 257// 64-bit CR instructions 258let Interpretation64Bit = 1 in { 259let neverHasSideEffects = 1 in { 260def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins g8rc:$rS), 261 "mtcrf $FXM, $rS", BrMCRX>, 262 PPC970_MicroCode, PPC970_Unit_CRU; 263 264let isCodeGenOnly = 1 in 265def MFCR8pseud: XFXForm_3<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 266 "#MFCR8pseud", SprMFCR>, 267 PPC970_MicroCode, PPC970_Unit_CRU; 268} // neverHasSideEffects = 1 269 270let neverHasSideEffects = 1 in 271def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 272 "mfcr $rT", SprMFCR>, 273 PPC970_MicroCode, PPC970_Unit_CRU; 274 275let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 276 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 277 "#EH_SJLJ_SETJMP64", 278 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 279 Requires<[In64BitMode]>; 280 let isTerminator = 1 in 281 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 282 "#EH_SJLJ_LONGJMP64", 283 [(PPCeh_sjlj_longjmp addr:$buf)]>, 284 Requires<[In64BitMode]>; 285} 286 287//===----------------------------------------------------------------------===// 288// 64-bit SPR manipulation instrs. 289 290let Uses = [CTR8] in { 291def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 292 "mfctr $rT", SprMFSPR>, 293 PPC970_DGroup_First, PPC970_Unit_FXU; 294} 295let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 296def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 297 "mtctr $rS", SprMTSPR>, 298 PPC970_DGroup_First, PPC970_Unit_FXU; 299} 300let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in { 301let Pattern = [(int_ppc_mtctr i64:$rS)] in 302def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 303 "mtctr $rS", SprMTSPR>, 304 PPC970_DGroup_First, PPC970_Unit_FXU; 305} 306 307let Pattern = [(set i64:$rT, readcyclecounter)] in 308def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 309 "mfspr $rT, 268", SprMFTB>, 310 PPC970_DGroup_First, PPC970_Unit_FXU; 311// Note that encoding mftb using mfspr is now the preferred form, 312// and has been since at least ISA v2.03. The mftb instruction has 313// now been phased out. Using mfspr, however, is known not to work on 314// the POWER3. 315 316let Defs = [X1], Uses = [X1] in 317def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 318 [(set i64:$result, 319 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 320 321let Defs = [LR8] in { 322def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 323 "mtlr $rS", SprMTSPR>, 324 PPC970_DGroup_First, PPC970_Unit_FXU; 325} 326let Uses = [LR8] in { 327def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 328 "mflr $rT", SprMFSPR>, 329 PPC970_DGroup_First, PPC970_Unit_FXU; 330} 331} // Interpretation64Bit 332 333//===----------------------------------------------------------------------===// 334// Fixed point instructions. 335// 336 337let PPC970_Unit = 1 in { // FXU Operations. 338let Interpretation64Bit = 1 in { 339let neverHasSideEffects = 1 in { 340 341let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 342def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 343 "li $rD, $imm", IntSimple, 344 [(set i64:$rD, imm64SExt16:$imm)]>; 345def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s17imm64:$imm), 346 "lis $rD, $imm", IntSimple, 347 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 348} 349 350// Logical ops. 351defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 352 "nand", "$rA, $rS, $rB", IntSimple, 353 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 354defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 355 "and", "$rA, $rS, $rB", IntSimple, 356 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 357defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 358 "andc", "$rA, $rS, $rB", IntSimple, 359 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 360defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 361 "or", "$rA, $rS, $rB", IntSimple, 362 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 363defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 364 "nor", "$rA, $rS, $rB", IntSimple, 365 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 366defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 367 "orc", "$rA, $rS, $rB", IntSimple, 368 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 369defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 370 "eqv", "$rA, $rS, $rB", IntSimple, 371 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 372defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 373 "xor", "$rA, $rS, $rB", IntSimple, 374 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 375 376// Logical ops with immediate. 377let Defs = [CR0] in { 378def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 379 "andi. $dst, $src1, $src2", IntGeneral, 380 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 381 isDOT; 382def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 383 "andis. $dst, $src1, $src2", IntGeneral, 384 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 385 isDOT; 386} 387def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 388 "ori $dst, $src1, $src2", IntSimple, 389 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 390def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 391 "oris $dst, $src1, $src2", IntSimple, 392 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 393def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 394 "xori $dst, $src1, $src2", IntSimple, 395 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 396def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 397 "xoris $dst, $src1, $src2", IntSimple, 398 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 399 400defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 401 "add", "$rT, $rA, $rB", IntSimple, 402 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 403// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 404// initial-exec thread-local storage model. 405let isCodeGenOnly = 1 in 406def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 407 "add $rT, $rA, $rB@tls", IntSimple, 408 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 409 410defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 411 "addc", "$rT, $rA, $rB", IntGeneral, 412 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 413 PPC970_DGroup_Cracked; 414let Defs = [CARRY] in 415def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 416 "addic $rD, $rA, $imm", IntGeneral, 417 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 418def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 419 "addi $rD, $rA, $imm", IntSimple, 420 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 421def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s17imm64:$imm), 422 "addis $rD, $rA, $imm", IntSimple, 423 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 424 425let Defs = [CARRY] in { 426def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 427 "subfic $rD, $rA, $imm", IntGeneral, 428 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 429defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 430 "subfc", "$rT, $rA, $rB", IntGeneral, 431 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 432 PPC970_DGroup_Cracked; 433} 434defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 435 "subf", "$rT, $rA, $rB", IntGeneral, 436 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 437defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 438 "neg", "$rT, $rA", IntSimple, 439 [(set i64:$rT, (ineg i64:$rA))]>; 440let Uses = [CARRY] in { 441defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 442 "adde", "$rT, $rA, $rB", IntGeneral, 443 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 444defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 445 "addme", "$rT, $rA", IntGeneral, 446 [(set i64:$rT, (adde i64:$rA, -1))]>; 447defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 448 "addze", "$rT, $rA", IntGeneral, 449 [(set i64:$rT, (adde i64:$rA, 0))]>; 450defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 451 "subfe", "$rT, $rA, $rB", IntGeneral, 452 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 453defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 454 "subfme", "$rT, $rA", IntGeneral, 455 [(set i64:$rT, (sube -1, i64:$rA))]>; 456defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 457 "subfze", "$rT, $rA", IntGeneral, 458 [(set i64:$rT, (sube 0, i64:$rA))]>; 459} 460 461 462defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 463 "mulhd", "$rT, $rA, $rB", IntMulHW, 464 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 465defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 466 "mulhdu", "$rT, $rA, $rB", IntMulHWU, 467 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 468} 469} // Interpretation64Bit 470 471let isCompare = 1, neverHasSideEffects = 1 in { 472 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 473 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 474 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 475 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 476 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm), 477 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 478 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2), 479 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 480} 481 482let neverHasSideEffects = 1 in { 483defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 484 "sld", "$rA, $rS, $rB", IntRotateD, 485 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 486defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 487 "srd", "$rA, $rS, $rB", IntRotateD, 488 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 489defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 490 "srad", "$rA, $rS, $rB", IntRotateD, 491 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 492 493let Interpretation64Bit = 1 in { 494defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 495 "extsb", "$rA, $rS", IntSimple, 496 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 497defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 498 "extsh", "$rA, $rS", IntSimple, 499 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 500} // Interpretation64Bit 501 502defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 503 "extsw", "$rA, $rS", IntSimple, 504 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 505let Interpretation64Bit = 1 in 506defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 507 "extsw", "$rA, $rS", IntSimple, 508 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 509 510defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 511 "sradi", "$rA, $rS, $SH", IntRotateDI, 512 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 513defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 514 "cntlzd", "$rA, $rS", IntGeneral, 515 [(set i64:$rA, (ctlz i64:$rS))]>; 516defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 517 "popcntd", "$rA, $rS", IntGeneral, 518 [(set i64:$rA, (ctpop i64:$rS))]>; 519 520// popcntw also does a population count on the high 32 bits (storing the 521// results in the high 32-bits of the output). We'll ignore that here (which is 522// safe because we never separately use the high part of the 64-bit registers). 523defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS), 524 "popcntw", "$rA, $rS", IntGeneral, 525 [(set i32:$rA, (ctpop i32:$rS))]>; 526 527defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 528 "divd", "$rT, $rA, $rB", IntDivD, 529 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64, 530 PPC970_DGroup_First, PPC970_DGroup_Cracked; 531defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 532 "divdu", "$rT, $rA, $rB", IntDivD, 533 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64, 534 PPC970_DGroup_First, PPC970_DGroup_Cracked; 535defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 536 "mulld", "$rT, $rA, $rB", IntMulHD, 537 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 538} 539 540let neverHasSideEffects = 1 in { 541let isCommutable = 1 in { 542defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 543 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 544 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI, 545 []>, isPPC64, RegConstraint<"$rSi = $rA">, 546 NoEncode<"$rSi">; 547} 548 549// Rotate instructions. 550defm RLDCL : MDSForm_1r<30, 8, 551 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 552 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD, 553 []>, isPPC64; 554defm RLDCR : MDSForm_1r<30, 9, 555 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 556 "rldcr", "$rA, $rS, $rB, $MBE", IntRotateD, 557 []>, isPPC64; 558defm RLDICL : MDForm_1r<30, 0, 559 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 560 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI, 561 []>, isPPC64; 562defm RLDICR : MDForm_1r<30, 1, 563 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 564 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI, 565 []>, isPPC64; 566defm RLDIC : MDForm_1r<30, 2, 567 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 568 "rldic", "$rA, $rS, $SH, $MBE", IntRotateDI, 569 []>, isPPC64; 570 571let Interpretation64Bit = 1 in { 572defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 573 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 574 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral, 575 []>; 576 577let isSelect = 1 in 578def ISEL8 : AForm_4<31, 15, 579 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 580 "isel $rT, $rA, $rB, $cond", IntGeneral, 581 []>; 582} // Interpretation64Bit 583} // neverHasSideEffects = 1 584} // End FXU Operations. 585 586 587//===----------------------------------------------------------------------===// 588// Load/Store instructions. 589// 590 591 592// Sign extending loads. 593let canFoldAsLoad = 1, PPC970_Unit = 2 in { 594let Interpretation64Bit = 1 in 595def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 596 "lha $rD, $src", LdStLHA, 597 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 598 PPC970_DGroup_Cracked; 599def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 600 "lwa $rD, $src", LdStLWA, 601 [(set i64:$rD, 602 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 603 PPC970_DGroup_Cracked; 604let Interpretation64Bit = 1 in 605def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 606 "lhax $rD, $src", LdStLHA, 607 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 608 PPC970_DGroup_Cracked; 609def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 610 "lwax $rD, $src", LdStLHA, 611 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 612 PPC970_DGroup_Cracked; 613 614// Update forms. 615let mayLoad = 1, neverHasSideEffects = 1 in { 616let Interpretation64Bit = 1 in 617def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 618 (ins memri:$addr), 619 "lhau $rD, $addr", LdStLHAU, 620 []>, RegConstraint<"$addr.reg = $ea_result">, 621 NoEncode<"$ea_result">; 622// NO LWAU! 623 624let Interpretation64Bit = 1 in 625def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 626 (ins memrr:$addr), 627 "lhaux $rD, $addr", LdStLHAU, 628 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 629 NoEncode<"$ea_result">; 630def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 631 (ins memrr:$addr), 632 "lwaux $rD, $addr", LdStLHAU, 633 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 634 NoEncode<"$ea_result">, isPPC64; 635} 636} 637 638let Interpretation64Bit = 1 in { 639// Zero extending loads. 640let canFoldAsLoad = 1, PPC970_Unit = 2 in { 641def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 642 "lbz $rD, $src", LdStLoad, 643 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 644def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 645 "lhz $rD, $src", LdStLoad, 646 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 647def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 648 "lwz $rD, $src", LdStLoad, 649 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 650 651def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 652 "lbzx $rD, $src", LdStLoad, 653 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 654def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 655 "lhzx $rD, $src", LdStLoad, 656 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 657def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 658 "lwzx $rD, $src", LdStLoad, 659 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 660 661 662// Update forms. 663let mayLoad = 1, neverHasSideEffects = 1 in { 664def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 665 "lbzu $rD, $addr", LdStLoadUpd, 666 []>, RegConstraint<"$addr.reg = $ea_result">, 667 NoEncode<"$ea_result">; 668def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 669 "lhzu $rD, $addr", LdStLoadUpd, 670 []>, RegConstraint<"$addr.reg = $ea_result">, 671 NoEncode<"$ea_result">; 672def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 673 "lwzu $rD, $addr", LdStLoadUpd, 674 []>, RegConstraint<"$addr.reg = $ea_result">, 675 NoEncode<"$ea_result">; 676 677def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 678 (ins memrr:$addr), 679 "lbzux $rD, $addr", LdStLoadUpd, 680 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 681 NoEncode<"$ea_result">; 682def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 683 (ins memrr:$addr), 684 "lhzux $rD, $addr", LdStLoadUpd, 685 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 686 NoEncode<"$ea_result">; 687def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 688 (ins memrr:$addr), 689 "lwzux $rD, $addr", LdStLoadUpd, 690 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 691 NoEncode<"$ea_result">; 692} 693} 694} // Interpretation64Bit 695 696 697// Full 8-byte loads. 698let canFoldAsLoad = 1, PPC970_Unit = 2 in { 699def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 700 "ld $rD, $src", LdStLD, 701 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 702// The following three definitions are selected for small code model only. 703// Otherwise, we need to create two instructions to form a 32-bit offset, 704// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 705def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 706 "#LDtoc", 707 [(set i64:$rD, 708 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 709def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 710 "#LDtocJTI", 711 [(set i64:$rD, 712 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 713def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 714 "#LDtocCPT", 715 [(set i64:$rD, 716 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 717 718let hasSideEffects = 1, isCodeGenOnly = 1 in { 719let RST = 2, DS = 2 in 720def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), 721 "ld 2, 8($reg)", LdStLD, 722 [(PPCload_toc i64:$reg)]>, isPPC64; 723 724let RST = 2, DS = 10, RA = 1 in 725def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 726 "ld 2, 40(1)", LdStLD, 727 [(PPCtoc_restore)]>, isPPC64; 728} 729def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 730 "ldx $rD, $src", LdStLD, 731 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 732def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 733 "ldbrx $rD, $src", LdStLoad, 734 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 735 736let mayLoad = 1, neverHasSideEffects = 1 in { 737def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 738 "ldu $rD, $addr", LdStLDU, 739 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 740 NoEncode<"$ea_result">; 741 742def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 743 (ins memrr:$addr), 744 "ldux $rD, $addr", LdStLDU, 745 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 746 NoEncode<"$ea_result">, isPPC64; 747} 748} 749 750def : Pat<(PPCload ixaddr:$src), 751 (LD ixaddr:$src)>; 752def : Pat<(PPCload xaddr:$src), 753 (LDX xaddr:$src)>; 754 755// Support for medium and large code model. 756def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 757 "#ADDIStocHA", 758 [(set i64:$rD, 759 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>, 760 isPPC64; 761def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 762 "#LDtocL", 763 [(set i64:$rD, 764 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64; 765def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 766 "#ADDItocL", 767 [(set i64:$rD, 768 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64; 769 770// Support for thread-local storage. 771def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 772 "#ADDISgotTprelHA", 773 [(set i64:$rD, 774 (PPCaddisGotTprelHA i64:$reg, 775 tglobaltlsaddr:$disp))]>, 776 isPPC64; 777def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 778 "#LDgotTprelL", 779 [(set i64:$rD, 780 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 781 isPPC64; 782def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 783 (ADD8TLS $in, tglobaltlsaddr:$g)>; 784def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 785 "#ADDIStlsgdHA", 786 [(set i64:$rD, 787 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 788 isPPC64; 789def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 790 "#ADDItlsgdL", 791 [(set i64:$rD, 792 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 793 isPPC64; 794def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 795 "#GETtlsADDR", 796 [(set i64:$rD, 797 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 798 isPPC64; 799def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 800 "#ADDIStlsldHA", 801 [(set i64:$rD, 802 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 803 isPPC64; 804def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 805 "#ADDItlsldL", 806 [(set i64:$rD, 807 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 808 isPPC64; 809def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 810 "#GETtlsldADDR", 811 [(set i64:$rD, 812 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 813 isPPC64; 814def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 815 "#ADDISdtprelHA", 816 [(set i64:$rD, 817 (PPCaddisDtprelHA i64:$reg, 818 tglobaltlsaddr:$disp))]>, 819 isPPC64; 820def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 821 "#ADDIdtprelL", 822 [(set i64:$rD, 823 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 824 isPPC64; 825 826let PPC970_Unit = 2 in { 827let Interpretation64Bit = 1 in { 828// Truncating stores. 829def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 830 "stb $rS, $src", LdStStore, 831 [(truncstorei8 i64:$rS, iaddr:$src)]>; 832def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 833 "sth $rS, $src", LdStStore, 834 [(truncstorei16 i64:$rS, iaddr:$src)]>; 835def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 836 "stw $rS, $src", LdStStore, 837 [(truncstorei32 i64:$rS, iaddr:$src)]>; 838def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 839 "stbx $rS, $dst", LdStStore, 840 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 841 PPC970_DGroup_Cracked; 842def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 843 "sthx $rS, $dst", LdStStore, 844 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 845 PPC970_DGroup_Cracked; 846def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 847 "stwx $rS, $dst", LdStStore, 848 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 849 PPC970_DGroup_Cracked; 850} // Interpretation64Bit 851 852// Normal 8-byte stores. 853def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 854 "std $rS, $dst", LdStSTD, 855 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 856def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 857 "stdx $rS, $dst", LdStSTD, 858 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 859 PPC970_DGroup_Cracked; 860def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 861 "stdbrx $rS, $dst", LdStStore, 862 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 863 PPC970_DGroup_Cracked; 864} 865 866// Stores with Update (pre-inc). 867let PPC970_Unit = 2, mayStore = 1 in { 868let Interpretation64Bit = 1 in { 869def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 870 "stbu $rS, $dst", LdStStoreUpd, []>, 871 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 872def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 873 "sthu $rS, $dst", LdStStoreUpd, []>, 874 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 875def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 876 "stwu $rS, $dst", LdStStoreUpd, []>, 877 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 878def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 879 "stdu $rS, $dst", LdStSTDU, []>, 880 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 881 isPPC64; 882 883def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 884 "stbux $rS, $dst", LdStStoreUpd, []>, 885 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 886 PPC970_DGroup_Cracked; 887def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 888 "sthux $rS, $dst", LdStStoreUpd, []>, 889 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 890 PPC970_DGroup_Cracked; 891def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 892 "stwux $rS, $dst", LdStStoreUpd, []>, 893 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 894 PPC970_DGroup_Cracked; 895} // Interpretation64Bit 896 897def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 898 "stdux $rS, $dst", LdStSTDU, []>, 899 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 900 PPC970_DGroup_Cracked, isPPC64; 901} 902 903// Patterns to match the pre-inc stores. We can't put the patterns on 904// the instruction definitions directly as ISel wants the address base 905// and offset to be separate operands, not a single complex operand. 906def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 907 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 908def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 909 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 910def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 911 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 912def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 913 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 914 915def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 916 (STBUX8 $rS, $ptrreg, $ptroff)>; 917def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 918 (STHUX8 $rS, $ptrreg, $ptroff)>; 919def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 920 (STWUX8 $rS, $ptrreg, $ptroff)>; 921def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 922 (STDUX $rS, $ptrreg, $ptroff)>; 923 924 925//===----------------------------------------------------------------------===// 926// Floating point instructions. 927// 928 929 930let PPC970_Unit = 3, neverHasSideEffects = 1, 931 Uses = [RM] in { // FPU Operations. 932defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 933 "fcfid", "$frD, $frB", FPGeneral, 934 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 935defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 936 "fctidz", "$frD, $frB", FPGeneral, 937 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 938 939defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 940 "fcfidu", "$frD, $frB", FPGeneral, 941 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 942defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 943 "fcfids", "$frD, $frB", FPGeneral, 944 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 945defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 946 "fcfidus", "$frD, $frB", FPGeneral, 947 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 948defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 949 "fctiduz", "$frD, $frB", FPGeneral, 950 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 951defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 952 "fctiwuz", "$frD, $frB", FPGeneral, 953 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 954} 955 956 957//===----------------------------------------------------------------------===// 958// Instruction Patterns 959// 960 961// Extensions and truncates to/from 32-bit regs. 962def : Pat<(i64 (zext i32:$in)), 963 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 964 0, 32)>; 965def : Pat<(i64 (anyext i32:$in)), 966 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 967def : Pat<(i32 (trunc i64:$in)), 968 (EXTRACT_SUBREG $in, sub_32)>; 969 970// Extending loads with i64 targets. 971def : Pat<(zextloadi1 iaddr:$src), 972 (LBZ8 iaddr:$src)>; 973def : Pat<(zextloadi1 xaddr:$src), 974 (LBZX8 xaddr:$src)>; 975def : Pat<(extloadi1 iaddr:$src), 976 (LBZ8 iaddr:$src)>; 977def : Pat<(extloadi1 xaddr:$src), 978 (LBZX8 xaddr:$src)>; 979def : Pat<(extloadi8 iaddr:$src), 980 (LBZ8 iaddr:$src)>; 981def : Pat<(extloadi8 xaddr:$src), 982 (LBZX8 xaddr:$src)>; 983def : Pat<(extloadi16 iaddr:$src), 984 (LHZ8 iaddr:$src)>; 985def : Pat<(extloadi16 xaddr:$src), 986 (LHZX8 xaddr:$src)>; 987def : Pat<(extloadi32 iaddr:$src), 988 (LWZ8 iaddr:$src)>; 989def : Pat<(extloadi32 xaddr:$src), 990 (LWZX8 xaddr:$src)>; 991 992// Standard shifts. These are represented separately from the real shifts above 993// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 994// amounts. 995def : Pat<(sra i64:$rS, i32:$rB), 996 (SRAD $rS, $rB)>; 997def : Pat<(srl i64:$rS, i32:$rB), 998 (SRD $rS, $rB)>; 999def : Pat<(shl i64:$rS, i32:$rB), 1000 (SLD $rS, $rB)>; 1001 1002// SHL/SRL 1003def : Pat<(shl i64:$in, (i32 imm:$imm)), 1004 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 1005def : Pat<(srl i64:$in, (i32 imm:$imm)), 1006 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 1007 1008// ROTL 1009def : Pat<(rotl i64:$in, i32:$sh), 1010 (RLDCL $in, $sh, 0)>; 1011def : Pat<(rotl i64:$in, (i32 imm:$imm)), 1012 (RLDICL $in, imm:$imm, 0)>; 1013 1014// Hi and Lo for Darwin Global Addresses. 1015def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 1016def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 1017def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 1018def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 1019def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 1020def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1021def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1022def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1023def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1024 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1025def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1026 (ADDI8 $in, tglobaltlsaddr:$g)>; 1027def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1028 (ADDIS8 $in, tglobaladdr:$g)>; 1029def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1030 (ADDIS8 $in, tconstpool:$g)>; 1031def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1032 (ADDIS8 $in, tjumptable:$g)>; 1033def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1034 (ADDIS8 $in, tblockaddress:$g)>; 1035 1036// Patterns to match r+r indexed loads and stores for 1037// addresses without at least 4-byte alignment. 1038def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1039 (LWAX xoaddr:$src)>; 1040def : Pat<(i64 (unaligned4load xoaddr:$src)), 1041 (LDX xoaddr:$src)>; 1042def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1043 (STDX $rS, xoaddr:$dst)>; 1044 1045