| 0e910d2cb5feac287c2a3050c1945a3c4a3d2dd5 |
|
06-Aug-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC64 mulli pattern
The PPC backend had been missing a pattern to generate mulli for 64-bit
multiples. We had been generating it only for 32-bit multiplies. Unfortunately,
generating li + mulld unnecessarily increases register pressure.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187807 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8d7435e9b1319c6e748a06c0b41a4c3de82ec750 |
|
17-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Add CTR-register clobber to builtin setjmp
Because the builtin longjmp implementation uses a CTR-based indirect jump, when
the control flow arrives at the builtin setjmp call, the CTR register has
necessarily been clobbered. Correspondingly, this adds CTR to the list of
implicit definitions of the builtin setjmp pseudo instruction.
We don't need to add CTR to the implicit definitions of builtin longjmp
because, even though it does clobber the CTR register, the control flow cannot
return to inside the loop unless there is also a builtin setjmp call.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186488 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 23a72c8f7e46618ff8dbdbba4e8c1a2c4e44e3df |
|
05-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support @tls in the asm parser
This adds support for the last missing construct to parse TLS-related
assembler code:
add 3, 4, symbol@tls
The ADD8TLS currently hard-codes the @tls into the assembler string.
This cannot be handled by the asm parser, since @tls is parsed as
a symbol variant. This patch changes ADD8TLS to have the @tls suffix
printed as symbol variant on output too, which allows us to remove
the isCodeGenOnly marker from ADD8TLS. This in turn means that we
can add a AsmOperand to accept @tls marked symbols on input.
As a side effect, this means that the fixup_ppc_tlsreg fixup type
is no longer necessary and can be merged into fixup_ppc_nofixup.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185692 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 33efedc0481c4b0d9866ff526eb1161372b5919f |
|
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Use mtocrf when available
Just as with mfocrf, it is also preferable to use mtocrf instead of
mtcrf when only a single CR register is to be written.
Current code however always emits mtcrf. This probably does not matter
when using an external assembler, since the GNU assembler will in fact
automatically replace mtcrf with mtocrf when possible. It does create
inefficient code with the integrated assembler, however.
To fix this, this patch adds MTOCRF/MTOCRF8 instruction patterns and
uses those instead of MTCRF/MTCRF8 everything. Just as done in the
MFOCRF patch committed as 185556, these patterns will be converted
back to MTCRF if MTOCRF is not available on the machine.
As a side effect, this allows to modify the MTCRF pattern to accept
the full range of mask operands for the benefit of the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 965b20e39c7fd73846e9b6ed55ba90e032ae3b1b |
|
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Always use mfocrf if available
When accessing just a single CR register, it is always preferable to
use mfocrf instead of mfcr, if the former is available on the CPU.
Current code makes that distinction in many, but not all places
where a single CR register value is retrieved. One missing
location is PPCRegisterInfo::lowerCRSpilling.
To fix this and make this simpler in the future, this patch changes
the bulk of the back-end to always assume mfocrf is available and
simply generate it when needed.
On machines that actually do not support mfocrf, the instruction
is replaced by mfcr at the very end, in EmitInstruction.
This has the additional benefit that we no longer need the
MFCRpseud hack, since before EmitInstruction we always have
a MFOCRF instruction pattern, which already models data flow
as required.
The patch also adds the MFOCRF8 version of the instruction,
which was missing so far.
Except for the PPCRegisterInfo::lowerCRSpilling case, no change
in generated code intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185556 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 44175d9715268bfb7c2cb10ebf14474f4a411464 |
|
03-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support mtspr/mfspr in the asm parser
This adds support for the generic forms of mtspr/mfspr
for the asm parser. The compiler will continue to use
the specialized patters for mtlr etc. since those are
needed to correctly describe data flow.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185532 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 25b9bbae69befa03cc48d4be73b741eff8e523bc |
|
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] PR16512 - Support TLS call sequences in the asm parser
This patch now adds support for recognizing TLS call sequences in
the asm parser. This needs a new pattern BL8_TLS, which is like
BL8_NOP_TLS except without nop. That pattern is used for the
asm parser only.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| a17a7e1868076a4430cfa16694bcb42884130928 |
|
02-Jul-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Rework TLS call operand processing
As part of the global-dynamic and local-dynamic TLS sequences, we need
to use a special form of the call instruction:
bl __tls_get_addr(sym@tlsld)
bl __tls_get_addr(sym@tlsgd)
which generates two fixups. The current implementation of this causes
problems with recognizing this form in the asm parser. To fix this,
this patch reworks operand processing for this special form by using
a single operand to hold both __tls_get_addr and sym@tlsld and defining
a print method to output the above form, and an encoding method to
generate the two fixups.
As a side simplification, the patch replaces the two instruction
patterns BL8_NOP_TLSGD and BL8_NOP_TLSLD by a single BL8_NOP_TLS,
since the patterns already operate in an identical fashion (whether
we have a local-dynamic or global-dynamic symbol is already encoded
in the symbol modifier).
No change in code generation intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@185477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8950dd127ad4cccd9dadf616b5057cf130f24ade |
|
26-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Accept 17-bit signed immediates for addis
The assembler currently strictly verifies that immediates for
s16imm operands are in range (-32768 ... 32767). This matches
the behaviour of the GNU assembler, with one exception: gas
allows, as a special case, operands in an extended range
(-65536 .. 65535) for the addis instruction only (and its
extended mnemonic lis).
The main reason for this seems to be to allow using unsigned
16-bit operands for lis, e.g. like lis %r1, 0xfedc.
Since this has been supported by gas for a long time, and
assembler source code seen "in the wild" actually exploits
this feature, this patch adds equivalent support to LLVM
for compatibility reasons.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184946 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 0b8594268feb1c804370541c7853e658caee0ae5 |
|
26-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support symbolic u16imm operands
Currently, all instructions taking s16imm operands support symbolic
operands. However, for u16imm operands, we only support actual
immediate integers. This causes the assembler to reject code like
ori %r5, %r5, symbol@l
This patch changes the u16imm operand definition to likewise
accept symbolic operands. In fact, s16imm and u16imm can
share the same encoding routine, now renamed to getImm16Encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 816c06f7fa73e8150e260a11d897be2f52d4f2b8 |
|
25-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add rldcr/rldic instructions
This adds pattern for the rldcr and rldic instructions (the last instruction
from the rotate/shift family that were missing). They are currently used
only by the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184833 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 2e8bd8950345b0857130dd0f4068222a79c103f2 |
|
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add predicted forms of branches
This adds support for the predicted forms of branches (+/-).
There are three cases to consider:
- Branches using a PPC::Predicate code
For these, I've added new PPC::Predicate codes corresponding
to the BO values for predicted branch forms, and updated insn
printing to print them correctly. I've also added new aliases
for the asm parser matching the new forms.
- bt/bf
I've added new aliases matching to gBC etc.
- bd(n)z variants
I've added new instruction patterns for the predicted forms.
In all cases, the new patterns are used for the asm parser only.
(The new infrastructure ought to be sufficient to allow use by
the compiler too at some point.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184754 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 9679c47a07386cbf3547a0927609c7ee080b2aab |
|
24-Jun-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Support absolute branches
There is currently only limited support for the "absolute" variants
of branch instructions. This patch adds support for the absolute
variants of all branches that are currently otherwise supported.
This requires adding new fixup types so that the correct variant
of relocation type can be selected by the object writer.
While the compiler will continue to usually choose the relative
branch variants, this will allow the asm parser to fully support
the absolute branches, with either immediate (numerical) or
symbolic target addresses.
No change in code generation intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184721 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 586f6d009a37d4d38be0badaaa60d7cdb647b442 |
|
24-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Remove symbolLo/symbolHi instruction operand types
Now that there is no longer any distinction between symbolLo
and symbolHi operands in either printing, encoding, or parsing,
the operand types can be removed in favor of simply using
s16imm.
This completes the patch series to decouple lo/hi operand part
processing from the particular instruction whose operand it is.
No change in code generation expected from this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182618 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| edaa58ee66699b99841ee5dfdd485aedbae3bf90 |
|
24-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Clean up generation of ha16() / lo16() markers
When targeting the Darwin assembler, we need to generate markers ha16() and
lo16() to designate the high and low parts of a (symbolic) immediate. This
is necessary not just for plain symbols, but also for certain symbolic
expression, typically along the lines of ha16(A - B). The latter doesn't
work when simply using VariantKind flags on the symbol reference.
This is why the current back-end uses hacks (explicitly called out as such
via multiple FIXMEs) in the symbolLo/symbolHi print methods.
This patch uses target-defined MCExpr codes to represent the Darwin
ha16/lo16 constructs, following along the lines of the equivalent solution
used by the ARM back end to handle their :upper16: / :lower16: markers.
This allows us to get rid of special handling both in the symbolLo/symbolHi
print method and in the common code MCExpr::print routine. Instead, the
ha16 / lo16 markers are printed simply in a custom print routine for the
target MCExpr types. (As a result, the symbolLo/symbolHi print methods
can now replaced by a single printS16ImmOperand routine that also handles
symbolic operands.)
The patch also provides a EvaluateAsRelocatableImpl routine to handle
ha16/lo16 constructs. This is not actually used at the moment by any
in-tree code, but is provided as it makes merging into David Fang's
out-of-tree Mach-O object writer simpler.
Since there is no longer any need to treat VK_PPC_GAS_HA16 and
VK_PPC_DARWIN_HA16 differently, they are merged into a single
VK_PPC_ADDR16_HA (and likewise for the _LO16 types).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182616 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 5cd01f74b11dc3e1c08c3ddea067af8203079b87 |
|
22-May-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Change some PowerPC PatLeaf definitions to ImmLeaf for fast-isel.
Using PatLeaf rather than ImmLeaf when defining immediate predicates
prevents simple patterns using those predicates from being recognized
for fast instruction selection. This patch replaces the immSExt16
PatLeaf predicate with two ImmLeaf predicates, imm32SExt16 and
imm64SExt16, allowing a few more patterns to be recognized (ADDI,
ADDIC, MULLI, ADDI8, and ADDIC8). Using the new predicates does not
help for LI, LI8, SUBFIC, and SUBFIC8 because these are rejected for
other reasons, but I see no reason to retain the PatLeaf predicate.
No functional change intended, and thus no test cases yet. This is
preliminary work for enabling fast-isel support for PowerPC. When
that support is ready, we'll be able to test this function.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 85c08b059ce4248ee739e756cf717a9b429e2ec2 |
|
20-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Rename PPC MTCTRse to MTCTRloop
As the pairing of this instruction form with the bdnz/bdz branches is now
enforced by the verification pass, make it clear from the name that these
are used only for counter-based loops.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182296 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 4456a8ec76bba1148f64bb2707e18b980eda291e |
|
17-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Fix hi/lo encoding in old-style code emitter
This patch implements the equivalent change to r182091/r182092
in the old-style code emitter. Instead of having two separate
16-bit immediate encoding routines depending on the instruction,
this patch introduces a single encoder that checks the machine
operand flags to decide whether the low or high half of a
symbol address is required.
Since now both encoders make no further distinction between
"symbolLo" and "symbolHi", the .td operand can now use a
single getS16ImmEncoding method.
Tested by running the old-style JIT tests on 32-bit Linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182097 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| b1fd3cd78f8acd21dbf514b75fef991827c343b6 |
|
15-May-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement PPC counter loops as a late IR-level pass
The old PPCCTRLoops pass, like the Hexagon pass version from which it was
derived, could only handle some simple loops in canonical form. We cannot
directly adapt the new Hexagon hardware loops pass, however, because the
Hexagon pass contains a fundamental assumption that non-constant-trip-count
loops will contain a guard, and this is not always true (the result being that
incorrect negative counts can be generated). With this commit, we replace the
pass with a late IR-level pass which makes use of SE to calculate the
backedge-taken counts and safely generate the loop-count expressions (including
any necessary max() parts). This IR level pass inserts custom intrinsics that
are lowered into the desired decrement-and-branch instructions.
The most fragile part of this new implementation is that interfering uses of
the counter register must be detected on the IR level (and, on PPC, this also
includes any indirect branches in addition to function calls). Also, to make
all of this work, we need a variant of the mtctr instruction that is marked
as having side effects. Without this, machine-code level CSE, DCE, etc.
illegally transform the resulting code. Hopefully, this can be improved
in the future.
This new pass is smaller than the original (and much smaller than the new
Hexagon hardware loops pass), and can handle many additional cases correctly.
In addition, the preheader-creation code has been copied from LoopSimplify, and
after we decide on where it belongs, this code will be refactored so that it
can be explicitly shared (making this implementation even smaller).
The new test-case files ctrloop-{le,lt,ne}.ll have been adapted from tests for
the new Hexagon pass. There are a few classes of loops that this pass does not
transform (noted by FIXMEs in the files), but these deficiencies can be
addressed within the SE infrastructure (thus helping many other passes as well).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181927 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 5e220753ff81ac5cbee874e7c00c76c7fbe0d20a |
|
03-May-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
[PowerPC] Add assembler parser
This adds assembler parser support to the PowerPC back end.
The parser will run for any powerpc-*-* and powerpc64-*-* triples,
but was tested only on 64-bit Linux. The supported syntax is
intended to be compatible with the GNU assembler.
The parser does not yet support all PowerPC instructions, but
it does support anything that is generated by LLVM itself.
There is no support for testing restricted instruction sets yet,
i.e. the parser will always accept any instructions it knows,
no matter what feature flags are given.
Instruction operands will be checked for validity and errors
generated. (Error handling in general could still be improved.)
The patch adds a number of test cases to verify instruction
and operand encodings. The tests currently cover all instructions
from the following PowerPC ISA v2.06 Book I facilities:
Branch, Fixed-point, Floating-Point, and Vector.
Note that a number of these instructions are not yet supported
by the back end; they are marked with FIXME.
A number of follow-on check-ins will add extra features. When
they are all included, LLVM passes all tests (including bootstrap)
when using clang -cc1as as the system assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| a3acc2b6cf093571812e7e55d936cf188c695e23 |
|
26-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Use RegisterOperand instead of RegisterClass operands
In the default PowerPC assembler syntax, registers are specified simply
by number, so they cannot be distinguished from immediate values (without
looking at the opcode). This means that the default operand matching logic
for the asm parser does not work, and we need to specify custom matchers.
Since those can only be specified with RegisterOperand classes and not
directly on the RegisterClass, all instructions patterns used by the asm
parser need to use a RegisterOperand (instead of a RegisterClass) for
all their register operands.
This patch adds one RegisterOperand for each RegisterClass, using the
same name as the class, just in lower case, and updates all instruction
patterns to use RegisterOperand instead of RegisterClass operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180611 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 1adc97c901e1c42d4f31981a3604d607581c31c3 |
|
26-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Fix encoding of rldimi and rldcl instructions
When testing the asm parser, I noticed wrong encodings for the
above instructions (wrong operand name in rldimi, wrong form
and sub-opcode for rldcl).
Tests will be added together with the asm parser.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180606 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 1fb54cfb0a013c8ab664a6e754b34a125fe85254 |
|
17-Apr-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Mark some more patterns as isCodeGenOnly.
A couple of recently introduced conditional branch patterns
also need to be marked as isCodeGenOnly since they cannot
be handled by the asm parser.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179690 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 00e86ad167e2d151d819ae7b691dadf9e1d9418c |
|
15-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Mark all PPC comparison instructions as not having side effects
Now that the CR spilling issues have been resolved, we can remove the
unmodeled-side-effect attributes from the comparison instructions (and also
mark them as isCompare). By allowing these, by default, to have unmodeled side
effects, we were hiding problems with CR spilling; but everything seems much
happier now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179502 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 63496f66c5b528a48f8da7714ee3f635f8aadd18 |
|
14-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Mark all PPC CR registers to be spilled as live-in and tag MFCR appropriately
Leaving MFCR has having unmodeled side effects is not enough to prevent
unwanted instruction reordering post-RA. We could probably apply a stronger
barrier attribute, but there is a better way: Add all (not just the first) CR
to be spilled as live-in to the entry block, and add all CRs to the MFCR
instruction as implicitly killed.
Unfortunately, I don't have a small test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179465 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 598574695b70627213ea7bc224ee87ccfef44031 |
|
12-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Remove (broken) nested implicit definition lists
TableGen will not combine nested list 'let' bindings into a single list, and
instead uses only the inner scope. As a result, several instruction definitions
were missing implicit register defs that were in outer scopes. This de-nests
these scopes and makes all instructions have only one let binding which sets
implicit register definitions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179392 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 171a8adf3168aee2f739f91c1800e9025892c7b5 |
|
12-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add PPC instruction record forms and associated query functions
This is prep. work for the implementation of optimizeCompare. Many PPC
instructions have 'record' forms (in almost all cases, this means that the RC
bit is set) that cause the result of the instruction to be compared with zero,
and the result of that comparison saved in a predefined condition register. In
order to add the record forms of the instructions without too much
copy-and-paste, the relevant functions have been refactored into multiclasses
which define both the record and normal forms.
Also, two TableGen-generated mapping functions have been added which allow
querying the instruction code for the record form given the normal form (and
vice versa).
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179356 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 90dd7fd167b6d09e4a7f37e35dcbfdc492546a79 |
|
10-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Prep for if conversion of bctr[l]
This adds in-principle support for if-converting the bctr[l] instructions.
These instructions are used for indirect branching. It seems, however, that the
current if converter will never actually predicate these. To do so, it would
need the ability to hoist a few setup insts. out of the conditionally-executed
block. For example, code like this:
void foo(int a, int (*bar)()) { if (a != 0) bar(); }
becomes:
...
beq 0, .LBB0_2
std 2, 40(1)
mr 12, 4
ld 3, 0(4)
ld 11, 16(4)
ld 2, 8(4)
mtctr 3
bctrl
ld 2, 40(1)
.LBB0_2:
...
and it would be safe to do all of this unconditionally with a predicated
beqctrl instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179156 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 7eb0d8148e1210d9e31ab471477de47b53bab117 |
|
10-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Allow PPC B and BLR to be if-converted into some predicated forms
This enables us to form predicated branches (which are the same conditional
branches we had before) and also a larger set of predicated returns (including
instructions like bdnzlr which is a conditional return and loop-counter
decrement all in one).
At the moment, if conversion does not capture all possible opportunities. A
simple example is provided in early-ret2.ll, where if conversion forms one
predicated return, and then the PPCEarlyReturn pass picks up the other one. So,
at least for now, we'll keep both mechanisms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 946a811ef12188f4a129f4f98759fc9f7ba33d61 |
|
07-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC rotate instructions don't have unmodeled side effcts
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178982 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| f0e3ca012bc7dd6b95c091a7f5f147794983cf97 |
|
07-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Most PPC M[TF]CR instructions do not have side effects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178978 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 3aea7cb7b2c54071fc273a0c3a97850bd14de5ac |
|
07-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC pre-increment load instructions do not have side effects
A few were missed in r178972.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178973 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| fa1d102a052e0375c954d9a35b3a687f81194f7a |
|
07-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC pre-increment load instructions do not have side effects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178972 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 012ffd56059576d4a0ee523f673b3190b1f03311 |
|
06-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC ISEL is a select and never has side effects
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 46479197843ecb651adc9417c49bbd1b00acfcb6 |
|
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add more PPC floating-point conversion instructions
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 1fce88313e4d46fdd432b68f7c54fde972c0b526 |
|
01-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC popcntw instruction
The popcntw instruction is available whenever the popcntd instruction is
available, and performs a separate popcnt on the lower and upper 32-bits.
Ignoring the high-order count, this can be used for the 32-bit input case
(saving on the explicit zero extension otherwise required to use popcntd).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178470 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405 |
|
31-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC(64) i32 -> float/double conversion
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode. Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.
This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| efdd4673d6e78f3d406c5d1f44316aef8a5a9a48 |
|
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC64 ldbrx/stdbrx instructions
These are 64-bit load/store with byte-swap, and available on the P7 and the A2.
Like the similar instructions for 16- and 32-bit words, these are matched in the
target DAG-combine phase against load/store-bswap pairs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178276 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| c53ab4d77f4b3d2905cf9ad625c28ff6b1c04aff |
|
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPC64 popcntd instruction
PPC ISA 2.06 (P7, A2, etc.) has a popcntd instruction. Add this instruction and
tell TTI about it so that popcount-loop recognition will know about it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178233 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| d01efc737aad480eaaa1316b05b7165ce7c04c96 |
|
28-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix typo in PPCInstr64Bit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178219 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 6375e1b87b089093fecdb09f609251e91d1c2c4f |
|
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Use the PPC no-r0 class on the TOC LD pseudos
The register parameter in these instructions becomes the base register in an
r+i ld instruction (and, thus, cannot be r0).
This is not yet testable because we don't yet allocate r0 (and even then any
test would be very fragile).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178121 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 56d926ac14406ef87d34fbf77632c26d8e789818 |
|
27-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Apply the no-r0 class to PPC TOC ADDI[S] pseudo instructions
Like the addi/addis instructions themselves, these pseudo instructions also
cannot have r0 as their register parameter (because it will be interpreted as
the value 0).
This is not yet testable because we don't yet allocate r0 (and even when we do,
any regression test would be very fragile because it would depend on the
register allocator heuristics).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178118 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 3d386421e0d8756a4665d00fcfa66a99990f0f91 |
|
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Mark patterns as isCodeGenOnly.
There remain a number of patterns that cannot (and should not)
be handled by the asm parser, in particular all the Pseudo patterns.
This commit marks those patterns as isCodeGenOnly.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178008 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| d67768db809d6b1cfe6f7c484b3719a6103286ea |
|
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Remove LDrs pattern.
The LDrs pattern is a duplicate of LD, except that it accepts memory
addresses where the displacement is a symbolLo64. An operand type
"memrs" is defined for just that purpose.
However, this wouldn't be necessary if the default "memrix" operand
type were to simply accept 64-bit symbolic addresses directly.
The only problem with that is that it uses "symbolLo", which is
hardcoded to 32-bit.
To fix this, this commit changes "memri" and "memrix" to use new
operand types for the memory displacement, which allow iPTR
instead of i32. This will also make address parsing easier to
implment in the asm parser.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178005 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 2b0850b8305380244ec98e1b1c89aaf57adf3b09 |
|
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Remove ADDIL patterns.
The ADDI/ADDI8 patterns are currently duplicated into ADDIL/ADDI8L,
which describe the same instruction, except that they accept a
symbolLo[64] operand instead of a s16imm[64] operand.
This duplication confuses the asm parser, and it actually not really
needed, since symbolLo[64] already accepts immediate operands anyway.
So this commit removes the duplicate patterns.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178004 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| a01c7dbaabae7cf569410bedd71361b75f65875f |
|
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Use CCBITRC operand for ISEL patterns.
This commit changes the ISEL patterns to use a CCBITRC operand
instead of a "pred" operand. This matches the actual instruction
text more directly, and simplifies use of ISEL with the asm parser.
In addition, this change allows some simplification of handling
the "pred" operand, as this is now only used by BCC.
No change in generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| e8680da874631c0531872c83d6643e05bbefebd1 |
|
26-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
PowerPC: Move some 64-bit branch patterns.
In PPCInstr64Bit.td, some branch patterns appear in a different sequence
than the corresponding 32-bit patterns in PPCInstrInfo.td.
To simplify future changes that affect both files, this commit moves
those patterns to rearrange them into a similar sequence.
No effect on generated code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178001 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 5b390e4cd8838bad351364e65d20c292fae6bf23 |
|
25-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Use direct types in PowerPC instruction patterns.
This commit updates the PowerPC back-end (PPCInstrInfo.td and
PPCInstr64Bit.td) to use types instead of register classes in
instruction patterns, along the lines of Jakob Stoklund Olesen's
changes in r177835 for Sparc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177890 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 1492a4e5185d963cb79786311b882153fce6718a |
|
25-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Use direct types in PowerPC Pat patterns.
This commit updates the PowerPC back-end (PPCInstrInfo.td and
PPCInstr64Bit.td) to use types instead of register classes in
Pat patterns, along the lines of Jakob Stoklund Olesen's
changes in r177829 for Sparc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 86765fbe170198e7bb40fd8499d1354f4c786f60 |
|
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Remove ABI-duplicated call instruction patterns.
We currently have a duplicated set of call instruction patterns depending
on the ABI to be followed (Darwin vs. Linux). This is a bit odd; while the
different ABIs will result in different instruction sequences, the actual
instructions themselves ought to be independent of the ABI. And in fact it
turns out that the only nontrivial difference between the two sets of
patterns is that in the PPC64 Linux ABI, the instruction used for indirect
calls is marked to take X11 as extra input register (which is indeed used
only with that ABI to hold an incoming environment pointer for nested
functions). However, this does not need to be hard-coded at the .td
pattern level; instead, the C++ code expanding calls can simply add that
use, just like it adds uses for argument registers anyway.
No change in generated code expected.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177735 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 89ec847ec79f422527dce0d5321be5526c84bb71 |
|
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Rename memrr ptrreg and offreg components.
Currently, the sub-operand of a memrr address that corresponds to what
hardware considers the base register is called "offreg", while the
sub-operand that corresponds to the offset is called "ptrreg".
To avoid confusion, this patch simply swaps the named of those two
sub-operands and updates all uses. No functional change is intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 881a7154b9f9b85f6a8515e282cacdfc9df156cf |
|
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix swapped BasePtr and Offset in pre-inc memory addresses.
PPCTargetLowering::getPreIndexedAddressParts currently provides
the base part of a memory address in the offset result, and the
offset part in the base result. That swap is then undone again
when an MI instruction is generated (in PPCDAGToDAGISel::Select
for loads, and using .md Pat patterns for stores).
This patch reverts this double swap, to make common code and
back-end be in sync as to which part of the address is base
and which is offset.
To avoid performance regressions in certain cases, target code
now checks whether the choice of base register would be rejected
for pre-inc accesses by common code, and attempts to swap base
and offset again in such cases. (Overall, this means that now
pre-ice accesses are generated *more* frequently than before.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177733 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| cff0faa16a7d03951fba0aa279a2c8441c5718f8 |
|
22-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Remove the xaddroff ComplexPattern.
The xaddroff pattern is currently (mistakenly) used to recognize
the *base* register in pre-inc store patterns. This patch replaces
those uses by ptr_rc_nor0 (as is elsewhere done to match the base
register of an address), and removes the now unused ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177731 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 3ea1b064a0b9c3d161b0f77a9e957970f98907ab |
|
22-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix a register-class comparison bug in PPCCTRLoops
Thanks to Jakob for isolating the underlying problem from the
test case in r177423. The original commit had introduced
asymmetric copy operations, but these turned out to be a work-around
to the real problem (the use of == instead of hasSubClassEq in PPCCTRLoops).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177679 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 7ee74a663a3b4d4ee6b55d23362f347ed1d390c2 |
|
21-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Implement builtin_{setjmp/longjmp} on PPC
This implements SJLJ lowering on PPC, making the Clang functions
__builtin_{setjmp/longjmp} functional on PPC platforms. The implementation
strategy is similar to that on X86, with the exception that a branch-and-link
variant is used to get the right jump address. Credit goes to Bill Schmidt for
suggesting the use of the unconditional bcl form (instead of the regular bl
instruction) to limit return-address-cache pollution.
Benchmarking the speed at -O3 of:
static jmp_buf env_sigill;
void foo() {
__builtin_longjmp(env_sigill,1);
}
main() {
...
for (int i = 0; i < c; ++i) {
if (__builtin_setjmp(env_sigill)) {
goto done;
} else {
foo();
}
done:;
}
...
}
vs. the same code using the libc setjmp/longjmp functions on a P7 shows that
this builtin implementation is ~4x faster with Altivec enabled and ~7.25x
faster with Altivec disabled. This comparison is somewhat unfair because the
libc version must also save/restore the VSX registers which we don't yet
support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| dff4d1522a3a14df3c40c33421e24f59633da67b |
|
19-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Add missing mayLoad flag to LHAUX8 and LWAUX.
All pre-increment load patterns need to set the mayLoad flag (since
they don't provide a DAG pattern).
This was missing for LHAUX8 and LWAUX, which is added by this patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177431 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8353d1e0e5fd23bb9b6c11acda8157d728d89223 |
|
19-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Rewrite LHAU8 pattern to use standard memory operand.
As opposed to to pre-increment store patterns, the pre-increment
load patterns were already using standard memory operands, with
the sole exception of LHAU8.
As there's no real reason why LHAU8 should be different here,
this patch simply rewrites the pattern to also use a memri
operand, just like all the other patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177430 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 5882e3d82831710a7ea1fe8de4813350d4eecf05 |
|
19-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Rewrite pre-increment store patterns to use standard memory operands.
Currently, pre-increment store patterns are written to use two separate
operands to represent address base and displacement:
stwu $rS, $ptroff($ptrreg)
This causes problems when implementing the assembler parser, so this
commit changes the patterns to use standard (complex) memory operands
like in all other memory access instruction patterns:
stwu $rS, $dst
To still match those instructions against the appropriate pre_store
SelectionDAG nodes, the patch uses the new feature that allows a Pat
to match multiple DAG operands against a single (complex) instruction
operand.
Approved by Hal Finkel.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177429 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 880d82e3dbf8ae6c2babf5943d524bbe25015eba |
|
19-Mar-2013 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix sub-operand size mismatch in tocentry operands.
The tocentry operand class refers to 64-bit values (it is only used in 64-bit,
where iPTR is a 64-bit type), but its sole suboperand is designated as 32-bit
type. This causes a mismatch to be detected at compile-time with the TableGen
patch I'll check in shortly.
To fix this, this commit changes the suboperand to a 64-bit type as well.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177427 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| a548afc98fd4c61a8dfdd550ba57c37f2cfe3ed9 |
|
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Prepare to make r0 an allocatable register on PPC
Currently the PPC r0 register is unconditionally reserved. There are two reasons
for this:
1. r0 is treated specially (as the constant 0) by certain instructions, and so
cannot be used with those instructions as a regular register.
2. r0 is used as a temporary register in the CR-register spilling process
(where, under some circumstances, we require two GPRs).
This change addresses the first reason by introducing a restricted register
class (without r0) for use by those instructions that treat r0 specially. These
register classes have a new pseudo-register, ZERO, which represents the r0-as-0
use. This has the side benefit of making the existing target code simpler (and
easier to understand), and will make it clear to the register allocator that
uses of r0 as 0 don't conflict will real uses of the r0 register.
Once the CR spilling code is improved, we'll be able to allocate r0.
Adding these extra register classes, for some reason unclear to me, causes
requests to the target to copy 32-bit registers to 64-bit registers. The
resulting code seems correct (and causes no test-suite failures), and the new
test case covers this new kind of asymmetric copy.
As r0 is still reserved, no functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177423 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| ec2e968b7a60a4b48bbb315f8dd6e96e51c31691 |
|
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Cleanup PPC64 unaligned i64 load/store
Remove an accidentally-added instruction definition and add a comment in the
test case. This is in response to a post-commit review by Bill Schmidt.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177404 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 08a215c2869a89b977754334943681a56f5fc460 |
|
19-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC unaligned 64-bit loads and stores
PPC64 supports unaligned loads and stores of 64-bit values, but
in order to use the r+i forms, the offset must be a multiple of 4.
Unfortunately, this cannot always be determined by examining the
immediate itself because it might be available only via a TOC entry.
In order to get around this issue, we additionally predicate the
selection of the r+i form on the alignment of the load or store
(forcing it to be at least 4 in order to select the r+i form).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177338 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 53b0b0e75480121e4e01a7a76e17909e92b1762a |
|
21-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Large code model support for PowerPC.
Large code model is identical to medium code model except that the
addis/addi sequence for "local" accesses is never used. All accesses
use the addis/ld sequence.
The coding changes are straightforward; most of the patch is taken up
with creating variants of the medium model tests for large model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175767 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| b453e16855f347e300f1dc0cd0dfbdd65c27b0d2 |
|
14-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch improves the 64-bit PowerPC InitialExec TLS support by providing
for a wider range of GOT entries that can hold thread-relative offsets.
This matches the behavior of GCC, which was not documented in the PPC64 TLS
ABI. The ABI will be updated with the new code sequence.
Former sequence:
ld 9,x@got@tprel(2)
add 9,9,x@tls
New sequence:
addis 9,2,x@got@tprel@ha
ld 9,x@got@tprel@l(9)
add 9,9,x@tls
Note that a linker optimization exists to transform the new sequence into
the shorter sequence when appropriate, by replacing the addis with a nop
and modifying the base register and relocation type of the ld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170209 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 1e18b861920ad2fd1a63e006cac61a4e274e5fdf |
|
13-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This is another cleanup patch for 64-bit PowerPC TLS processing. I had
some hackery in place that hid my poor use of TblGen, which I've now sorted
out and cleaned up. No change in observable behavior, so no new test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170149 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| dfebc4cc4c267f797e823b781d73586cc6fc49c5 |
|
13-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This is just a clean-up patch that simplifies the initial-exec TLS logic by
avoiding use of machine operand flags. No change in observable behavior, so
no new test cases.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170141 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 349c2787cf9e174c8aa955bf8e3b09a405b2aece |
|
12-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements local-dynamic TLS model support for the 64-bit
PowerPC target. This is the last of the four models, so we now have
full TLS support.
This is mostly a straightforward extension of the general dynamic model.
I had to use an additional Chain operand to tie ADDIS_DTPREL_HA to the
register copy following ADDI_TLSLD_L; otherwise everything above the
ADDIS_DTPREL_HA appeared dead and was removed.
As before, there are new test cases to test the assembly generation, and
the relocations output during integrated assembly. The expected code
gen sequence can be read in test/CodeGen/PowerPC/tls-ld.ll.
There are a couple of things I think can be done more efficiently in the
overall TLS code, so there will likely be a clean-up patch forthcoming;
but for now I want to be sure the functionality is in place.
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170003 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 57ac1f458a754f30cf500410b438fb260f9b8fe5 |
|
11-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements the general dynamic TLS model for 64-bit PowerPC.
Given a thread-local symbol x with global-dynamic access, the generated
code to obtain x's address is:
Instruction Relocation Symbol
addis ra,r2,x@got@tlsgd@ha R_PPC64_GOT_TLSGD16_HA x
addi r3,ra,x@got@tlsgd@l R_PPC64_GOT_TLSGD16_L x
bl __tls_get_addr(x@tlsgd) R_PPC64_TLSGD x
R_PPC64_REL24 __tls_get_addr
nop
<use address in r3>
The implementation borrows from the medium code model work for introducing
special forms of ADDIS and ADDI into the DAG representation. This is made
slightly more complicated by having to introduce a call to the external
function __tls_get_addr. Using the full call machinery is overkill and,
more importantly, makes it difficult to add a special relocation. So I've
introduced another opcode GET_TLS_ADDR to represent the function call, and
surrounded it with register copies to set up the parameter and return value.
Most of the code is pretty straightforward. I ran into one peculiarity
when I introduced a new PPC opcode BL8_NOP_ELF_TLSGD, which is just like
BL8_NOP_ELF except that it takes another parameter to represent the symbol
("x" above) that requires a relocation on the call. Something in the
TblGen machinery causes BL8_NOP_ELF and BL8_NOP_ELF_TLSGD to be treated
identically during the emit phase, so this second operand was never
visited to generate relocations. This is the reason for the slightly
messy workaround in PPCMCCodeEmitter.cpp:getDirectBrEncoding().
Two new tests are included to demonstrate correct external assembly and
correct generation of relocations using the integrated assembler.
Comments welcome!
Thanks,
Bill
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169910 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| d7802bf0ddcac16ee910105922492aee86a53e1b |
|
04-Dec-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch introduces initial-exec model support for thread-local storage
on 64-bit PowerPC ELF.
The patch includes code to handle external assembly and MC output with the
integrated assembler. It intentionally does not support the "old" JIT.
For the initial-exec TLS model, the ABI requires the following to calculate
the address of external thread-local variable x:
Code sequence Relocation Symbol
ld 9,x@got@tprel(2) R_PPC64_GOT_TPREL16_DS x
add 9,9,x@tls R_PPC64_TLS x
The register 9 is arbitrary here. The linker will replace x@got@tprel
with the offset relative to the thread pointer to the generated GOT
entry for symbol x. It will replace x@tls with the thread-pointer
register (13).
The two test cases verify correct assembly output and relocation output
as just described.
PowerPC-specific selection node variants are added for the two
instructions above: LD_GOT_TPREL and ADD_TLS. These are inserted
when an initial-exec global variable is encountered by
PPCTargetLowering::LowerGlobalTLSAddress(), and later lowered to
machine instructions LDgotTPREL and ADD8TLS. LDgotTPREL is a pseudo
that uses the same LDrs support added for medium code model's LDtocL,
with a different relocation type.
The rest of the processing is straightforward.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169281 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 34a9d4b3b9b7858b729a1af67afa721c048fe5e7 |
|
27-Nov-2012 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
This patch implements medium code model support for 64-bit PowerPC.
The default for 64-bit PowerPC is small code model, in which TOC entries
must be addressable using a 16-bit offset from the TOC pointer. Additionally,
only TOC entries are addressed via the TOC pointer.
With medium code model, TOC entries and data sections can all be addressed
via the TOC pointer using a 32-bit offset. Cooperation with the linker
allows 16-bit offsets to be used when these are sufficient, reducing the
number of extra instructions that need to be executed. Medium code model
also does not generate explicit TOC entries in ".section toc" for variables
that are wholly internal to the compilation unit.
Consider a load of an external 4-byte integer. With small code model, the
compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
With medium model, it instead generates:
addis 3, 2, .LC1@toc@ha
ld 3, .LC1@toc@l(3)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc ei[TC],ei
Here .LC1@toc@ha is a relocation requesting the upper 16 bits of the
32-bit offset of ei's TOC entry from the TOC base pointer. Similarly,
.LC1@toc@l is a relocation requesting the lower 16 bits. Note that if
the linker determines that ei's TOC entry is within a 16-bit offset of
the TOC base pointer, it will replace the "addis" with a "nop", and
replace the "ld" with the identical "ld" instruction from the small
code model example.
Consider next a load of a function-scope static integer. For small code
model, the compiler generates:
ld 3, .LC1@toc(2)
lwz 4, 0(3)
.section .toc,"aw",@progbits
.LC1:
.tc test_fn_static.si[TC],test_fn_static.si
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
For medium code model, the compiler generates:
addis 3, 2, test_fn_static.si@toc@ha
addi 3, 3, test_fn_static.si@toc@l
lwz 4, 0(3)
.type test_fn_static.si,@object
.local test_fn_static.si
.comm test_fn_static.si,4,4
Again, the linker may replace the "addis" with a "nop", calculating only
a 16-bit offset when this is sufficient.
Note that it would be more efficient for the compiler to generate:
addis 3, 2, test_fn_static.si@toc@ha
lwz 4, test_fn_static.si@toc@l(3)
The current patch does not perform this optimization yet. This will be
addressed as a peephole optimization in a later patch.
For the moment, the default code model for 64-bit PowerPC will remain the
small code model. We plan to eventually change the default to medium code
model, which matches current upstream GCC behavior. Note that the different
code models are ABI-compatible, so code compiled with different models will
be linked and execute correctly.
I've tested the regression suite and the application/benchmark test suite in
two ways: Once with the patch as submitted here, and once with additional
logic to force medium code model as the default. The tests all compile
cleanly, with one exception. The mandel-2 application test fails due to an
unrelated ABI compatibility with passing complex numbers. It just so happens
that small code model was incredibly lucky, in that temporary values in
floating-point registers held the expected values needed by the external
library routine that was called incorrectly. My current thought is to correct
the ABI problems with _Complex before making medium code model the default,
to avoid introducing this "regression."
Here are a few comments on how the patch works, since the selection code
can be difficult to follow:
The existing logic for small code model defines three pseudo-instructions:
LDtoc for most uses, LDtocJTI for jump table addresses, and LDtocCPT for
constant pool addresses. These are expanded by SelectCodeCommon(). The
pseudo-instruction approach doesn't work for medium code model, because
we need to generate two instructions when we match the same pattern.
Instead, new logic in PPCDAGToDAGISel::Select() intercepts the TOC_ENTRY
node for medium code model, and generates an ADDIStocHA followed by either
a LDtocL or an ADDItocL. These new node types correspond naturally to
the sequences described above.
The addis/ld sequence is generated for the following cases:
* Jump table addresses
* Function addresses
* External global variables
* Tentative definitions of global variables (common linkage)
The addis/addi sequence is generated for the following cases:
* Constant pool entries
* File-scope static global variables
* Function-scope static variables
Expanding to the two-instruction sequences at select time exposes the
instructions to subsequent optimization, particularly scheduling.
The rest of the processing occurs at assembly time, in
PPCAsmPrinter::EmitInstruction. Each of the instructions is converted to
a "real" PowerPC instruction. When a TOC entry needs to be created, this
is done here in the same manner as for the existing LDtoc, LDtocJTI, and
LDtocCPT pseudo-instructions (I factored out a new routine to handle this).
I had originally thought that if a TOC entry was needed for LDtocL or
ADDItocL, it would already have been generated for the previous ADDIStocHA.
However, at higher optimization levels, the ADDIStocHA may appear in a
different block, which may be assembled textually following the block
containing the LDtocL or ADDItocL. So it is necessary to include the
possibility of creating a new TOC entry for those two instructions.
Note that for LDtocL, we generate a new form of LD called LDrs. This
allows specifying the @toc@l relocation for the offset field of the LD
instruction (i.e., the offset is replaced by a SymbolLo relocation).
When the peephole optimization described above is added, we will need
to do similar things for all immediate-form load and store operations.
The seven "mcm-n.ll" test cases are kept separate because otherwise the
intermingling of various TOC entries and so forth makes the tests fragile
and hard to understand.
The above assumes use of an external assembler. For use of the
integrated assembler, new relocations are added and used by
PPCELFObjectWriter. Testing is done with "mcm-obj.ll", which tests for
proper generation of the various relocations for the same sequences
tested with the external assembler.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168708 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8f887369cbab012e39c3fc80b00ea399509aa24e |
|
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix wrong PowerPC instruction opcodes for:
- lwaux
- lhzux
- stbu
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 18430436cad62d6215e1c07cba2059f6eecb7657 |
|
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix instruction encoding for "bd(n)z" on PowerPC,
by using a new instruction format BForm_1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167861 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| bc40df3f22a026ffce616cbd69ddb28148b82aad |
|
13-Nov-2012 |
Ulrich Weigand <ulrich.weigand@de.ibm.com> |
Fix instruction encoding for "isel" on PowerPC,
using a new instruction format AForm_4.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@167860 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| edf5e9a1d5f0cb4cfe747c761c73a2e303f365c4 |
|
26-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
PowerPC: Fix for rldcl/rldicl/rldicr MC emission
This patch fixes the rldcl/rldicl/rldicr instruction emission. The issue is
the MDForm_1 instruction defines the PowerISA MB field from 'rldicl'
with the name MBE, but RLDCL/RLDICL/RLDICR definition uses as 'MB'.
It end up by generatint the 'rldicl' enconding at
'lib/Target/PowerPC/PPCGenMCCodeEmitter.inc' to use the fourth argument as the
third. The patch changes it by adjusting to use the fourth argument as
intended.
Fixes PR14180.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 18560fae0bb122857a61bb36f22628901cdc3dde |
|
25-Oct-2012 |
Adhemerval Zanella <azanella@linux.vnet.ibm.com> |
This patch fixes the MC object emission of 'nop' for external function calls
and also fixes the R_PPC64_TOC16 and R_PPC64_TOC16_DS relocation offset.
The 'nop' is needed so a restore TOC instruction (ld r2,40(r1)) can be placed
by the linker to correct restore the TOC of previous function.
Current code has two issues: it defines in PPCInstr64Bit.td file a LDinto_toc
and LDtoc_restore as a DSForm_1 with DS_RA=0 where it should be
DS=2 (the 8 bytes displacement of the TOC saving). It also wrongly emits a
MC intruction using an uint32_t value while the PPC::BL8_NOP_ELF
and PPC::BLA8_NOP_ELF are both uint64_t (because of the following 'nop').
This patch corrects the remaining ExecutionEngine using MCJIT:
ExecutionEngine/2002-12-16-ArgTest.ll
ExecutionEngine/2003-05-07-ArgumentTest.ll
ExecutionEngine/2005-12-02-TailCallBug.ll
ExecutionEngine/hello.ll
ExecutionEngine/hello2.ll
ExecutionEngine/test-call.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@166682 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 916381569aa5cd33e4ed4c1585f48cf5da1a6684 |
|
04-Oct-2012 |
Will Schmidt <will_schmidt@vnet.ibm.com> |
- add tokens to PPCInstrInfo.td and PPCInstr64Bit.td to resolve
"Instruction 'foo' has no tokens" errors during llvm-tblgen
-gen-asm-matcher attempts. At this time, the added
tokens are "#comment" style rather than the actual mnemonic. This will
be revisited once the rest of the base asmparser bits get straightened
out for ppc64-elf-linux.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165237 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| c10d5e9dae40801622c73237b484d51da73f77b9 |
|
05-Sep-2012 |
Hal Finkel <hfinkel@anl.gov> |
Move the PPC TOC defs into the PPC64 InstrInfo file.
Since TOC is just defined for PPC64, move its definition to PPC64 td file.
Patch by Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@163234 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8dc440a46a5153a1640a3050480cceca9b8af05d |
|
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split several PPC instruction classes.
Slight reorganisation of PPC instruction classes for scheduling. No
functionality change for existing subtargets.
- Clearly separate load/store-with-update instructions from regular loads and stores.
- Split IntRotateD -> IntRotateD and IntRotateDI
- Split out fsub and fadd from FPGeneral -> FPAddSub
- Update existing itineraries
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162729 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| f3c3828e57d922bbe912ffabbd9252b9f5100c14 |
|
28-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Allow remat of LI on PPC.
Allow load-immediates to be rematerialised in the register coalescer for
PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail,
because it relies on a register move getting emitted. The immediate load is
equivalent, so change this test case.
Patch by Tobias von Koch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162727 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 9fb8b49380e7cf6ce88400ad65051e830563bc81 |
|
24-Aug-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Lower constant pools and jump tables via TOC on PPC64/SVR4.
In collaboration with Adhemerval Zanella.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162562 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8da94ad6e0947690201c543da556ec0396ad9912 |
|
07-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add a comment about mftb vs. mfspr on PPC.
Thanks to Alex Rosenberg for the suggestion.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161428 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| f45717e985260e9416dbd2fe8df471d48705c86a |
|
06-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
MFTB on PPC64 should really be encoded using MFSPR.
The MFTB instruction itself is being phased out, and its functionality
is provided by MFSPR. According to the ISA docs, using MFSPR works on all known
chips except for the 601 (which did not have a timebase register anyway)
and the POWER3.
Thanks to Adhemerval Zanella for pointing this out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8cc3474f72388836fa4ca7d3622289fb9ee08b41 |
|
04-Aug-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add readcyclecounter lowering on PPC64.
On PPC64, this can be done with a simple TableGen pattern.
To enable this, I've added the (otherwise missing) readcyclecounter
SDNode definition to TargetSelectionDAG.td.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161302 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 68c10a2ff74fe882cfd789983b2d0f12e42fb0ec |
|
13-Jul-2012 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
Remove variable_ops from call instructions in most targets.
Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160189 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 009f7afbeb77d1cc8e962bac7057b73b6d39d62f |
|
23-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for the PPC isel instruction.
The isel (integer select) instruction is supported on the 440 and A2
embedded cores and on the POWER7.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159045 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 0fcdd8b2cc2b1bcf0aa64870d5269f9ac6dc76c0 |
|
20-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for generating reg+reg (indexed) pre-inc loads on PPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158823 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| ac81cc3282750d724f824547bc519caec0a01bce |
|
19-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add support for generating reg+reg preinc stores on PPC.
PPC will now generate STWUX and friends.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158698 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 16803097fbefa313fdadc3adede659bd0e52cec1 |
|
12-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split out the PPC instruction class IntSimple from IntGeneral.
On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158366 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 0a3e33b633aa645465b6bda0bba82788b0644a01 |
|
10-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Improve ext/trunc patterns on PPC64.
The PPC64 backend had patterns for i32 <-> i64 extensions and truncations that
would leave self-moves in the final assembly. Replacing those patterns with ones
based on the SUBREG builtins yields better-looking code.
Thanks to Jakob and Owen for their suggestions in this matter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 99f823f94374917174f96a7689955b8463db6816 |
|
08-Jun-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add the PPCCTRLoops pass: a PPC machine-code-level optimization pass to form CTR-based loop branching code.
This pass is derived from the Hexagon HardwareLoops pass. The only significant enhancement over the Hexagon
pass is that PPCCTRLoops will also attempt to delete the replaced add and compare operations if they are
no longer otherwise used. Also, invalid preheader DebugLoc is not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158204 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| fd42ed676e37c29364f53f848320b7cb706111e0 |
|
04-Jun-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Implement local-exec TLS on PowerPC.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157935 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 2e8e5c0eca6f34a94f92824fc713afd6dc329e25 |
|
20-May-2012 |
Hal Finkel <hfinkel@anl.gov> |
Add a missing PPC 64-bit stwu pattern.
This seems to fix the remaining compile-time failures on PPC64 when
compiling with -enable-ppc-preinc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 20b529b3f90bf17b6023ed6f8983c53c1f5be1ad |
|
01-Apr-2012 |
Hal Finkel <hfinkel@anl.gov> |
Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.
Loads and stores can have different pipeline behavior, especially on
embedded chips. This change allows those differences to be expressed.
Except for the 440 scheduler, there are no functionality changes.
On the 440, the latency adjustment is only by one cycle, and so this
probably does not affect much. Nevertheless, it will make a larger
difference in the future and this removes a FIXME from the 440 itin.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153821 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 5b00ceaeeabff8c25abb09926343c3fcb06053d8 |
|
31-Mar-2012 |
Hal Finkel <hfinkel@anl.gov> |
Fix dynamic linking on PPC64.
Dynamic linking on PPC64 has had problems since we had to move the top-down
hazard-detection logic post-ra. For dynamic linking to work there needs to be
a nop placed after every call. It turns out that it is really hard to guarantee
that nothing will be placed in between the call (bl) and the nop during post-ra
scheduling. Previous attempts at fixing this by placing logic inside the
hazard detector only partially worked.
This is now fixed in a different way: call+nop codegen-only instructions. As far
as CodeGen is concerned the pair is now a single instruction and cannot be split.
This solution works much better than previous attempts.
The scoreboard hazard detector is also renamed to be more generic, there is currently
no cpu-specific logic in it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153816 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| e46137f498fa81a088f13d24c79242eed3ff45a7 |
|
06-Mar-2012 |
Roman Divacky <rdivacky@freebsd.org> |
Convert PowerPC to register mask operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152122 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 3161039cf3318a1634af04e1da2038e9dc1f4b3a |
|
24-Feb-2012 |
Hal Finkel <hfinkel@anl.gov> |
X11/X2 loads around indirect calls on ppc64 should not be deleted.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151374 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 31d157ae1ac2cd9c787dc3c1d28e64c682803844 |
|
18-Feb-2012 |
Jia Liu <proljc@gmail.com> |
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150878 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 234bb38d6c421ea22229087a9835afe99e531276 |
|
07-Dec-2011 |
Hal Finkel <hfinkel@anl.gov> |
make CR spill and restore 64-bit clean (no functional change), and fix some other problems found with -verify-machineinstrs
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146024 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 0c9b559bfd0b476c2dde787285a1195f3142c423 |
|
03-Jun-2011 |
Roman Divacky <rdivacky@freebsd.org> |
Fix wrong usages of CTR/MCTR where CTR8/MCTR8 was meant.
- Check for MTCTR8 in addition to MTCTR when looking up a hazard.
- When lowering an indirect call use CTR8 when targeting 64bit.
- Introduce BCTR8 that uses CTR8 and use it on 64bit when expanding ISD::BRIND.
The last change fixes PR8487. With those changes, we are able to compile a
running "ls" and "sh" on FreeBSD/PowerPC64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132552 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 0113e4e3f242fef41e6c733d1945f9950276cc9c |
|
19-May-2011 |
Cameron Zwarich <zwarich@apple.com> |
Fix PR8828 by removing the explicit def in MovePCToLR as well as the pointless
piclabel operand. The operand in the tablegen definition doesn't actually turn
into an MI operand, so it just confuses anything checking the TargetInstrDesc
for the number of operands. It suffices to just have an implicit def of LR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@131626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| cf3a74824f7c8936fc5c2ebb8ec215621963844e |
|
04-Apr-2011 |
Jakob Stoklund Olesen <stoklund@2pi.dk> |
PowerPC atomic pseudos clobber CR0, they don't read it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@128829 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| b7035d04421112a4585245f67bc564170ec45b29 |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
split out an encoder for memri operands, allowing a relocation to be plopped
into the immediate field. This allows us to encode stuff like this:
lbz r3, lo16(__ZL4init)(r4) ; globalopt.cpp:5
; encoding: [0x88,0x64,A,A]
; fixup A - offset: 0, value: lo16(__ZL4init), kind: fixup_ppc_lo16
stw r3, lo16(__ZL1s)(r5) ; globalopt.cpp:6
; encoding: [0x90,0x65,A,A]
; fixup A - offset: 0, value: lo16(__ZL1s), kind: fixup_ppc_lo16
With this, we should have a completely function MCCodeEmitter for PPC, wewt.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119134 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 17e2c188359769a1df18c42593a94ce0fc2a9a75 |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
add support for encoding the lo14 forms used for a few PPC64 addressing
modes. For example, we now get:
ld r3, lo16(_G)(r3) ; encoding: [0xe8,0x63,A,0bAAAAAA00]
; fixup A - offset: 0, value: lo16(_G), kind: fixup_ppc_lo14
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119133 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 85cf7d737dd26e984974e072d28225bd00c625c2 |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
implement the start of support for lo16 and ha16, allowing us to get stuff like:
lis r4, ha16(__ZL4init) ; encoding: [0x3c,0x80,A,A]
; fixup A - offset: 0, value: ha16(__ZL4init), kind: fixup_ppc_ha16
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| ab638645647bef87ffe8d545fbcb1b69d3af45ce |
|
15-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
remove asmstrings (which can never be printed) from pseudo
instructions, allowing is to eliminate some dead operand
printing methods from the instprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119113 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 142b531e024c7b814df74951b378b9e3e11d0d42 |
|
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
move the pic base symbol stuff up to MachineFunction
since it is trivial and will be shared between ppc and x86.
This substantially simplifies the X86 backend also.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119089 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 6135a96792ca05f6366e5dbaee6208e84589c47f |
|
14-Nov-2010 |
Chris Lattner <sabre@nondot.org> |
reimplement ppc asmprinter "toc" handling to use a VariantKind
on the operand, required for .o file writing and fixing
the PowerPC/mult-alt-generic-powerpc64.ll failure with the new
instprinter.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@119087 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 9fa200d2a2360412465bbd6cfb485af2e9d5b1b4 |
|
27-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
remove a bogus pattern, which had the same pattern as STDU
but codegen'd differently. This really wanted to use some
sort of subreg to get the low 4 bytes of the G8RC register
or something. However, it's invalid and nothing is testing
it, so I'm just zapping the bogosity.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97345 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 9f036412ac6f66405f07259185bc63153fb8e059 |
|
21-Feb-2010 |
Chris Lattner <sabre@nondot.org> |
Eliminate some uses of immAllOnes, just use -1, it does
the same thing and is more efficient for the matcher.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96712 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 3a84dae654630a89a91a73807201b6067c4774ec |
|
18-Dec-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add support for calls through function pointers in the 64-bit PowerPC SVR4 ABI.
Patch contributed by Ken Werner of IBM!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91680 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 3d90dbee695e723f422dafca3fc75f193268ab9e |
|
04-Nov-2009 |
Bob Wilson <bob.wilson@apple.com> |
Add PowerPC codegen for indirect branches.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86050 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 533297b58da8c74bec65551e1aface9801fc2259 |
|
29-Oct-2009 |
Dan Gohman <gohman@apple.com> |
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@85517 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8dffc819c5f4326700262e7d1ff906d0d44ca906 |
|
18-Sep-2009 |
Dale Johannesen <dalej@apple.com> |
Model the carry bit on ppc32. Without this we could
move a SUBFC (etc.) below the SUBFE (etc.) that consumed
the carry bit. Add missing ADDIC8, noticed along the way.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@82266 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 6b16eff207f99bbde3c0f7340452a5287218772c |
|
15-Aug-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Add support for the PowerPC 64-bit SVR4 ABI.
The Link Register is volatile when using the 32-bit SVR4 ABI.
Make it possible to use the 64-bit SVR4 ABI.
Add non-volatile registers for the 64-bit SVR4 ABI.
Make sure r2 is a reserved register when using the 64-bit SVR4 ABI.
Update PPCFrameInfo for the 64-bit SVR4 ABI.
Add FIXME for 64-bit Darwin PPC.
Insert NOP instruction after direct function calls.
Emit official procedure descriptors.
Create TOC entries for GlobalAddress references.
Spill 64-bit non-volatile registers to the correct slots.
Only custom lower VAARG when using the 32-bit SVR4 ABI.
Use simple VASTART lowering for the 64-bit SVR4 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@79091 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 2a9ddfb903ae3baede7282348afae1f750905248 |
|
03-Jul-2009 |
Tilmann Scheller <tilmann.scheller@googlemail.com> |
Refactor ABI code in the PowerPC backend.
Make CalculateParameterAndLinkageAreaSize() Darwin-specific.
Remove SVR4 specific code from LowerCALL_Darwin() and LowerFORMAL_ARGUMENTS_Darwin().
Rename MachoABI to DarwinABI for consistency.
Rename ELF ABI to SVR4 ABI for consistency.
Factor out common call return lowering between the Darwin and SVR4 ABI.
Factor out common call lowering between the Darwin and SVR4 ABI.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@74766 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 15511cf1660cfd6bb8b8e8fca2db9450f50430ee |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Rename isSimpleLoad to canFoldAsLoad, to better reflect its meaning.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60487 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 41474baac839da410302950305722cb0e026a094 |
|
03-Dec-2008 |
Dan Gohman <gohman@apple.com> |
Add a sanity-check to tablegen to catch the case where isSimpleLoad
is set but mayLoad is not set. Fix all the problems this turned up.
Change code to not use isSimpleLoad instead of mayLoad unless it
really wants isSimpleLoad.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60459 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| b384ab9ea113ad22a9c7034b98060c7470f0dcc5 |
|
29-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Add a RM pseudoreg for the rounding mode, which
allows ppcf128->int conversion to work with
DeadInstructionElimination. This is now turned
off but RM is harmless. It does not do a complete
job of modeling the rounding mode.
Revert marking MFCR as using all 7 CR subregisters;
while correct, this caused the problem in PR 2964,
plus the local RA crash noted in the comments.
This was needed to make DeadInstructionElimination,
but as we are not running that, it is backed out
for now. Eventually it should go back in and the
other problems fixed where they're broken.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58391 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 639076fb84ab02e75d39415bd426a6a576ddef62 |
|
23-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Mark defs and uses of CTR and LR correctly.
Prevents DeadMachineInstructionElim from thinking
things like MTCTR are dead (fixes massive
testsuite breakage at -O0).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58043 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| f5aeb1a8e4cf272c7348376d185ef8d8267653e0 |
|
12-Sep-2008 |
Dan Gohman <gohman@apple.com> |
Rename ConstantSDNode::getValue to getZExtValue, for consistency
with ConstantInt. This led to fixing a bug in TargetLowering.cpp
using getValue instead of getAPIntValue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@56159 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| bdab93a2ef5d9574bb4e322e020849f9bc9c90d7 |
|
26-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Implement 32 & 64 bit versions of PPC atomic
binary primitives.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55343 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 140a8bb00640a5af4ae29516ac7c18c22f75c2be |
|
25-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Remove PPC-specific lowering for atomics; the
generic stuff works fine.
Mark rewritten cmp-and-swap as not using CR1.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55336 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 5f0cfa299d16e6d43577317176cab1a463c912da |
|
22-Aug-2008 |
Dale Johannesen <dalej@apple.com> |
Rewrite ppc code generated for __sync_{bool|val}_compare_and_swap
so that lwarx and stwcx are always executed the same number of times.
This is important for performance, I'm told.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55163 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 5330192ab59d65f285799ff5a9acd67d27417a56 |
|
12-Jul-2008 |
Evan Cheng <evan.cheng@apple.com> |
Implement llvm.atomic.cmp.swap.i32 on PPC. Patch by Gary Benson!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53505 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 30e62c098b5841259f8026df1c5c45c7c1182a38 |
|
30-Apr-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8608f2eff2dab5345243c40d0bca9138f2dce6f1 |
|
19-Apr-2008 |
Evan Cheng <evan.cheng@apple.com> |
64-bit atomic operations.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@49949 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| da47e6e0d003c873da960361549e57ee4617c301 |
|
15-Mar-2008 |
Evan Cheng <evan.cheng@apple.com> |
Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| af8ee84fe5a0d61db29f5489352f98d13842729c |
|
07-Mar-2008 |
Chris Lattner <sabre@nondot.org> |
Add support for ppc64 shifts with 7-bit (oversized) shift amount (e.g. PPCshl).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48027 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 834f1ce0312e3d00d836f9560cb63182c2c4570f |
|
07-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 2e48a70b35635165703838fc8d3796b664207aa1 |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
rename isStore -> mayStore to more accurately reflect what it captures.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45656 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| c8478d8b12c2d7e4cea32d0c9940f5cac2baa4dd |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
Change the 'isStore' inferrer to look for 'SDNPMayStore'
instead of "ISD::STORE". This allows us to mark target-specific dag
nodes as storing (such as ppc byteswap stores). This allows us to remove
more explicit isStore flags from the .td files.
Finally, add a warning for when a .td file contains an explicit
isStore and tblgen is able to infer it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 9c9fbf8e9c48f40d53cb434347d18395d9e0e02c |
|
06-Jan-2008 |
Chris Lattner <sabre@nondot.org> |
remove some isStore flags that are now inferred automatically.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 4ee451de366474b9c228b4e5fa573795a715216d |
|
29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 152b7e18748f7e06a93260f22cc9dac8eb3abee2 |
|
23-Oct-2007 |
Evan Cheng <evan.cheng@apple.com> |
Temporary solution: added a different set of BCTRL_Macho / BCTRL_ELF with right callee-saved defs set for ppc64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43248 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 071a279e94e30d51aff3b46a4651d686982488a0 |
|
11-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 67c906dce729d64861af8ca708f5e19d6a058b35 |
|
04-Sep-2007 |
Evan Cheng <evan.cheng@apple.com> |
Fix for PR1613: added 64-bit rotate left PPC instructions and patterns.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41711 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| caf778ab3b57f978d430ff9f56cfa7d2dec5aabb |
|
02-Aug-2007 |
Evan Cheng <evan.cheng@apple.com> |
Some out operands were incorrectly specified as input operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40697 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| ffbaccae029ac238972e3814967260f029b6058a |
|
21-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
No more noResults.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| d5f181a665be91d58019f3dbffedc8ebe49e6b9d |
|
20-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Oops. These stores actually produce results.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40074 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 64d80e3387f328d21cd9cc06464b5de7861e3f27 |
|
19-Jul-2007 |
Evan Cheng <evan.cheng@apple.com> |
Change instruction description to split OperandList into OutOperandList and
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
"add{l} {$src2, $dst|$dst, $src2}",
[(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| ccde4cb8ab6ba78296ffa0cb261757cd9cacb18a |
|
17-May-2007 |
Chris Lattner <sabre@nondot.org> |
add support for 128-bit add/sub on ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37158 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| ec58d9f9ddfbfe16ea40822164f340b256c89191 |
|
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| ef3c030e0e08b7d9446445823f4972fcf18c1ce1 |
|
03-Apr-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
The ELF ABI specifies F1-F8 registers as argument registers for double, not
F1-F10. This affects only ELF, not MachO.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35622 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| b6ead97b7e576721f47a3bc3739fea52f261e22f |
|
25-Mar-2007 |
Chris Lattner <sabre@nondot.org> |
Fix CodeGen/PowerPC/2007-03-24-cntlzd.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35329 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 63f8fb1993bf2b4286c5a6763e2eee414a751699 |
|
27-Feb-2007 |
Nicolas Geoffray <nicolas.geoffray@lip6.fr> |
Differentiate between the MachO and the ELF ABI the CALL instruction.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34667 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 1fa3d9ef93578970b2e0506104b96c3ffaa42bcf |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
one important bugfix: PPC32 didn't have both elf and macho support for
external symbols and global addresses. Add the missing ones.
one important workaround: PPCISD::CALL is matched by both PPCcall_ELF
and PPCcall_Macho, disable the _ELF patterns for now.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34601 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 9f0bc659c8d2f1e401a9690e4900b0fd2a70bdfe |
|
25-Feb-2007 |
Chris Lattner <sabre@nondot.org> |
implement support for the linux/ppc function call ABI. Patch by
Nicolas Geoffray!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34574 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| ba74cdf7f6044de319e118c28c84e076b421376f |
|
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Patterns no longer needed due to fix in the DAG combiner.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32612 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 352235515ff58d8a250797c62aebb4767b3b229f |
|
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Not all test cases are created equal. This fix is needed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32605 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 182a5acdeb58db5467c08c34f1db42af47b0c44c |
|
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Not needed. Misinterpreted error message from other bug (Missing load/store
relocations.)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32604 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| c4a81dc9357987bd0f4a4dc1593e8f38d6567fbd |
|
15-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Provide 64-bit support for i64 sextload<i8>.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32600 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 78f97f3118c0d7fbebf4084e24689c596d5e4fb7 |
|
12-Dec-2006 |
Jim Laskey <jlaskey@mac.com> |
Reduce number of instructions to load 64-bit constants.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32481 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 94c96cc5197f527a8cb9f953be3a2e8f2f5aa9e3 |
|
06-Dec-2006 |
Chris Lattner <sabre@nondot.org> |
implement sextinreg i8->i64 and i16->i64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@32293 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 2f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173 |
|
16-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
This is a general clean up of the PowerPC ABI. Address several problems and
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 1b0a2d8370b28de0d3998b0303bc3dad983989d9 |
|
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
fix a regression that I introduced. stdu should scale the offset by 4
before printing it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31791 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 80df01d2cf68b680b1c90eb0d3b0f2defcdf202b |
|
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
add ppc64 r+i stores with update.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31776 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8e28b5c4265ea636e5b737d9352096498be28d3b |
|
16-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Stop using isTwoAddress, switching to operand constraints instead.
Tell the codegen emitter that specific operands are not to be encoded, fixing
JIT regressions w.r.t. pre-inc loads and stores (e.g. lwzu, which we generate
even when general preinc loads are not enabled).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31770 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 0851b4f3eda110cc21c8d4b59f0d55bc84d9d088 |
|
15-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
fix ldu/stu jit encoding. Swith 64-bit preinc load instrs to use memri
addrmodes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31757 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 5e14b821cdab1fa42baeb2ed1f663597d8345824 |
|
15-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Fix the PPC regressions last night
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31752 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 6a5339ba656805a9cd3bf7d884f99bb87ec84e98 |
|
14-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Rework PPC64 calls. Now we have a LR8/CTR8 register which the PPC64 calls
clobber. This allows LR8 to be save/restored correctly as a 64-bit quantity,
instead of handling it as a 32-bit quantity. This unbreaks ppc64 codegen when
the code is actually located above the 4G boundary.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31734 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| a94a203f346e65d40c4c3fe478c5d8d7a2ff5df6 |
|
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
implement proper PPC64 prolog/epilog codegen.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| d181c0120c6c82a6b5370e4d3040b803093e169b |
|
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
Mark operands as symbol lo instead of imm32 so that they print lo(x) around
globals.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31672 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 94e509caeab08edb27849ea9be5dc80e74d95f38 |
|
11-Nov-2006 |
Chris Lattner <sabre@nondot.org> |
implement preinc support for r+i loads on ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31654 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 8b2794aeff151be8cdbd44786c1d0f94f8f2e427 |
|
13-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30945 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 466685d41a9ea4905b9486fea38e83802e46f196 |
|
09-Oct-2006 |
Evan Cheng <evan.cheng@apple.com> |
Reflects ISD::LOAD / ISD::LOADX / LoadSDNode changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30844 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 7c395ad06f0eaaffa638da58899b51daba2041a4 |
|
28-Sep-2006 |
Chris Lattner <sabre@nondot.org> |
Shift amounts are always 32-bits, even in 64-bit mode. This fixes
CodeGen/PowerPC/2006-09-28-shift_64.ll
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@30652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 303c695529f58ec12f7c31a6406c560cd23cc4f2 |
|
18-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Make the implicit def instructions look like other instrs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29174 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 518f9c7ad0566a69886a4db1b76e995df22bca0f |
|
14-Jul-2006 |
Chris Lattner <sabre@nondot.org> |
Add missing PPC64 extload/truncstores
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| cccef1c6fffa292c227a289d447f6b848ab56c62 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Don't match 64-bit bitfield inserts into rlwimi's. todo add rldimi. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28944 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| e4172be9209a81a41cbea97b9307e368e7e3ea4c |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add a pattern for i64 sra. Print 8-byte units with a space between the .quad
and the data
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28934 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 2e6b77d8035459c17d7f0b7055e579a0d9090bdd |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add 64-bit MTCTR so that indirect calls work.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28931 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 1fd81107f3b0d8c5cea1c4f66f7bddbc61e76a19 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Fix an incorrect store pattern. This fixes em3d.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 563ecfbf8207ce941ddc0ee60c65378c6b9c572f |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Implement 64-bit undef, sub, shl/shr, srem/urem
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28929 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 00659b17817b3b5af4d9e9b93fed2a91fe27b019 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add zextload from i32 -> i64, with this, perimeter works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28926 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 041e9d345f57249e5d9fad21514778c0ba5633b6 |
|
27-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Rearrange compares, add ADDI8, add sext from 32-to-64 bit register
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28920 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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| b410dc99774d52b4491750dab10b91cca1d661d8 |
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21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Rename OR4 -> OR. Move some PPC64-specific stuff to the 64-bit file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28889 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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| f2c5bca165fa654ad46f2b232773b2116b734b63 |
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21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
add some logical ops
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28887 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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| 3ae5eef0278db0cff59f714ab4b2124ec31b942e |
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21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add some more immediate patterns. This allows us to compile:
void test6() {
Y = 0xABCD0123BCDE4567;
}
into:
_test6:
lis r2, -21555
lis r3, ha16(_Y)
ori r2, r2, 291
rldicr r2, r2, 32, 31
oris r2, r2, 48350
ori r2, r2, 17767
std r2, lo16(_Y)(r3)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28885 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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| eded521a17fa2b39f6b1f9af5943036312bb3149 |
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21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Instead of li/xoris use li/oris. Note that this doesn't work if bit 15 is
set, so disable the pattern in that case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28884 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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| 0ea70b219a8408a25eaa522cbfc7e09f6dbc9d87 |
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21-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add some 64-bit logical ops.
Split imm16Shifted into a sext/zext form for 64-bit support.
Add some patterns for immediate formation. For example, we now compile this:
static unsigned long long Y;
void test3() {
Y = 0xF0F00F00;
}
into:
_test3:
li r2, 3840
lis r3, ha16(_Y)
xoris r2, r2, 61680
std r2, lo16(_Y)(r3)
blr
GCC produces:
_test3:
li r0,0
lis r2,ha16(_Y)
ori r0,r0,61680
sldi r0,r0,16
ori r0,r0,3840
std r0,lo16(_Y)(r2)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28883 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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| f27bb6de10b8a1b4b2e52b137ffda68c6ba0b9f4 |
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20-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add some patterns for globals, so we can now compile this:
static unsigned long long X, Y;
void test1() {
X = Y;
}
into:
_test1:
lis r2, ha16(_Y)
lis r3, ha16(_X)
ld r2, lo16(_Y)(r2)
std r2, lo16(_X)(r3)
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28879 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 047854f2b7a3f070f1bf4e5c24be2fc597bc544e |
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20-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Add some patterns for ppc64
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28866 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
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| a24b7618f8a64976a5846c97261b2b5fb92da23e |
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16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Upgrade some load/store instructions to use the proper addressing mode stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28841 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 059ca0f5b712e5460dcbccfa802b7adb3bccbac9 |
|
16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
fix some assumptions that pointers can only be 32-bits. With this, we can
now compile:
static unsigned long X;
void test1() {
X = 0;
}
into:
_test1:
lis r2, ha16(_X)
li r3, 0
stw r3, lo16(_X)(r2)
blr
Totally amazing :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28839 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|
| 956f43c3109f207bb91ef5f5a3cb12303ed28f8c |
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16-Jun-2006 |
Chris Lattner <sabre@nondot.org> |
Split 64-bit instructions out into a separate .td file
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28838 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCInstr64Bit.td
|