PPCInstr64Bit.td revision ac81cc3282750d724f824547bc519caec0a01bce
1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20} 21def u16imm64 : Operand<i64> { 22 let PrintMethod = "printU16ImmOperand"; 23} 24def symbolHi64 : Operand<i64> { 25 let PrintMethod = "printSymbolHi"; 26 let EncoderMethod = "getHA16Encoding"; 27} 28def symbolLo64 : Operand<i64> { 29 let PrintMethod = "printSymbolLo"; 30 let EncoderMethod = "getLO16Encoding"; 31} 32 33//===----------------------------------------------------------------------===// 34// 64-bit transformation functions. 35// 36 37def SHL64 : SDNodeXForm<imm, [{ 38 // Transformation function: 63 - imm 39 return getI32Imm(63 - N->getZExtValue()); 40}]>; 41 42def SRL64 : SDNodeXForm<imm, [{ 43 // Transformation function: 64 - imm 44 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 45}]>; 46 47def HI32_48 : SDNodeXForm<imm, [{ 48 // Transformation function: shift the immediate value down into the low bits. 49 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 50}]>; 51 52def HI48_64 : SDNodeXForm<imm, [{ 53 // Transformation function: shift the immediate value down into the low bits. 54 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 55}]>; 56 57 58//===----------------------------------------------------------------------===// 59// Calls. 60// 61 62let Defs = [LR8] in 63 def MovePCtoLR8 : Pseudo<(outs), (ins), "", []>, 64 PPC970_Unit_BRU; 65 66// Darwin ABI Calls. 67let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 68 // Convenient aliases for call instructions 69 let Uses = [RM] in { 70 def BL8_Darwin : IForm<18, 0, 1, 71 (outs), (ins calltarget:$func, variable_ops), 72 "bl $func", BrB, []>; // See Pat patterns below. 73 def BLA8_Darwin : IForm<18, 1, 1, 74 (outs), (ins aaddr:$func, variable_ops), 75 "bla $func", BrB, [(PPCcall_Darwin (i64 imm:$func))]>; 76 } 77 let Uses = [CTR8, RM] in { 78 def BCTRL8_Darwin : XLForm_2_ext<19, 528, 20, 0, 1, 79 (outs), (ins variable_ops), 80 "bctrl", BrB, 81 [(PPCbctrl_Darwin)]>, Requires<[In64BitMode]>; 82 } 83} 84 85// ELF 64 ABI Calls = Darwin ABI Calls 86// Used to define BL8_ELF and BLA8_ELF 87let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 88 // Convenient aliases for call instructions 89 let Uses = [RM] in { 90 def BL8_ELF : IForm<18, 0, 1, 91 (outs), (ins calltarget:$func, variable_ops), 92 "bl $func", BrB, []>; // See Pat patterns below. 93 94 let isCodeGenOnly = 1 in 95 def BL8_NOP_ELF : IForm_and_DForm_4_zero<18, 0, 1, 24, 96 (outs), (ins calltarget:$func, variable_ops), 97 "bl $func\n\tnop", BrB, []>; 98 99 def BLA8_ELF : IForm<18, 1, 1, 100 (outs), (ins aaddr:$func, variable_ops), 101 "bla $func", BrB, [(PPCcall_SVR4 (i64 imm:$func))]>; 102 103 let isCodeGenOnly = 1 in 104 def BLA8_NOP_ELF : IForm_and_DForm_4_zero<18, 1, 1, 24, 105 (outs), (ins aaddr:$func, variable_ops), 106 "bla $func\n\tnop", BrB, 107 [(PPCcall_nop_SVR4 (i64 imm:$func))]>; 108 } 109 let Uses = [X11, CTR8, RM] in { 110 def BCTRL8_ELF : XLForm_2_ext<19, 528, 20, 0, 1, 111 (outs), (ins variable_ops), 112 "bctrl", BrB, 113 [(PPCbctrl_SVR4)]>, Requires<[In64BitMode]>; 114 } 115} 116 117 118// Calls 119def : Pat<(PPCcall_Darwin (i64 tglobaladdr:$dst)), 120 (BL8_Darwin tglobaladdr:$dst)>; 121def : Pat<(PPCcall_Darwin (i64 texternalsym:$dst)), 122 (BL8_Darwin texternalsym:$dst)>; 123 124def : Pat<(PPCcall_SVR4 (i64 tglobaladdr:$dst)), 125 (BL8_ELF tglobaladdr:$dst)>; 126def : Pat<(PPCcall_nop_SVR4 (i64 tglobaladdr:$dst)), 127 (BL8_NOP_ELF tglobaladdr:$dst)>; 128 129def : Pat<(PPCcall_SVR4 (i64 texternalsym:$dst)), 130 (BL8_ELF texternalsym:$dst)>; 131def : Pat<(PPCcall_nop_SVR4 (i64 texternalsym:$dst)), 132 (BL8_NOP_ELF texternalsym:$dst)>; 133 134def : Pat<(PPCnop), 135 (NOP)>; 136 137// Atomic operations 138let usesCustomInserter = 1 in { 139 let Defs = [CR0] in { 140 def ATOMIC_LOAD_ADD_I64 : Pseudo< 141 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 142 [(set G8RC:$dst, (atomic_load_add_64 xoaddr:$ptr, G8RC:$incr))]>; 143 def ATOMIC_LOAD_SUB_I64 : Pseudo< 144 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 145 [(set G8RC:$dst, (atomic_load_sub_64 xoaddr:$ptr, G8RC:$incr))]>; 146 def ATOMIC_LOAD_OR_I64 : Pseudo< 147 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 148 [(set G8RC:$dst, (atomic_load_or_64 xoaddr:$ptr, G8RC:$incr))]>; 149 def ATOMIC_LOAD_XOR_I64 : Pseudo< 150 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 151 [(set G8RC:$dst, (atomic_load_xor_64 xoaddr:$ptr, G8RC:$incr))]>; 152 def ATOMIC_LOAD_AND_I64 : Pseudo< 153 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 154 [(set G8RC:$dst, (atomic_load_and_64 xoaddr:$ptr, G8RC:$incr))]>; 155 def ATOMIC_LOAD_NAND_I64 : Pseudo< 156 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$incr), "", 157 [(set G8RC:$dst, (atomic_load_nand_64 xoaddr:$ptr, G8RC:$incr))]>; 158 159 def ATOMIC_CMP_SWAP_I64 : Pseudo< 160 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$old, G8RC:$new), "", 161 [(set G8RC:$dst, 162 (atomic_cmp_swap_64 xoaddr:$ptr, G8RC:$old, G8RC:$new))]>; 163 164 def ATOMIC_SWAP_I64 : Pseudo< 165 (outs G8RC:$dst), (ins memrr:$ptr, G8RC:$new), "", 166 [(set G8RC:$dst, (atomic_swap_64 xoaddr:$ptr, G8RC:$new))]>; 167 } 168} 169 170// Instructions to support atomic operations 171def LDARX : XForm_1<31, 84, (outs G8RC:$rD), (ins memrr:$ptr), 172 "ldarx $rD, $ptr", LdStLDARX, 173 [(set G8RC:$rD, (PPClarx xoaddr:$ptr))]>; 174 175let Defs = [CR0] in 176def STDCX : XForm_1<31, 214, (outs), (ins G8RC:$rS, memrr:$dst), 177 "stdcx. $rS, $dst", LdStSTDCX, 178 [(PPCstcx G8RC:$rS, xoaddr:$dst)]>, 179 isDOT; 180 181let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 182def TCRETURNdi8 :Pseudo< (outs), 183 (ins calltarget:$dst, i32imm:$offset, variable_ops), 184 "#TC_RETURNd8 $dst $offset", 185 []>; 186 187let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 188def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset, variable_ops), 189 "#TC_RETURNa8 $func $offset", 190 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 191 192let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 193def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset, variable_ops), 194 "#TC_RETURNr8 $dst $offset", 195 []>; 196 197 198let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 199 isIndirectBranch = 1, isCall = 1, Uses = [CTR8, RM] in { 200 let isReturn = 1 in { 201 def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 202 Requires<[In64BitMode]>; 203 } 204 205 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 206 Requires<[In64BitMode]>; 207} 208 209 210let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 211 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 212def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 213 "b $dst", BrB, 214 []>; 215 216 217let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 218 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 219def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 220 "ba $dst", BrB, 221 []>; 222 223def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 224 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 225 226def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 227 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 228 229def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 230 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 231 232let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 233 let Defs = [CTR8], Uses = [CTR8] in { 234 def BDZ8 : IForm_ext<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 235 "bdz $dst", BrB, []>; 236 def BDNZ8 : IForm_ext<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 237 "bdnz $dst", BrB, []>; 238 } 239} 240 241// 64-but CR instructions 242def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins G8RC:$rS), 243 "mtcrf $FXM, $rS", BrMCRX>, 244 PPC970_MicroCode, PPC970_Unit_CRU; 245 246def MFCR8pseud: XFXForm_3<31, 19, (outs G8RC:$rT), (ins crbitm:$FXM), 247 "", SprMFCR>, 248 PPC970_MicroCode, PPC970_Unit_CRU; 249 250def MFCR8 : XFXForm_3<31, 19, (outs G8RC:$rT), (ins), 251 "mfcr $rT", SprMFCR>, 252 PPC970_MicroCode, PPC970_Unit_CRU; 253 254//===----------------------------------------------------------------------===// 255// 64-bit SPR manipulation instrs. 256 257let Uses = [CTR8] in { 258def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs G8RC:$rT), (ins), 259 "mfctr $rT", SprMFSPR>, 260 PPC970_DGroup_First, PPC970_Unit_FXU; 261} 262let Pattern = [(PPCmtctr G8RC:$rS)], Defs = [CTR8] in { 263def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins G8RC:$rS), 264 "mtctr $rS", SprMTSPR>, 265 PPC970_DGroup_First, PPC970_Unit_FXU; 266} 267 268let Defs = [X1], Uses = [X1] in 269def DYNALLOC8 : Pseudo<(outs G8RC:$result), (ins G8RC:$negsize, memri:$fpsi),"", 270 [(set G8RC:$result, 271 (PPCdynalloc G8RC:$negsize, iaddr:$fpsi))]>; 272 273let Defs = [LR8] in { 274def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins G8RC:$rS), 275 "mtlr $rS", SprMTSPR>, 276 PPC970_DGroup_First, PPC970_Unit_FXU; 277} 278let Uses = [LR8] in { 279def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs G8RC:$rT), (ins), 280 "mflr $rT", SprMFSPR>, 281 PPC970_DGroup_First, PPC970_Unit_FXU; 282} 283 284//===----------------------------------------------------------------------===// 285// Fixed point instructions. 286// 287 288let PPC970_Unit = 1 in { // FXU Operations. 289 290def LI8 : DForm_2_r0<14, (outs G8RC:$rD), (ins symbolLo64:$imm), 291 "li $rD, $imm", IntSimple, 292 [(set G8RC:$rD, immSExt16:$imm)]>; 293def LIS8 : DForm_2_r0<15, (outs G8RC:$rD), (ins symbolHi64:$imm), 294 "lis $rD, $imm", IntSimple, 295 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 296 297// Logical ops. 298def NAND8: XForm_6<31, 476, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 299 "nand $rA, $rS, $rB", IntSimple, 300 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 301def AND8 : XForm_6<31, 28, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 302 "and $rA, $rS, $rB", IntSimple, 303 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 304def ANDC8: XForm_6<31, 60, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 305 "andc $rA, $rS, $rB", IntSimple, 306 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 307def OR8 : XForm_6<31, 444, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 308 "or $rA, $rS, $rB", IntSimple, 309 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 310def NOR8 : XForm_6<31, 124, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 311 "nor $rA, $rS, $rB", IntSimple, 312 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 313def ORC8 : XForm_6<31, 412, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 314 "orc $rA, $rS, $rB", IntSimple, 315 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 316def EQV8 : XForm_6<31, 284, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 317 "eqv $rA, $rS, $rB", IntSimple, 318 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 319def XOR8 : XForm_6<31, 316, (outs G8RC:$rA), (ins G8RC:$rS, G8RC:$rB), 320 "xor $rA, $rS, $rB", IntSimple, 321 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 322 323// Logical ops with immediate. 324def ANDIo8 : DForm_4<28, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 325 "andi. $dst, $src1, $src2", IntGeneral, 326 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 327 isDOT; 328def ANDISo8 : DForm_4<29, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 329 "andis. $dst, $src1, $src2", IntGeneral, 330 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 331 isDOT; 332def ORI8 : DForm_4<24, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 333 "ori $dst, $src1, $src2", IntSimple, 334 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 335def ORIS8 : DForm_4<25, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 336 "oris $dst, $src1, $src2", IntSimple, 337 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 338def XORI8 : DForm_4<26, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 339 "xori $dst, $src1, $src2", IntSimple, 340 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 341def XORIS8 : DForm_4<27, (outs G8RC:$dst), (ins G8RC:$src1, u16imm:$src2), 342 "xoris $dst, $src1, $src2", IntSimple, 343 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 344 345def ADD8 : XOForm_1<31, 266, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 346 "add $rT, $rA, $rB", IntSimple, 347 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 348 349let Defs = [CARRY] in { 350def ADDC8 : XOForm_1<31, 10, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 351 "addc $rT, $rA, $rB", IntGeneral, 352 [(set G8RC:$rT, (addc G8RC:$rA, G8RC:$rB))]>, 353 PPC970_DGroup_Cracked; 354def ADDIC8 : DForm_2<12, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 355 "addic $rD, $rA, $imm", IntGeneral, 356 [(set G8RC:$rD, (addc G8RC:$rA, immSExt16:$imm))]>; 357} 358def ADDI8 : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 359 "addi $rD, $rA, $imm", IntSimple, 360 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 361def ADDI8L : DForm_2<14, (outs G8RC:$rD), (ins G8RC:$rA, symbolLo64:$imm), 362 "addi $rD, $rA, $imm", IntSimple, 363 [(set G8RC:$rD, (add G8RC:$rA, immSExt16:$imm))]>; 364def ADDIS8 : DForm_2<15, (outs G8RC:$rD), (ins G8RC:$rA, symbolHi64:$imm), 365 "addis $rD, $rA, $imm", IntSimple, 366 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 367 368let Defs = [CARRY] in { 369def SUBFIC8: DForm_2< 8, (outs G8RC:$rD), (ins G8RC:$rA, s16imm64:$imm), 370 "subfic $rD, $rA, $imm", IntGeneral, 371 [(set G8RC:$rD, (subc immSExt16:$imm, G8RC:$rA))]>; 372def SUBFC8 : XOForm_1<31, 8, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 373 "subfc $rT, $rA, $rB", IntGeneral, 374 [(set G8RC:$rT, (subc G8RC:$rB, G8RC:$rA))]>, 375 PPC970_DGroup_Cracked; 376} 377def SUBF8 : XOForm_1<31, 40, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 378 "subf $rT, $rA, $rB", IntGeneral, 379 [(set G8RC:$rT, (sub G8RC:$rB, G8RC:$rA))]>; 380def NEG8 : XOForm_3<31, 104, 0, (outs G8RC:$rT), (ins G8RC:$rA), 381 "neg $rT, $rA", IntSimple, 382 [(set G8RC:$rT, (ineg G8RC:$rA))]>; 383let Uses = [CARRY], Defs = [CARRY] in { 384def ADDE8 : XOForm_1<31, 138, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 385 "adde $rT, $rA, $rB", IntGeneral, 386 [(set G8RC:$rT, (adde G8RC:$rA, G8RC:$rB))]>; 387def ADDME8 : XOForm_3<31, 234, 0, (outs G8RC:$rT), (ins G8RC:$rA), 388 "addme $rT, $rA", IntGeneral, 389 [(set G8RC:$rT, (adde G8RC:$rA, -1))]>; 390def ADDZE8 : XOForm_3<31, 202, 0, (outs G8RC:$rT), (ins G8RC:$rA), 391 "addze $rT, $rA", IntGeneral, 392 [(set G8RC:$rT, (adde G8RC:$rA, 0))]>; 393def SUBFE8 : XOForm_1<31, 136, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 394 "subfe $rT, $rA, $rB", IntGeneral, 395 [(set G8RC:$rT, (sube G8RC:$rB, G8RC:$rA))]>; 396def SUBFME8 : XOForm_3<31, 232, 0, (outs G8RC:$rT), (ins G8RC:$rA), 397 "subfme $rT, $rA", IntGeneral, 398 [(set G8RC:$rT, (sube -1, G8RC:$rA))]>; 399def SUBFZE8 : XOForm_3<31, 200, 0, (outs G8RC:$rT), (ins G8RC:$rA), 400 "subfze $rT, $rA", IntGeneral, 401 [(set G8RC:$rT, (sube 0, G8RC:$rA))]>; 402} 403 404 405def MULHD : XOForm_1<31, 73, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 406 "mulhd $rT, $rA, $rB", IntMulHW, 407 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 408def MULHDU : XOForm_1<31, 9, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 409 "mulhdu $rT, $rA, $rB", IntMulHWU, 410 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 411 412def CMPD : XForm_16_ext<31, 0, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 413 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 414def CMPLD : XForm_16_ext<31, 32, (outs CRRC:$crD), (ins G8RC:$rA, G8RC:$rB), 415 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 416def CMPDI : DForm_5_ext<11, (outs CRRC:$crD), (ins G8RC:$rA, s16imm:$imm), 417 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 418def CMPLDI : DForm_6_ext<10, (outs CRRC:$dst), (ins G8RC:$src1, u16imm:$src2), 419 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 420 421def SLD : XForm_6<31, 27, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 422 "sld $rA, $rS, $rB", IntRotateD, 423 [(set G8RC:$rA, (PPCshl G8RC:$rS, GPRC:$rB))]>, isPPC64; 424def SRD : XForm_6<31, 539, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 425 "srd $rA, $rS, $rB", IntRotateD, 426 [(set G8RC:$rA, (PPCsrl G8RC:$rS, GPRC:$rB))]>, isPPC64; 427let Defs = [CARRY] in { 428def SRAD : XForm_6<31, 794, (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB), 429 "srad $rA, $rS, $rB", IntRotateD, 430 [(set G8RC:$rA, (PPCsra G8RC:$rS, GPRC:$rB))]>, isPPC64; 431} 432 433def EXTSB8 : XForm_11<31, 954, (outs G8RC:$rA), (ins G8RC:$rS), 434 "extsb $rA, $rS", IntSimple, 435 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i8))]>; 436def EXTSH8 : XForm_11<31, 922, (outs G8RC:$rA), (ins G8RC:$rS), 437 "extsh $rA, $rS", IntSimple, 438 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i16))]>; 439 440def EXTSW : XForm_11<31, 986, (outs G8RC:$rA), (ins G8RC:$rS), 441 "extsw $rA, $rS", IntSimple, 442 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 443/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 444def EXTSW_32 : XForm_11<31, 986, (outs GPRC:$rA), (ins GPRC:$rS), 445 "extsw $rA, $rS", IntSimple, 446 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 447def EXTSW_32_64 : XForm_11<31, 986, (outs G8RC:$rA), (ins GPRC:$rS), 448 "extsw $rA, $rS", IntSimple, 449 [(set G8RC:$rA, (sext GPRC:$rS))]>, isPPC64; 450 451let Defs = [CARRY] in { 452def SRADI : XSForm_1<31, 413, (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH), 453 "sradi $rA, $rS, $SH", IntRotateD, 454 [(set G8RC:$rA, (sra G8RC:$rS, (i32 imm:$SH)))]>, isPPC64; 455} 456def CNTLZD : XForm_11<31, 58, (outs G8RC:$rA), (ins G8RC:$rS), 457 "cntlzd $rA, $rS", IntGeneral, 458 [(set G8RC:$rA, (ctlz G8RC:$rS))]>; 459 460def DIVD : XOForm_1<31, 489, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 461 "divd $rT, $rA, $rB", IntDivD, 462 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 463 PPC970_DGroup_First, PPC970_DGroup_Cracked; 464def DIVDU : XOForm_1<31, 457, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 465 "divdu $rT, $rA, $rB", IntDivD, 466 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 467 PPC970_DGroup_First, PPC970_DGroup_Cracked; 468def MULLD : XOForm_1<31, 233, 0, (outs G8RC:$rT), (ins G8RC:$rA, G8RC:$rB), 469 "mulld $rT, $rA, $rB", IntMulHD, 470 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 471 472 473let isCommutable = 1 in { 474def RLDIMI : MDForm_1<30, 3, 475 (outs G8RC:$rA), (ins G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 476 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 477 []>, isPPC64, RegConstraint<"$rSi = $rA">, 478 NoEncode<"$rSi">; 479} 480 481// Rotate instructions. 482def RLDCL : MDForm_1<30, 0, 483 (outs G8RC:$rA), (ins G8RC:$rS, GPRC:$rB, u6imm:$MB), 484 "rldcl $rA, $rS, $rB, $MB", IntRotateD, 485 []>, isPPC64; 486def RLDICL : MDForm_1<30, 0, 487 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$MB), 488 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 489 []>, isPPC64; 490def RLDICR : MDForm_1<30, 1, 491 (outs G8RC:$rA), (ins G8RC:$rS, u6imm:$SH, u6imm:$ME), 492 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 493 []>, isPPC64; 494 495def RLWINM8 : MForm_2<21, 496 (outs G8RC:$rA), (ins G8RC:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 497 "rlwinm $rA, $rS, $SH, $MB, $ME", IntGeneral, 498 []>; 499 500} // End FXU Operations. 501 502 503//===----------------------------------------------------------------------===// 504// Load/Store instructions. 505// 506 507 508// Sign extending loads. 509let canFoldAsLoad = 1, PPC970_Unit = 2 in { 510def LHA8: DForm_1<42, (outs G8RC:$rD), (ins memri:$src), 511 "lha $rD, $src", LdStLHA, 512 [(set G8RC:$rD, (sextloadi16 iaddr:$src))]>, 513 PPC970_DGroup_Cracked; 514def LWA : DSForm_1<58, 2, (outs G8RC:$rD), (ins memrix:$src), 515 "lwa $rD, $src", LdStLWA, 516 [(set G8RC:$rD, (sextloadi32 ixaddr:$src))]>, isPPC64, 517 PPC970_DGroup_Cracked; 518def LHAX8: XForm_1<31, 343, (outs G8RC:$rD), (ins memrr:$src), 519 "lhax $rD, $src", LdStLHA, 520 [(set G8RC:$rD, (sextloadi16 xaddr:$src))]>, 521 PPC970_DGroup_Cracked; 522def LWAX : XForm_1<31, 341, (outs G8RC:$rD), (ins memrr:$src), 523 "lwax $rD, $src", LdStLHA, 524 [(set G8RC:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 525 PPC970_DGroup_Cracked; 526 527// Update forms. 528let mayLoad = 1 in 529def LHAU8 : DForm_1a<43, (outs G8RC:$rD, ptr_rc:$ea_result), (ins symbolLo:$disp, 530 ptr_rc:$rA), 531 "lhau $rD, $disp($rA)", LdStLoad, 532 []>, RegConstraint<"$rA = $ea_result">, 533 NoEncode<"$ea_result">; 534// NO LWAU! 535 536} 537 538// Zero extending loads. 539let canFoldAsLoad = 1, PPC970_Unit = 2 in { 540def LBZ8 : DForm_1<34, (outs G8RC:$rD), (ins memri:$src), 541 "lbz $rD, $src", LdStLoad, 542 [(set G8RC:$rD, (zextloadi8 iaddr:$src))]>; 543def LHZ8 : DForm_1<40, (outs G8RC:$rD), (ins memri:$src), 544 "lhz $rD, $src", LdStLoad, 545 [(set G8RC:$rD, (zextloadi16 iaddr:$src))]>; 546def LWZ8 : DForm_1<32, (outs G8RC:$rD), (ins memri:$src), 547 "lwz $rD, $src", LdStLoad, 548 [(set G8RC:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 549 550def LBZX8 : XForm_1<31, 87, (outs G8RC:$rD), (ins memrr:$src), 551 "lbzx $rD, $src", LdStLoad, 552 [(set G8RC:$rD, (zextloadi8 xaddr:$src))]>; 553def LHZX8 : XForm_1<31, 279, (outs G8RC:$rD), (ins memrr:$src), 554 "lhzx $rD, $src", LdStLoad, 555 [(set G8RC:$rD, (zextloadi16 xaddr:$src))]>; 556def LWZX8 : XForm_1<31, 23, (outs G8RC:$rD), (ins memrr:$src), 557 "lwzx $rD, $src", LdStLoad, 558 [(set G8RC:$rD, (zextloadi32 xaddr:$src))]>; 559 560 561// Update forms. 562let mayLoad = 1 in { 563def LBZU8 : DForm_1<35, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 564 "lbzu $rD, $addr", LdStLoad, 565 []>, RegConstraint<"$addr.reg = $ea_result">, 566 NoEncode<"$ea_result">; 567def LHZU8 : DForm_1<41, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 568 "lhzu $rD, $addr", LdStLoad, 569 []>, RegConstraint<"$addr.reg = $ea_result">, 570 NoEncode<"$ea_result">; 571def LWZU8 : DForm_1<33, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memri:$addr), 572 "lwzu $rD, $addr", LdStLoad, 573 []>, RegConstraint<"$addr.reg = $ea_result">, 574 NoEncode<"$ea_result">; 575} 576} 577 578 579// Full 8-byte loads. 580let canFoldAsLoad = 1, PPC970_Unit = 2 in { 581def LD : DSForm_1<58, 0, (outs G8RC:$rD), (ins memrix:$src), 582 "ld $rD, $src", LdStLD, 583 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 584def LDtoc: Pseudo<(outs G8RC:$rD), (ins tocentry:$disp, G8RC:$reg), 585 "", 586 [(set G8RC:$rD, 587 (PPCtoc_entry tglobaladdr:$disp, G8RC:$reg))]>, isPPC64; 588 589let hasSideEffects = 1 in { 590let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 591def LDinto_toc: DSForm_1<58, 0, (outs), (ins G8RC:$reg), 592 "ld 2, 8($reg)", LdStLD, 593 [(PPCload_toc G8RC:$reg)]>, isPPC64; 594 595let RST = 2, DS_RA = 0 in // FIXME: Should be a pseudo. 596def LDtoc_restore : DSForm_1<58, 0, (outs), (ins), 597 "ld 2, 40(1)", LdStLD, 598 [(PPCtoc_restore)]>, isPPC64; 599} 600def LDX : XForm_1<31, 21, (outs G8RC:$rD), (ins memrr:$src), 601 "ldx $rD, $src", LdStLD, 602 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 603 604let mayLoad = 1 in 605def LDU : DSForm_1<58, 1, (outs G8RC:$rD, ptr_rc:$ea_result), (ins memrix:$addr), 606 "ldu $rD, $addr", LdStLD, 607 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 608 NoEncode<"$ea_result">; 609 610} 611 612def : Pat<(PPCload ixaddr:$src), 613 (LD ixaddr:$src)>; 614def : Pat<(PPCload xaddr:$src), 615 (LDX xaddr:$src)>; 616 617let PPC970_Unit = 2 in { 618// Truncating stores. 619def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src), 620 "stb $rS, $src", LdStStore, 621 [(truncstorei8 G8RC:$rS, iaddr:$src)]>; 622def STH8 : DForm_1<44, (outs), (ins G8RC:$rS, memri:$src), 623 "sth $rS, $src", LdStStore, 624 [(truncstorei16 G8RC:$rS, iaddr:$src)]>; 625def STW8 : DForm_1<36, (outs), (ins G8RC:$rS, memri:$src), 626 "stw $rS, $src", LdStStore, 627 [(truncstorei32 G8RC:$rS, iaddr:$src)]>; 628def STBX8 : XForm_8<31, 215, (outs), (ins G8RC:$rS, memrr:$dst), 629 "stbx $rS, $dst", LdStStore, 630 [(truncstorei8 G8RC:$rS, xaddr:$dst)]>, 631 PPC970_DGroup_Cracked; 632def STHX8 : XForm_8<31, 407, (outs), (ins G8RC:$rS, memrr:$dst), 633 "sthx $rS, $dst", LdStStore, 634 [(truncstorei16 G8RC:$rS, xaddr:$dst)]>, 635 PPC970_DGroup_Cracked; 636def STWX8 : XForm_8<31, 151, (outs), (ins G8RC:$rS, memrr:$dst), 637 "stwx $rS, $dst", LdStStore, 638 [(truncstorei32 G8RC:$rS, xaddr:$dst)]>, 639 PPC970_DGroup_Cracked; 640// Normal 8-byte stores. 641def STD : DSForm_1<62, 0, (outs), (ins G8RC:$rS, memrix:$dst), 642 "std $rS, $dst", LdStSTD, 643 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 644def STDX : XForm_8<31, 149, (outs), (ins G8RC:$rS, memrr:$dst), 645 "stdx $rS, $dst", LdStSTD, 646 [(store G8RC:$rS, xaddr:$dst)]>, isPPC64, 647 PPC970_DGroup_Cracked; 648} 649 650let PPC970_Unit = 2 in { 651 652def STBU8 : DForm_1a<38, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 653 symbolLo:$ptroff, ptr_rc:$ptrreg), 654 "stbu $rS, $ptroff($ptrreg)", LdStStore, 655 [(set ptr_rc:$ea_res, 656 (pre_truncsti8 G8RC:$rS, ptr_rc:$ptrreg, 657 iaddroff:$ptroff))]>, 658 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 659def STHU8 : DForm_1a<45, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 660 symbolLo:$ptroff, ptr_rc:$ptrreg), 661 "sthu $rS, $ptroff($ptrreg)", LdStStore, 662 [(set ptr_rc:$ea_res, 663 (pre_truncsti16 G8RC:$rS, ptr_rc:$ptrreg, 664 iaddroff:$ptroff))]>, 665 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 666 667def STWU8 : DForm_1a<37, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 668 symbolLo:$ptroff, ptr_rc:$ptrreg), 669 "stwu $rS, $ptroff($ptrreg)", LdStStore, 670 [(set ptr_rc:$ea_res, 671 (pre_truncsti32 G8RC:$rS, ptr_rc:$ptrreg, 672 iaddroff:$ptroff))]>, 673 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">; 674 675def STDU : DSForm_1a<62, 1, (outs ptr_rc:$ea_res), (ins G8RC:$rS, 676 s16immX4:$ptroff, ptr_rc:$ptrreg), 677 "stdu $rS, $ptroff($ptrreg)", LdStSTD, 678 [(set ptr_rc:$ea_res, (pre_store G8RC:$rS, ptr_rc:$ptrreg, 679 iaddroff:$ptroff))]>, 680 RegConstraint<"$ptrreg = $ea_res">, NoEncode<"$ea_res">, 681 isPPC64; 682 683 684def STBUX8 : XForm_8<31, 247, (outs ptr_rc:$ea_res), 685 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 686 "stbux $rS, $ptroff, $ptrreg", LdStStore, 687 [(set ptr_rc:$ea_res, 688 (pre_truncsti8 G8RC:$rS, 689 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 690 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 691 PPC970_DGroup_Cracked; 692 693def STHUX8 : XForm_8<31, 439, (outs ptr_rc:$ea_res), 694 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 695 "sthux $rS, $ptroff, $ptrreg", LdStStore, 696 [(set ptr_rc:$ea_res, 697 (pre_truncsti16 G8RC:$rS, 698 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 699 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 700 PPC970_DGroup_Cracked; 701 702def STWUX8 : XForm_8<31, 183, (outs ptr_rc:$ea_res), 703 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 704 "stwux $rS, $ptroff, $ptrreg", LdStStore, 705 [(set ptr_rc:$ea_res, 706 (pre_truncsti32 G8RC:$rS, 707 ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 708 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 709 PPC970_DGroup_Cracked; 710 711def STDUX : XForm_8<31, 181, (outs ptr_rc:$ea_res), 712 (ins G8RC:$rS, ptr_rc:$ptroff, ptr_rc:$ptrreg), 713 "stdux $rS, $ptroff, $ptrreg", LdStStore, 714 [(set ptr_rc:$ea_res, 715 (pre_store G8RC:$rS, ptr_rc:$ptrreg, xaddroff:$ptroff))]>, 716 RegConstraint<"$ptroff = $ea_res">, NoEncode<"$ea_res">, 717 PPC970_DGroup_Cracked, isPPC64; 718 719// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 720def STD_32 : DSForm_1<62, 0, (outs), (ins GPRC:$rT, memrix:$dst), 721 "std $rT, $dst", LdStSTD, 722 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 723def STDX_32 : XForm_8<31, 149, (outs), (ins GPRC:$rT, memrr:$dst), 724 "stdx $rT, $dst", LdStSTD, 725 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 726 PPC970_DGroup_Cracked; 727} 728 729 730 731//===----------------------------------------------------------------------===// 732// Floating point instructions. 733// 734 735 736let PPC970_Unit = 3, Uses = [RM] in { // FPU Operations. 737def FCFID : XForm_26<63, 846, (outs F8RC:$frD), (ins F8RC:$frB), 738 "fcfid $frD, $frB", FPGeneral, 739 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 740def FCTIDZ : XForm_26<63, 815, (outs F8RC:$frD), (ins F8RC:$frB), 741 "fctidz $frD, $frB", FPGeneral, 742 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 743} 744 745 746//===----------------------------------------------------------------------===// 747// Instruction Patterns 748// 749 750// Extensions and truncates to/from 32-bit regs. 751def : Pat<(i64 (zext GPRC:$in)), 752 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32), 753 0, 32)>; 754def : Pat<(i64 (anyext GPRC:$in)), 755 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GPRC:$in, sub_32)>; 756def : Pat<(i32 (trunc G8RC:$in)), 757 (EXTRACT_SUBREG G8RC:$in, sub_32)>; 758 759// Extending loads with i64 targets. 760def : Pat<(zextloadi1 iaddr:$src), 761 (LBZ8 iaddr:$src)>; 762def : Pat<(zextloadi1 xaddr:$src), 763 (LBZX8 xaddr:$src)>; 764def : Pat<(extloadi1 iaddr:$src), 765 (LBZ8 iaddr:$src)>; 766def : Pat<(extloadi1 xaddr:$src), 767 (LBZX8 xaddr:$src)>; 768def : Pat<(extloadi8 iaddr:$src), 769 (LBZ8 iaddr:$src)>; 770def : Pat<(extloadi8 xaddr:$src), 771 (LBZX8 xaddr:$src)>; 772def : Pat<(extloadi16 iaddr:$src), 773 (LHZ8 iaddr:$src)>; 774def : Pat<(extloadi16 xaddr:$src), 775 (LHZX8 xaddr:$src)>; 776def : Pat<(extloadi32 iaddr:$src), 777 (LWZ8 iaddr:$src)>; 778def : Pat<(extloadi32 xaddr:$src), 779 (LWZX8 xaddr:$src)>; 780 781// Standard shifts. These are represented separately from the real shifts above 782// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 783// amounts. 784def : Pat<(sra G8RC:$rS, GPRC:$rB), 785 (SRAD G8RC:$rS, GPRC:$rB)>; 786def : Pat<(srl G8RC:$rS, GPRC:$rB), 787 (SRD G8RC:$rS, GPRC:$rB)>; 788def : Pat<(shl G8RC:$rS, GPRC:$rB), 789 (SLD G8RC:$rS, GPRC:$rB)>; 790 791// SHL/SRL 792def : Pat<(shl G8RC:$in, (i32 imm:$imm)), 793 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 794def : Pat<(srl G8RC:$in, (i32 imm:$imm)), 795 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 796 797// ROTL 798def : Pat<(rotl G8RC:$in, GPRC:$sh), 799 (RLDCL G8RC:$in, GPRC:$sh, 0)>; 800def : Pat<(rotl G8RC:$in, (i32 imm:$imm)), 801 (RLDICL G8RC:$in, imm:$imm, 0)>; 802 803// Hi and Lo for Darwin Global Addresses. 804def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 805def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 806def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 807def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 808def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 809def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 810def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 811def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 812def : Pat<(PPChi tglobaltlsaddr:$g, G8RC:$in), 813 (ADDIS8 G8RC:$in, tglobaltlsaddr:$g)>; 814def : Pat<(PPClo tglobaltlsaddr:$g, G8RC:$in), 815 (ADDI8L G8RC:$in, tglobaltlsaddr:$g)>; 816def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 817 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 818def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 819 (ADDIS8 G8RC:$in, tconstpool:$g)>; 820def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 821 (ADDIS8 G8RC:$in, tjumptable:$g)>; 822def : Pat<(add G8RC:$in, (PPChi tblockaddress:$g, 0)), 823 (ADDIS8 G8RC:$in, tblockaddress:$g)>; 824