PPCInstr64Bit.td revision b410dc99774d52b4491750dab10b91cca1d661d8
1//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def symbolHi64 : Operand<i64> { 19 let PrintMethod = "printSymbolHi"; 20} 21def symbolLo64 : Operand<i64> { 22 let PrintMethod = "printSymbolLo"; 23} 24 25//===----------------------------------------------------------------------===// 26// 64-bit transformation functions. 27// 28 29def SHL64 : SDNodeXForm<imm, [{ 30 // Transformation function: 63 - imm 31 return getI32Imm(63 - N->getValue()); 32}]>; 33 34def SRL64 : SDNodeXForm<imm, [{ 35 // Transformation function: 64 - imm 36 return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0); 37}]>; 38 39def HI32_48 : SDNodeXForm<imm, [{ 40 // Transformation function: shift the immediate value down into the low bits. 41 return getI32Imm((unsigned short)(N->getValue() >> 32)); 42}]>; 43 44def HI48_64 : SDNodeXForm<imm, [{ 45 // Transformation function: shift the immediate value down into the low bits. 46 return getI32Imm((unsigned short)(N->getValue() >> 48)); 47}]>; 48 49 50//===----------------------------------------------------------------------===// 51// Fixed point instructions. 52// 53 54let PPC970_Unit = 1 in { // FXU Operations. 55 56// Copies, extends, truncates. 57def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB), 58 "or $rA, $rS, $rB", IntGeneral, 59 []>; 60def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB), 61 "or $rA, $rS, $rB", IntGeneral, 62 []>; 63 64def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm), 65 "li $rD, $imm", IntGeneral, 66 [(set G8RC:$rD, immSExt16:$imm)]>; 67def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm), 68 "lis $rD, $imm", IntGeneral, 69 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 70 71// Logical ops. 72def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 73 "nand $rA, $rS, $rB", IntGeneral, 74 [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>; 75def AND8 : XForm_6<31, 28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 76 "and $rA, $rS, $rB", IntGeneral, 77 [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>; 78def ANDC8: XForm_6<31, 60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 79 "andc $rA, $rS, $rB", IntGeneral, 80 [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>; 81def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 82 "or $rA, $rS, $rB", IntGeneral, 83 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 84def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 85 "nor $rA, $rS, $rB", IntGeneral, 86 [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>; 87def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 88 "orc $rA, $rS, $rB", IntGeneral, 89 [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>; 90def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 91 "eqv $rA, $rS, $rB", IntGeneral, 92 [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>; 93def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 94 "xor $rA, $rS, $rB", IntGeneral, 95 [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>; 96 97// Logical ops with immediate. 98def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 99 "andi. $dst, $src1, $src2", IntGeneral, 100 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 101 isDOT; 102def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 103 "andis. $dst, $src1, $src2", IntGeneral, 104 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 105 isDOT; 106def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 107 "ori $dst, $src1, $src2", IntGeneral, 108 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 109def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 110 "oris $dst, $src1, $src2", IntGeneral, 111 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 112def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 113 "xori $dst, $src1, $src2", IntGeneral, 114 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 115def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 116 "xoris $dst, $src1, $src2", IntGeneral, 117 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 118 119 120 121def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 122 "add $rT, $rA, $rB", IntGeneral, 123 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 124def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm), 125 "addis $rD, $rA, $imm", IntGeneral, 126 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 127 128 129 130 131def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 132 "mulhd $rT, $rA, $rB", IntMulHW, 133 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 134def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 135 "mulhdu $rT, $rA, $rB", IntMulHWU, 136 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 137 138def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 139 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 140 141def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 142 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 143def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 144 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 145def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 146 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 147 148def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 149 "sld $rA, $rS, $rB", IntRotateD, 150 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64; 151def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 152 "srd $rA, $rS, $rB", IntRotateD, 153 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64; 154def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 155 "srad $rA, $rS, $rB", IntRotateD, 156 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64; 157def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS), 158 "extsw $rA, $rS", IntGeneral, 159 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 160/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 161def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS), 162 "extsw $rA, $rS", IntGeneral, 163 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 164 165def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH), 166 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64; 167def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 168 "divd $rT, $rA, $rB", IntDivD, 169 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 170 PPC970_DGroup_First, PPC970_DGroup_Cracked; 171def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 172 "divdu $rT, $rA, $rB", IntDivD, 173 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 174 PPC970_DGroup_First, PPC970_DGroup_Cracked; 175def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 176 "mulld $rT, $rA, $rB", IntMulHD, 177 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 178 179let isTwoAddress = 1, isCommutable = 1 in { 180def RLDIMI : MDForm_1<30, 3, 181 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 182 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 183 []>, isPPC64; 184} 185 186// Rotate instructions. 187def RLDICL : MDForm_1<30, 0, 188 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB), 189 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 190 []>, isPPC64; 191def RLDICR : MDForm_1<30, 1, 192 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME), 193 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 194 []>, isPPC64; 195} 196 197 198//===----------------------------------------------------------------------===// 199// Load/Store instructions. 200// 201 202 203let isLoad = 1, PPC970_Unit = 2 in { 204def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src), 205 "lwa $rD, $src", LdStLWA, 206 [(set G8RC:$rD, (sextload ixaddr:$src, i32))]>, isPPC64, 207 PPC970_DGroup_Cracked; 208def LD : DSForm_2<58, 0, (ops G8RC:$rD, memrix:$src), 209 "ld $rD, $src", LdStLD, 210 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 211 212def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src), 213 "lwax $rD, $src", LdStLHA, 214 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64, 215 PPC970_DGroup_Cracked; 216def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src), 217 "ldx $rD, $src", LdStLD, 218 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 219} 220let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 221def STD : DSForm_2<62, 0, (ops G8RC:$rS, memrix:$dst), 222 "std $rS, $dst", LdStSTD, 223 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 224def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst), 225 "stdx $rS, $dst", LdStSTD, 226 [(store G8RC:$rS, iaddr:$dst)]>, isPPC64, 227 PPC970_DGroup_Cracked; 228def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst), 229 "stdux $rS, $dst", LdStSTD, 230 []>, isPPC64; 231 232// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 233def STD_32 : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst), 234 "std $rT, $dst", LdStSTD, 235 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 236def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst), 237 "stdx $rT, $dst", LdStSTD, 238 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 239 PPC970_DGroup_Cracked; 240} 241 242 243 244//===----------------------------------------------------------------------===// 245// Floating point instructions. 246// 247 248 249let PPC970_Unit = 3 in { // FPU Operations. 250def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB), 251 "fcfid $frD, $frB", FPGeneral, 252 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 253def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB), 254 "fctidz $frD, $frB", FPGeneral, 255 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 256} 257 258 259//===----------------------------------------------------------------------===// 260// Instruction Patterns 261// 262 263// Immediate support. 264// Handled above: 265// sext(0x0000_0000_0000_FFFF, i8) -> li imm 266// sext(0x0000_0000_FFFF_0000, i16) -> lis imm>>16 267 268// sext(0x0000_0000_FFFF_FFFF, i16) -> lis + ori 269def sext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{ 270 return N->getValue() == (uint64_t)(int32_t)N->getValue(); 271}]>; 272def : Pat<(i64 sext_0x0000_0000_FFFF_FFFF_i16:$imm), 273 (ORI8 (LIS8 (HI16 imm:$imm)), (LO16 imm:$imm))>; 274 275// zext(0x0000_0000_FFFF_7FFF, i16) -> oris (li lo16(imm)), imm>>16 276def zext_0x0000_0000_FFFF_7FFF_i16 : PatLeaf<(imm), [{ 277 return (N->getValue() & 0xFFFFFFFF00008000ULL) == 0; 278}]>; 279def : Pat<(i64 zext_0x0000_0000_FFFF_7FFF_i16:$imm), 280 (ORIS8 (LI8 (LO16 imm:$imm)), (HI16 imm:$imm))>; 281 282// zext(0x0000_0000_FFFF_FFFF, i16) -> oris (ori (li 0), lo16(imm)), imm>>16 283def zext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{ 284 return (N->getValue() & 0xFFFFFFFF00000000ULL) == 0; 285}]>; 286def : Pat<(i64 zext_0x0000_0000_FFFF_FFFF_i16:$imm), 287 (ORIS8 (ORI8 (LI8 0), (LO16 imm:$imm)), (HI16 imm:$imm))>; 288 289// FIXME: Handle smart forms where the top 32-bits are set. Right now, stuff 290// like 0xABCD0123BCDE0000 hits the case below, which produces ORI R, R, 0's! 291 292// Fully general (and most expensive: 6 instructions!) immediate pattern. 293def : Pat<(i64 imm:$imm), 294 (ORI8 295 (ORIS8 296 (RLDICR 297 (ORI8 298 (LIS8 (HI48_64 imm:$imm)), 299 (HI32_48 imm:$imm)), 300 32, 31), 301 (HI16 imm:$imm)), 302 (LO16 imm:$imm))>; 303 304 305// Extensions and truncates to/from 32-bit regs. 306def : Pat<(i64 (zext GPRC:$in)), 307 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 308def : Pat<(i64 (anyext GPRC:$in)), 309 (OR4To8 GPRC:$in, GPRC:$in)>; 310def : Pat<(i32 (trunc G8RC:$in)), 311 (OR8To4 G8RC:$in, G8RC:$in)>; 312 313// SHL/SRL 314def : Pat<(shl G8RC:$in, (i64 imm:$imm)), 315 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 316def : Pat<(srl G8RC:$in, (i64 imm:$imm)), 317 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 318 319// Hi and Lo for Darwin Global Addresses. 320def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 321def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 322def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 323def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 324def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 325def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 326def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 327 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 328def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 329 (ADDIS8 G8RC:$in, tconstpool:$g)>; 330def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 331 (ADDIS8 G8RC:$in, tjumptable:$g)>; 332