PPCInstr64Bit.td revision f2c5bca165fa654ad46f2b232773b2116b734b63 
1//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===//
2// 
3//                     The LLVM Compiler Infrastructure
4//
5// This file was developed by Chris Lattner and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7// 
8//===----------------------------------------------------------------------===//
9//
10// This file describes the PowerPC 64-bit instructions.  These patterns are used
11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode.
12//
13//===----------------------------------------------------------------------===//
14
15//===----------------------------------------------------------------------===//
16// 64-bit operands.
17//
18def symbolHi64 : Operand<i64> {
19  let PrintMethod = "printSymbolHi";
20}
21def symbolLo64 : Operand<i64> {
22  let PrintMethod = "printSymbolLo";
23}
24
25
26
27
28//===----------------------------------------------------------------------===//
29// Fixed point instructions.
30//
31
32let PPC970_Unit = 1 in {  // FXU Operations.
33
34// Copies, extends, truncates.
35def OR4To8  : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB),
36                   "or $rA, $rS, $rB", IntGeneral,
37                   []>;
38def OR8To4  : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB),
39                   "or $rA, $rS, $rB", IntGeneral,
40                   []>;
41
42def LI8  : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm),
43                      "li $rD, $imm", IntGeneral,
44                      [(set G8RC:$rD, immSExt16:$imm)]>;
45def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm),
46                      "lis $rD, $imm", IntGeneral,
47                      [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>;
48
49// Logical ops.
50def NAND8: XForm_6<31, 476, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
51                   "nand $rA, $rS, $rB", IntGeneral,
52                   [(set G8RC:$rA, (not (and G8RC:$rS, G8RC:$rB)))]>;
53def AND8 : XForm_6<31,  28, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
54                   "and $rA, $rS, $rB", IntGeneral,
55                   [(set G8RC:$rA, (and G8RC:$rS, G8RC:$rB))]>;
56def ANDC8: XForm_6<31,  60, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
57                   "andc $rA, $rS, $rB", IntGeneral,
58                   [(set G8RC:$rA, (and G8RC:$rS, (not G8RC:$rB)))]>;
59def OR8  : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
60                   "or $rA, $rS, $rB", IntGeneral,
61                   [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>;
62def NOR8 : XForm_6<31, 124, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
63                   "nor $rA, $rS, $rB", IntGeneral,
64                   [(set G8RC:$rA, (not (or G8RC:$rS, G8RC:$rB)))]>;
65def ORC8 : XForm_6<31, 412, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
66                   "orc $rA, $rS, $rB", IntGeneral,
67                   [(set G8RC:$rA, (or G8RC:$rS, (not G8RC:$rB)))]>;
68def EQV8 : XForm_6<31, 284, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
69                   "eqv $rA, $rS, $rB", IntGeneral,
70                   [(set G8RC:$rA, (not (xor G8RC:$rS, G8RC:$rB)))]>;
71def XOR8 : XForm_6<31, 316, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
72                   "xor $rA, $rS, $rB", IntGeneral,
73                   [(set G8RC:$rA, (xor G8RC:$rS, G8RC:$rB))]>;
74
75// Logical ops with immediate.
76def ANDIo8  : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
77                      "andi. $dst, $src1, $src2", IntGeneral,
78                      [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>,
79                      isDOT;
80def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
81                     "andis. $dst, $src1, $src2", IntGeneral,
82                    [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>,
83                     isDOT;
84def ORI8    : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
85                      "ori $dst, $src1, $src2", IntGeneral,
86                      [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>;
87def ORIS8   : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
88                      "oris $dst, $src1, $src2", IntGeneral,
89                    [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>;
90def XORI8   : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
91                      "xori $dst, $src1, $src2", IntGeneral,
92                      [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>;
93def XORIS8  : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2),
94                      "xoris $dst, $src1, $src2", IntGeneral,
95                   [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>;
96
97
98                   
99def ADD8  : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
100                     "add $rT, $rA, $rB", IntGeneral,
101                     [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>;
102def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm),
103                     "addis $rD, $rA, $imm", IntGeneral,
104                     [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>;
105
106
107
108
109def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
110                     "mulhd $rT, $rA, $rB", IntMulHW,
111                     [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>;
112def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
113                     "mulhdu $rT, $rA, $rB", IntMulHWU,
114                     [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>;
115
116def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
117                        "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64;
118
119def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
120                         "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64;
121def CMPD   : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
122                          "cmpd $crD, $rA, $rB", IntCompare>, isPPC64;
123def CMPLD  : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
124                          "cmpld $crD, $rA, $rB", IntCompare>, isPPC64;
125
126def SLD  : XForm_6<31,  27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
127                   "sld $rA, $rS, $rB", IntRotateD,
128                   [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64;
129def SRD  : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
130                   "srd $rA, $rS, $rB", IntRotateD,
131                   [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64;
132def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB),
133                   "srad $rA, $rS, $rB", IntRotateD,
134                   [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64;
135def EXTSW  : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS),
136                      "extsw $rA, $rS", IntGeneral,
137                      [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64;
138/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers.
139def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS),
140                      "extsw $rA, $rS", IntGeneral,
141                      [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64;
142
143def SRADI  : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH),
144                      "sradi $rA, $rS, $SH", IntRotateD>, isPPC64;
145def DIVD  : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
146                     "divd $rT, $rA, $rB", IntDivD,
147                     [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
148                     PPC970_DGroup_First, PPC970_DGroup_Cracked;
149def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
150                     "divdu $rT, $rA, $rB", IntDivD,
151                     [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64,
152                     PPC970_DGroup_First, PPC970_DGroup_Cracked;
153def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB),
154                     "mulld $rT, $rA, $rB", IntMulHD,
155                     [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64;
156
157let isTwoAddress = 1, isCommutable = 1 in {
158def RLDIMI : MDForm_1<30, 3,
159                      (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB),
160                      "rldimi $rA, $rS, $SH, $MB", IntRotateD,
161                      []>, isPPC64;
162}
163
164// Rotate instructions.
165def RLDICL : MDForm_1<30, 0,
166                      (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB),
167                      "rldicl $rA, $rS, $SH, $MB", IntRotateD,
168                      []>, isPPC64;
169def RLDICR : MDForm_1<30, 1,
170                      (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME),
171                      "rldicr $rA, $rS, $SH, $ME", IntRotateD,
172                      []>, isPPC64;
173}
174
175
176//===----------------------------------------------------------------------===//
177// Load/Store instructions.
178//
179
180
181let isLoad = 1, PPC970_Unit = 2 in {
182def LWA  : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src),
183                    "lwa $rD, $src", LdStLWA,
184                    [(set G8RC:$rD, (sextload ixaddr:$src, i32))]>, isPPC64,
185                    PPC970_DGroup_Cracked;
186def LD   : DSForm_2<58, 0, (ops G8RC:$rD, memrix:$src),
187                    "ld $rD, $src", LdStLD,
188                    [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64;
189
190def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src),
191                   "lwax $rD, $src", LdStLHA,
192                   [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64,
193                   PPC970_DGroup_Cracked;
194def LDX  : XForm_1<31,  21, (ops G8RC:$rD, memrr:$src),
195                   "ldx $rD, $src", LdStLD,
196                   [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64;
197}
198let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
199def STD  : DSForm_2<62, 0, (ops G8RC:$rS, memrix:$dst),
200                    "std $rS, $dst", LdStSTD,
201                    [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64;
202def STDX  : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst),
203                   "stdx $rS, $dst", LdStSTD,
204                   [(store G8RC:$rS, iaddr:$dst)]>, isPPC64,
205                   PPC970_DGroup_Cracked;
206def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst),
207                   "stdux $rS, $dst", LdStSTD,
208                   []>, isPPC64;
209                   
210// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register.
211def STD_32  : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst),
212                       "std $rT, $dst", LdStSTD,
213                       [(PPCstd_32  GPRC:$rT, ixaddr:$dst)]>, isPPC64;
214def STDX_32  : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst),
215                       "stdx $rT, $dst", LdStSTD,
216                       [(PPCstd_32  GPRC:$rT, xaddr:$dst)]>, isPPC64,
217                       PPC970_DGroup_Cracked;
218}
219
220
221
222//===----------------------------------------------------------------------===//
223// Floating point instructions.
224//
225
226
227let PPC970_Unit = 3 in {  // FPU Operations.
228def FCFID  : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB),
229                      "fcfid $frD, $frB", FPGeneral,
230                      [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64;
231def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB),
232                      "fctidz $frD, $frB", FPGeneral,
233                      [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64;
234}
235
236
237//===----------------------------------------------------------------------===//
238// Instruction Patterns
239//
240
241def HI32_48 : SDNodeXForm<imm, [{
242  // Transformation function: shift the immediate value down into the low bits.
243  return getI32Imm((unsigned short)(N->getValue() >> 32));
244}]>;
245
246def HI48_64 : SDNodeXForm<imm, [{
247  // Transformation function: shift the immediate value down into the low bits.
248  return getI32Imm((unsigned short)(N->getValue() >> 48));
249}]>;
250
251
252// Immediate support.
253// Handled above:
254//   sext(0x0000_0000_0000_FFFF,  i8) -> li imm
255//   sext(0x0000_0000_FFFF_0000, i16) -> lis imm>>16
256
257// sext(0x0000_0000_FFFF_FFFF,  i16)  -> lis + ori
258def sext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
259  return N->getValue() == (uint64_t)(int32_t)N->getValue();
260}]>;
261def : Pat<(i64 sext_0x0000_0000_FFFF_FFFF_i16:$imm),
262          (ORI8 (LIS8 (HI16 imm:$imm)), (LO16 imm:$imm))>;
263
264// zext(0x0000_0000_FFFF_7FFF, i16) -> oris (li lo16(imm)), imm>>16
265def zext_0x0000_0000_FFFF_7FFF_i16 : PatLeaf<(imm), [{
266  return (N->getValue() & 0xFFFFFFFF00008000ULL) == 0;
267}]>;
268def : Pat<(i64 zext_0x0000_0000_FFFF_7FFF_i16:$imm),
269          (ORIS8 (LI8 (LO16 imm:$imm)), (HI16 imm:$imm))>;
270
271// zext(0x0000_0000_FFFF_FFFF, i16) -> oris (ori (li 0), lo16(imm)), imm>>16
272def zext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{
273  return (N->getValue() & 0xFFFFFFFF00000000ULL) == 0;
274}]>;
275def : Pat<(i64 zext_0x0000_0000_FFFF_FFFF_i16:$imm),
276          (ORIS8 (ORI8 (LI8 0), (LO16 imm:$imm)), (HI16 imm:$imm))>;
277
278// FIXME: Handle smart forms where the top 32-bits are set.  Right now, stuff
279// like 0xABCD0123BCDE0000 hits the case below, which produces ORI R, R, 0's! 
280
281// Fully general (and most expensive: 6 instructions!) immediate pattern.
282def : Pat<(i64 imm:$imm),
283          (ORI8 
284             (ORIS8 
285                (RLDICR
286                   (ORI8
287                      (LIS8 (HI48_64 imm:$imm)),
288                      (HI32_48 imm:$imm)),
289                   32, 31),
290                (HI16 imm:$imm)),
291             (LO16 imm:$imm))>;
292
293
294// Extensions and truncates to/from 32-bit regs.
295def : Pat<(i64 (zext GPRC:$in)),
296          (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>;
297def : Pat<(i64 (anyext GPRC:$in)),
298          (OR4To8 GPRC:$in, GPRC:$in)>;
299def : Pat<(i32 (trunc G8RC:$in)),
300          (OR8To4 G8RC:$in, G8RC:$in)>;
301
302// SHL/SRL
303def : Pat<(shl G8RC:$in, (i64 imm:$imm)),
304          (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>;
305def : Pat<(srl G8RC:$in, (i64 imm:$imm)),
306          (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>;
307
308// Hi and Lo for Darwin Global Addresses.
309def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>;
310def : Pat<(PPClo tglobaladdr:$in, 0), (LI8  tglobaladdr:$in)>;
311def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>;
312def : Pat<(PPClo tconstpool:$in , 0), (LI8  tconstpool:$in)>;
313def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>;
314def : Pat<(PPClo tjumptable:$in , 0), (LI8  tjumptable:$in)>;
315def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)),
316          (ADDIS8 G8RC:$in, tglobaladdr:$g)>;
317def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)),
318          (ADDIS8 G8RC:$in, tconstpool:$g)>;
319def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)),
320          (ADDIS8 G8RC:$in, tjumptable:$g)>;
321