PPCInstr64Bit.td revision 3ae5eef0278db0cff59f714ab4b2124ec31b942e
1//===- PPCInstr64Bit.td - The PowerPC 64-bit Support -------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file was developed by Chris Lattner and is distributed under 6// the University of Illinois Open Source License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def symbolHi64 : Operand<i64> { 19 let PrintMethod = "printSymbolHi"; 20} 21def symbolLo64 : Operand<i64> { 22 let PrintMethod = "printSymbolLo"; 23} 24 25 26 27 28//===----------------------------------------------------------------------===// 29// Fixed point instructions. 30// 31 32let PPC970_Unit = 1 in { // FXU Operations. 33 34// Copies, extends, truncates. 35def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 36 "or $rA, $rS, $rB", IntGeneral, 37 [(set G8RC:$rA, (or G8RC:$rS, G8RC:$rB))]>; 38def OR4To8 : XForm_6<31, 444, (ops G8RC:$rA, GPRC:$rS, GPRC:$rB), 39 "or $rA, $rS, $rB", IntGeneral, 40 []>; 41def OR8To4 : XForm_6<31, 444, (ops GPRC:$rA, G8RC:$rS, G8RC:$rB), 42 "or $rA, $rS, $rB", IntGeneral, 43 []>; 44 45def LI8 : DForm_2_r0<14, (ops G8RC:$rD, symbolLo64:$imm), 46 "li $rD, $imm", IntGeneral, 47 [(set G8RC:$rD, immSExt16:$imm)]>; 48def LIS8 : DForm_2_r0<15, (ops G8RC:$rD, symbolHi64:$imm), 49 "lis $rD, $imm", IntGeneral, 50 [(set G8RC:$rD, imm16ShiftedSExt:$imm)]>; 51 52// Logical ops. 53def ANDIo8 : DForm_4<28, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 54 "andi. $dst, $src1, $src2", IntGeneral, 55 [(set G8RC:$dst, (and G8RC:$src1, immZExt16:$src2))]>, 56 isDOT; 57def ANDISo8 : DForm_4<29, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 58 "andis. $dst, $src1, $src2", IntGeneral, 59 [(set G8RC:$dst, (and G8RC:$src1,imm16ShiftedZExt:$src2))]>, 60 isDOT; 61def ORI8 : DForm_4<24, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 62 "ori $dst, $src1, $src2", IntGeneral, 63 [(set G8RC:$dst, (or G8RC:$src1, immZExt16:$src2))]>; 64def ORIS8 : DForm_4<25, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 65 "oris $dst, $src1, $src2", IntGeneral, 66 [(set G8RC:$dst, (or G8RC:$src1, imm16ShiftedZExt:$src2))]>; 67def XORI8 : DForm_4<26, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 68 "xori $dst, $src1, $src2", IntGeneral, 69 [(set G8RC:$dst, (xor G8RC:$src1, immZExt16:$src2))]>; 70def XORIS8 : DForm_4<27, (ops G8RC:$dst, G8RC:$src1, u16imm:$src2), 71 "xoris $dst, $src1, $src2", IntGeneral, 72 [(set G8RC:$dst, (xor G8RC:$src1, imm16ShiftedZExt:$src2))]>; 73 74 75 76def ADD8 : XOForm_1<31, 266, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 77 "add $rT, $rA, $rB", IntGeneral, 78 [(set G8RC:$rT, (add G8RC:$rA, G8RC:$rB))]>; 79def ADDIS8 : DForm_2<15, (ops G8RC:$rD, G8RC:$rA, symbolHi64:$imm), 80 "addis $rD, $rA, $imm", IntGeneral, 81 [(set G8RC:$rD, (add G8RC:$rA, imm16ShiftedSExt:$imm))]>; 82 83 84 85 86def MULHD : XOForm_1<31, 73, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 87 "mulhd $rT, $rA, $rB", IntMulHW, 88 [(set G8RC:$rT, (mulhs G8RC:$rA, G8RC:$rB))]>; 89def MULHDU : XOForm_1<31, 9, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 90 "mulhdu $rT, $rA, $rB", IntMulHWU, 91 [(set G8RC:$rT, (mulhu G8RC:$rA, G8RC:$rB))]>; 92 93def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), 94 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 95 96def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), 97 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 98def CMPD : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 99 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 100def CMPLD : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB), 101 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 102 103def SLD : XForm_6<31, 27, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 104 "sld $rA, $rS, $rB", IntRotateD, 105 [(set G8RC:$rA, (shl G8RC:$rS, G8RC:$rB))]>, isPPC64; 106def SRD : XForm_6<31, 539, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 107 "srd $rA, $rS, $rB", IntRotateD, 108 [(set G8RC:$rA, (srl G8RC:$rS, G8RC:$rB))]>, isPPC64; 109def SRAD : XForm_6<31, 794, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), 110 "srad $rA, $rS, $rB", IntRotateD, 111 [(set G8RC:$rA, (sra G8RC:$rS, G8RC:$rB))]>, isPPC64; 112def EXTSW : XForm_11<31, 986, (ops G8RC:$rA, G8RC:$rS), 113 "extsw $rA, $rS", IntGeneral, 114 [(set G8RC:$rA, (sext_inreg G8RC:$rS, i32))]>, isPPC64; 115/// EXTSW_32 - Just like EXTSW, but works on '32-bit' registers. 116def EXTSW_32 : XForm_11<31, 986, (ops GPRC:$rA, GPRC:$rS), 117 "extsw $rA, $rS", IntGeneral, 118 [(set GPRC:$rA, (PPCextsw_32 GPRC:$rS))]>, isPPC64; 119 120def SRADI : XSForm_1<31, 413, (ops GPRC:$rA, GPRC:$rS, u6imm:$SH), 121 "sradi $rA, $rS, $SH", IntRotateD>, isPPC64; 122def DIVD : XOForm_1<31, 489, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 123 "divd $rT, $rA, $rB", IntDivD, 124 [(set G8RC:$rT, (sdiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 125 PPC970_DGroup_First, PPC970_DGroup_Cracked; 126def DIVDU : XOForm_1<31, 457, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 127 "divdu $rT, $rA, $rB", IntDivD, 128 [(set G8RC:$rT, (udiv G8RC:$rA, G8RC:$rB))]>, isPPC64, 129 PPC970_DGroup_First, PPC970_DGroup_Cracked; 130def MULLD : XOForm_1<31, 233, 0, (ops G8RC:$rT, G8RC:$rA, G8RC:$rB), 131 "mulld $rT, $rA, $rB", IntMulHD, 132 [(set G8RC:$rT, (mul G8RC:$rA, G8RC:$rB))]>, isPPC64; 133 134let isTwoAddress = 1, isCommutable = 1 in { 135def RLDIMI : MDForm_1<30, 3, 136 (ops G8RC:$rA, G8RC:$rSi, G8RC:$rS, u6imm:$SH, u6imm:$MB), 137 "rldimi $rA, $rS, $SH, $MB", IntRotateD, 138 []>, isPPC64; 139} 140 141// Rotate instructions. 142def RLDICL : MDForm_1<30, 0, 143 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$MB), 144 "rldicl $rA, $rS, $SH, $MB", IntRotateD, 145 []>, isPPC64; 146def RLDICR : MDForm_1<30, 1, 147 (ops G8RC:$rA, G8RC:$rS, u6imm:$SH, u6imm:$ME), 148 "rldicr $rA, $rS, $SH, $ME", IntRotateD, 149 []>, isPPC64; 150} 151 152 153//===----------------------------------------------------------------------===// 154// Load/Store instructions. 155// 156 157 158let isLoad = 1, PPC970_Unit = 2 in { 159def LWA : DSForm_1<58, 2, (ops G8RC:$rD, memrix:$src), 160 "lwa $rD, $src", LdStLWA, 161 [(set G8RC:$rD, (sextload ixaddr:$src, i32))]>, isPPC64, 162 PPC970_DGroup_Cracked; 163def LD : DSForm_2<58, 0, (ops G8RC:$rD, memrix:$src), 164 "ld $rD, $src", LdStLD, 165 [(set G8RC:$rD, (load ixaddr:$src))]>, isPPC64; 166 167def LWAX : XForm_1<31, 341, (ops G8RC:$rD, memrr:$src), 168 "lwax $rD, $src", LdStLHA, 169 [(set G8RC:$rD, (sextload xaddr:$src, i32))]>, isPPC64, 170 PPC970_DGroup_Cracked; 171def LDX : XForm_1<31, 21, (ops G8RC:$rD, memrr:$src), 172 "ldx $rD, $src", LdStLD, 173 [(set G8RC:$rD, (load xaddr:$src))]>, isPPC64; 174} 175let isStore = 1, noResults = 1, PPC970_Unit = 2 in { 176def STD : DSForm_2<62, 0, (ops G8RC:$rS, memrix:$dst), 177 "std $rS, $dst", LdStSTD, 178 [(store G8RC:$rS, ixaddr:$dst)]>, isPPC64; 179def STDX : XForm_8<31, 149, (ops G8RC:$rS, memrr:$dst), 180 "stdx $rS, $dst", LdStSTD, 181 [(store G8RC:$rS, iaddr:$dst)]>, isPPC64, 182 PPC970_DGroup_Cracked; 183def STDUX : XForm_8<31, 181, (ops G8RC:$rS, memrr:$dst), 184 "stdux $rS, $dst", LdStSTD, 185 []>, isPPC64; 186 187// STD_32/STDX_32 - Just like STD/STDX, but uses a '32-bit' input register. 188def STD_32 : DSForm_2<62, 0, (ops GPRC:$rT, memrix:$dst), 189 "std $rT, $dst", LdStSTD, 190 [(PPCstd_32 GPRC:$rT, ixaddr:$dst)]>, isPPC64; 191def STDX_32 : XForm_8<31, 149, (ops GPRC:$rT, memrr:$dst), 192 "stdx $rT, $dst", LdStSTD, 193 [(PPCstd_32 GPRC:$rT, xaddr:$dst)]>, isPPC64, 194 PPC970_DGroup_Cracked; 195} 196 197 198 199//===----------------------------------------------------------------------===// 200// Floating point instructions. 201// 202 203 204let PPC970_Unit = 3 in { // FPU Operations. 205def FCFID : XForm_26<63, 846, (ops F8RC:$frD, F8RC:$frB), 206 "fcfid $frD, $frB", FPGeneral, 207 [(set F8RC:$frD, (PPCfcfid F8RC:$frB))]>, isPPC64; 208def FCTIDZ : XForm_26<63, 815, (ops F8RC:$frD, F8RC:$frB), 209 "fctidz $frD, $frB", FPGeneral, 210 [(set F8RC:$frD, (PPCfctidz F8RC:$frB))]>, isPPC64; 211} 212 213 214//===----------------------------------------------------------------------===// 215// Instruction Patterns 216// 217 218def HI32_48 : SDNodeXForm<imm, [{ 219 // Transformation function: shift the immediate value down into the low bits. 220 return getI32Imm((unsigned short)(N->getValue() >> 32)); 221}]>; 222 223def HI48_64 : SDNodeXForm<imm, [{ 224 // Transformation function: shift the immediate value down into the low bits. 225 return getI32Imm((unsigned short)(N->getValue() >> 48)); 226}]>; 227 228 229// Immediate support. 230// Handled above: 231// sext(0x0000_0000_0000_FFFF, i8) -> li imm 232// sext(0x0000_0000_FFFF_0000, i16) -> lis imm>>16 233 234// sext(0x0000_0000_FFFF_FFFF, i16) -> lis + ori 235def sext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{ 236 return N->getValue() == (uint64_t)(int32_t)N->getValue(); 237}]>; 238def : Pat<(i64 sext_0x0000_0000_FFFF_FFFF_i16:$imm), 239 (ORI8 (LIS8 (HI16 imm:$imm)), (LO16 imm:$imm))>; 240 241// zext(0x0000_0000_FFFF_7FFF, i16) -> oris (li lo16(imm)), imm>>16 242def zext_0x0000_0000_FFFF_7FFF_i16 : PatLeaf<(imm), [{ 243 return (N->getValue() & 0xFFFFFFFF00008000ULL) == 0; 244}]>; 245def : Pat<(i64 zext_0x0000_0000_FFFF_7FFF_i16:$imm), 246 (ORIS8 (LI8 (LO16 imm:$imm)), (HI16 imm:$imm))>; 247 248// zext(0x0000_0000_FFFF_FFFF, i16) -> oris (ori (li 0), lo16(imm)), imm>>16 249def zext_0x0000_0000_FFFF_FFFF_i16 : PatLeaf<(imm), [{ 250 return (N->getValue() & 0xFFFFFFFF00000000ULL) == 0; 251}]>; 252def : Pat<(i64 zext_0x0000_0000_FFFF_FFFF_i16:$imm), 253 (ORIS8 (ORI8 (LI8 0), (LO16 imm:$imm)), (HI16 imm:$imm))>; 254 255 256// Fully general (and most expensive: 6 instructions!) immediate pattern. 257def : Pat<(i64 imm:$imm), 258 (ORI8 259 (ORIS8 260 (RLDICR 261 (ORI8 262 (LIS8 (HI48_64 imm:$imm)), 263 (HI32_48 imm:$imm)), 264 32, 31), 265 (HI16 imm:$imm)), 266 (LO16 imm:$imm))>; 267 268 269// Extensions and truncates to/from 32-bit regs. 270def : Pat<(i64 (zext GPRC:$in)), 271 (RLDICL (OR4To8 GPRC:$in, GPRC:$in), 0, 32)>; 272def : Pat<(i64 (anyext GPRC:$in)), 273 (OR4To8 GPRC:$in, GPRC:$in)>; 274def : Pat<(i32 (trunc G8RC:$in)), 275 (OR8To4 G8RC:$in, G8RC:$in)>; 276 277// SHL/SRL 278def : Pat<(shl G8RC:$in, (i64 imm:$imm)), 279 (RLDICR G8RC:$in, imm:$imm, (SHL64 imm:$imm))>; 280def : Pat<(srl G8RC:$in, (i64 imm:$imm)), 281 (RLDICL G8RC:$in, (SRL64 imm:$imm), imm:$imm)>; 282 283// Hi and Lo for Darwin Global Addresses. 284def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 285def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 286def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 287def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 288def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 289def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 290def : Pat<(add G8RC:$in, (PPChi tglobaladdr:$g, 0)), 291 (ADDIS8 G8RC:$in, tglobaladdr:$g)>; 292def : Pat<(add G8RC:$in, (PPChi tconstpool:$g, 0)), 293 (ADDIS8 G8RC:$in, tconstpool:$g)>; 294def : Pat<(add G8RC:$in, (PPChi tjumptable:$g, 0)), 295 (ADDIS8 G8RC:$in, tjumptable:$g)>; 296