PPCInstr64Bit.td revision 586f6d009a37d4d38be0badaaa60d7cdb647b442
1//===-- PPCInstr64Bit.td - The PowerPC 64-bit Support ------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// This file is distributed under the University of Illinois Open Source 6// License. See LICENSE.TXT for details. 7// 8//===----------------------------------------------------------------------===// 9// 10// This file describes the PowerPC 64-bit instructions. These patterns are used 11// both when in ppc64 mode and when in "use 64-bit extensions in 32-bit" mode. 12// 13//===----------------------------------------------------------------------===// 14 15//===----------------------------------------------------------------------===// 16// 64-bit operands. 17// 18def s16imm64 : Operand<i64> { 19 let PrintMethod = "printS16ImmOperand"; 20 let EncoderMethod = "getS16ImmEncoding"; 21 let ParserMatchClass = PPCS16ImmAsmOperand; 22} 23def u16imm64 : Operand<i64> { 24 let PrintMethod = "printU16ImmOperand"; 25 let ParserMatchClass = PPCU16ImmAsmOperand; 26} 27def tocentry : Operand<iPTR> { 28 let MIOperandInfo = (ops i64imm:$imm); 29} 30def tlsreg : Operand<i64> { 31 let EncoderMethod = "getTLSRegEncoding"; 32} 33def tlsgd : Operand<i64> {} 34 35//===----------------------------------------------------------------------===// 36// 64-bit transformation functions. 37// 38 39def SHL64 : SDNodeXForm<imm, [{ 40 // Transformation function: 63 - imm 41 return getI32Imm(63 - N->getZExtValue()); 42}]>; 43 44def SRL64 : SDNodeXForm<imm, [{ 45 // Transformation function: 64 - imm 46 return N->getZExtValue() ? getI32Imm(64 - N->getZExtValue()) : getI32Imm(0); 47}]>; 48 49def HI32_48 : SDNodeXForm<imm, [{ 50 // Transformation function: shift the immediate value down into the low bits. 51 return getI32Imm((unsigned short)(N->getZExtValue() >> 32)); 52}]>; 53 54def HI48_64 : SDNodeXForm<imm, [{ 55 // Transformation function: shift the immediate value down into the low bits. 56 return getI32Imm((unsigned short)(N->getZExtValue() >> 48)); 57}]>; 58 59 60//===----------------------------------------------------------------------===// 61// Calls. 62// 63 64let Interpretation64Bit = 1 in { 65let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in { 66 let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { 67 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 68 Requires<[In64BitMode]>; 69 70 let isCodeGenOnly = 1 in 71 def BCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond), 72 "b${cond:cc}ctr ${cond:reg}", BrB, []>, 73 Requires<[In64BitMode]>; 74 } 75} 76 77let Defs = [LR8] in 78 def MovePCtoLR8 : Pseudo<(outs), (ins), "#MovePCtoLR8", []>, 79 PPC970_Unit_BRU; 80 81let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in { 82 let Defs = [CTR8], Uses = [CTR8] in { 83 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst), 84 "bdz $dst">; 85 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst), 86 "bdnz $dst">; 87 } 88 89 let isReturn = 1, Defs = [CTR8], Uses = [CTR8, LR8, RM] in { 90 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins), 91 "bdzlr", BrB, []>; 92 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins), 93 "bdnzlr", BrB, []>; 94 } 95} 96 97 98 99let isCall = 1, PPC970_Unit = 7, Defs = [LR8] in { 100 // Convenient aliases for call instructions 101 let Uses = [RM] in { 102 def BL8 : IForm<18, 0, 1, (outs), (ins calltarget:$func), 103 "bl $func", BrB, []>; // See Pat patterns below. 104 105 def BLA8 : IForm<18, 1, 1, (outs), (ins aaddr:$func), 106 "bla $func", BrB, [(PPCcall (i64 imm:$func))]>; 107 } 108 let Uses = [RM], isCodeGenOnly = 1 in { 109 def BL8_NOP : IForm_and_DForm_4_zero<18, 0, 1, 24, 110 (outs), (ins calltarget:$func), 111 "bl $func\n\tnop", BrB, []>; 112 113 def BL8_NOP_TLSGD : IForm_and_DForm_4_zero<18, 0, 1, 24, 114 (outs), (ins calltarget:$func, tlsgd:$sym), 115 "bl $func($sym)\n\tnop", BrB, []>; 116 117 def BL8_NOP_TLSLD : IForm_and_DForm_4_zero<18, 0, 1, 24, 118 (outs), (ins calltarget:$func, tlsgd:$sym), 119 "bl $func($sym)\n\tnop", BrB, []>; 120 121 def BLA8_NOP : IForm_and_DForm_4_zero<18, 1, 1, 24, 122 (outs), (ins aaddr:$func), 123 "bla $func\n\tnop", BrB, 124 [(PPCcall_nop (i64 imm:$func))]>; 125 } 126 let Uses = [CTR8, RM] in { 127 def BCTRL8 : XLForm_2_ext<19, 528, 20, 0, 1, (outs), (ins), 128 "bctrl", BrB, [(PPCbctrl)]>, 129 Requires<[In64BitMode]>; 130 131 let isCodeGenOnly = 1 in 132 def BCCTRL8 : XLForm_2_br<19, 528, 1, (outs), (ins pred:$cond), 133 "b${cond:cc}ctrl ${cond:reg}", BrB, []>, 134 Requires<[In64BitMode]>; 135 } 136} 137} // Interpretation64Bit 138 139// Calls 140def : Pat<(PPCcall (i64 tglobaladdr:$dst)), 141 (BL8 tglobaladdr:$dst)>; 142def : Pat<(PPCcall_nop (i64 tglobaladdr:$dst)), 143 (BL8_NOP tglobaladdr:$dst)>; 144 145def : Pat<(PPCcall (i64 texternalsym:$dst)), 146 (BL8 texternalsym:$dst)>; 147def : Pat<(PPCcall_nop (i64 texternalsym:$dst)), 148 (BL8_NOP texternalsym:$dst)>; 149 150// Atomic operations 151let usesCustomInserter = 1 in { 152 let Defs = [CR0] in { 153 def ATOMIC_LOAD_ADD_I64 : Pseudo< 154 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_ADD_I64", 155 [(set i64:$dst, (atomic_load_add_64 xoaddr:$ptr, i64:$incr))]>; 156 def ATOMIC_LOAD_SUB_I64 : Pseudo< 157 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_SUB_I64", 158 [(set i64:$dst, (atomic_load_sub_64 xoaddr:$ptr, i64:$incr))]>; 159 def ATOMIC_LOAD_OR_I64 : Pseudo< 160 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_OR_I64", 161 [(set i64:$dst, (atomic_load_or_64 xoaddr:$ptr, i64:$incr))]>; 162 def ATOMIC_LOAD_XOR_I64 : Pseudo< 163 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_XOR_I64", 164 [(set i64:$dst, (atomic_load_xor_64 xoaddr:$ptr, i64:$incr))]>; 165 def ATOMIC_LOAD_AND_I64 : Pseudo< 166 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_AND_i64", 167 [(set i64:$dst, (atomic_load_and_64 xoaddr:$ptr, i64:$incr))]>; 168 def ATOMIC_LOAD_NAND_I64 : Pseudo< 169 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$incr), "#ATOMIC_LOAD_NAND_I64", 170 [(set i64:$dst, (atomic_load_nand_64 xoaddr:$ptr, i64:$incr))]>; 171 172 def ATOMIC_CMP_SWAP_I64 : Pseudo< 173 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$old, g8rc:$new), "#ATOMIC_CMP_SWAP_I64", 174 [(set i64:$dst, (atomic_cmp_swap_64 xoaddr:$ptr, i64:$old, i64:$new))]>; 175 176 def ATOMIC_SWAP_I64 : Pseudo< 177 (outs g8rc:$dst), (ins memrr:$ptr, g8rc:$new), "#ATOMIC_SWAP_I64", 178 [(set i64:$dst, (atomic_swap_64 xoaddr:$ptr, i64:$new))]>; 179 } 180} 181 182// Instructions to support atomic operations 183def LDARX : XForm_1<31, 84, (outs g8rc:$rD), (ins memrr:$ptr), 184 "ldarx $rD, $ptr", LdStLDARX, 185 [(set i64:$rD, (PPClarx xoaddr:$ptr))]>; 186 187let Defs = [CR0] in 188def STDCX : XForm_1<31, 214, (outs), (ins g8rc:$rS, memrr:$dst), 189 "stdcx. $rS, $dst", LdStSTDCX, 190 [(PPCstcx i64:$rS, xoaddr:$dst)]>, 191 isDOT; 192 193let Interpretation64Bit = 1 in { 194let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 195def TCRETURNdi8 :Pseudo< (outs), 196 (ins calltarget:$dst, i32imm:$offset), 197 "#TC_RETURNd8 $dst $offset", 198 []>; 199 200let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 201def TCRETURNai8 :Pseudo<(outs), (ins aaddr:$func, i32imm:$offset), 202 "#TC_RETURNa8 $func $offset", 203 [(PPCtc_return (i64 imm:$func), imm:$offset)]>; 204 205let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [RM] in 206def TCRETURNri8 : Pseudo<(outs), (ins CTRRC8:$dst, i32imm:$offset), 207 "#TC_RETURNr8 $dst $offset", 208 []>; 209 210let isCodeGenOnly = 1 in { 211 212let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, isBranch = 1, 213 isIndirectBranch = 1, isCall = 1, isReturn = 1, Uses = [CTR8, RM] in 214def TAILBCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", BrB, []>, 215 Requires<[In64BitMode]>; 216 217 218let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 219 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 220def TAILB8 : IForm<18, 0, 0, (outs), (ins calltarget:$dst), 221 "b $dst", BrB, 222 []>; 223 224 225let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7, 226 isBarrier = 1, isCall = 1, isReturn = 1, Uses = [RM] in 227def TAILBA8 : IForm<18, 0, 0, (outs), (ins aaddr:$dst), 228 "ba $dst", BrB, 229 []>; 230 231} 232} // Interpretation64Bit 233 234def : Pat<(PPCtc_return (i64 tglobaladdr:$dst), imm:$imm), 235 (TCRETURNdi8 tglobaladdr:$dst, imm:$imm)>; 236 237def : Pat<(PPCtc_return (i64 texternalsym:$dst), imm:$imm), 238 (TCRETURNdi8 texternalsym:$dst, imm:$imm)>; 239 240def : Pat<(PPCtc_return CTRRC8:$dst, imm:$imm), 241 (TCRETURNri8 CTRRC8:$dst, imm:$imm)>; 242 243 244// 64-bit CR instructions 245let Interpretation64Bit = 1 in { 246let neverHasSideEffects = 1 in { 247def MTCRF8 : XFXForm_5<31, 144, (outs crbitm:$FXM), (ins g8rc:$rS), 248 "mtcrf $FXM, $rS", BrMCRX>, 249 PPC970_MicroCode, PPC970_Unit_CRU; 250 251let isCodeGenOnly = 1 in 252def MFCR8pseud: XFXForm_3<31, 19, (outs g8rc:$rT), (ins crbitm:$FXM), 253 "#MFCR8pseud", SprMFCR>, 254 PPC970_MicroCode, PPC970_Unit_CRU; 255} // neverHasSideEffects = 1 256 257let neverHasSideEffects = 1 in 258def MFCR8 : XFXForm_3<31, 19, (outs g8rc:$rT), (ins), 259 "mfcr $rT", SprMFCR>, 260 PPC970_MicroCode, PPC970_Unit_CRU; 261 262let hasSideEffects = 1, isBarrier = 1, usesCustomInserter = 1 in { 263 def EH_SjLj_SetJmp64 : Pseudo<(outs gprc:$dst), (ins memr:$buf), 264 "#EH_SJLJ_SETJMP64", 265 [(set i32:$dst, (PPCeh_sjlj_setjmp addr:$buf))]>, 266 Requires<[In64BitMode]>; 267 let isTerminator = 1 in 268 def EH_SjLj_LongJmp64 : Pseudo<(outs), (ins memr:$buf), 269 "#EH_SJLJ_LONGJMP64", 270 [(PPCeh_sjlj_longjmp addr:$buf)]>, 271 Requires<[In64BitMode]>; 272} 273 274//===----------------------------------------------------------------------===// 275// 64-bit SPR manipulation instrs. 276 277let Uses = [CTR8] in { 278def MFCTR8 : XFXForm_1_ext<31, 339, 9, (outs g8rc:$rT), (ins), 279 "mfctr $rT", SprMFSPR>, 280 PPC970_DGroup_First, PPC970_Unit_FXU; 281} 282let Pattern = [(PPCmtctr i64:$rS)], Defs = [CTR8] in { 283def MTCTR8 : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 284 "mtctr $rS", SprMTSPR>, 285 PPC970_DGroup_First, PPC970_Unit_FXU; 286} 287let hasSideEffects = 1, isCodeGenOnly = 1, Defs = [CTR8] in { 288let Pattern = [(int_ppc_mtctr i64:$rS)] in 289def MTCTR8loop : XFXForm_7_ext<31, 467, 9, (outs), (ins g8rc:$rS), 290 "mtctr $rS", SprMTSPR>, 291 PPC970_DGroup_First, PPC970_Unit_FXU; 292} 293 294let Pattern = [(set i64:$rT, readcyclecounter)] in 295def MFTB8 : XFXForm_1_ext<31, 339, 268, (outs g8rc:$rT), (ins), 296 "mfspr $rT, 268", SprMFTB>, 297 PPC970_DGroup_First, PPC970_Unit_FXU; 298// Note that encoding mftb using mfspr is now the preferred form, 299// and has been since at least ISA v2.03. The mftb instruction has 300// now been phased out. Using mfspr, however, is known not to work on 301// the POWER3. 302 303let Defs = [X1], Uses = [X1] in 304def DYNALLOC8 : Pseudo<(outs g8rc:$result), (ins g8rc:$negsize, memri:$fpsi),"#DYNALLOC8", 305 [(set i64:$result, 306 (PPCdynalloc i64:$negsize, iaddr:$fpsi))]>; 307 308let Defs = [LR8] in { 309def MTLR8 : XFXForm_7_ext<31, 467, 8, (outs), (ins g8rc:$rS), 310 "mtlr $rS", SprMTSPR>, 311 PPC970_DGroup_First, PPC970_Unit_FXU; 312} 313let Uses = [LR8] in { 314def MFLR8 : XFXForm_1_ext<31, 339, 8, (outs g8rc:$rT), (ins), 315 "mflr $rT", SprMFSPR>, 316 PPC970_DGroup_First, PPC970_Unit_FXU; 317} 318} // Interpretation64Bit 319 320//===----------------------------------------------------------------------===// 321// Fixed point instructions. 322// 323 324let PPC970_Unit = 1 in { // FXU Operations. 325let Interpretation64Bit = 1 in { 326let neverHasSideEffects = 1 in { 327 328let isReMaterializable = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in { 329def LI8 : DForm_2_r0<14, (outs g8rc:$rD), (ins s16imm64:$imm), 330 "li $rD, $imm", IntSimple, 331 [(set i64:$rD, imm64SExt16:$imm)]>; 332def LIS8 : DForm_2_r0<15, (outs g8rc:$rD), (ins s16imm64:$imm), 333 "lis $rD, $imm", IntSimple, 334 [(set i64:$rD, imm16ShiftedSExt:$imm)]>; 335} 336 337// Logical ops. 338defm NAND8: XForm_6r<31, 476, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 339 "nand", "$rA, $rS, $rB", IntSimple, 340 [(set i64:$rA, (not (and i64:$rS, i64:$rB)))]>; 341defm AND8 : XForm_6r<31, 28, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 342 "and", "$rA, $rS, $rB", IntSimple, 343 [(set i64:$rA, (and i64:$rS, i64:$rB))]>; 344defm ANDC8: XForm_6r<31, 60, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 345 "andc", "$rA, $rS, $rB", IntSimple, 346 [(set i64:$rA, (and i64:$rS, (not i64:$rB)))]>; 347defm OR8 : XForm_6r<31, 444, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 348 "or", "$rA, $rS, $rB", IntSimple, 349 [(set i64:$rA, (or i64:$rS, i64:$rB))]>; 350defm NOR8 : XForm_6r<31, 124, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 351 "nor", "$rA, $rS, $rB", IntSimple, 352 [(set i64:$rA, (not (or i64:$rS, i64:$rB)))]>; 353defm ORC8 : XForm_6r<31, 412, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 354 "orc", "$rA, $rS, $rB", IntSimple, 355 [(set i64:$rA, (or i64:$rS, (not i64:$rB)))]>; 356defm EQV8 : XForm_6r<31, 284, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 357 "eqv", "$rA, $rS, $rB", IntSimple, 358 [(set i64:$rA, (not (xor i64:$rS, i64:$rB)))]>; 359defm XOR8 : XForm_6r<31, 316, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB), 360 "xor", "$rA, $rS, $rB", IntSimple, 361 [(set i64:$rA, (xor i64:$rS, i64:$rB))]>; 362 363// Logical ops with immediate. 364let Defs = [CR0] in { 365def ANDIo8 : DForm_4<28, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 366 "andi. $dst, $src1, $src2", IntGeneral, 367 [(set i64:$dst, (and i64:$src1, immZExt16:$src2))]>, 368 isDOT; 369def ANDISo8 : DForm_4<29, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 370 "andis. $dst, $src1, $src2", IntGeneral, 371 [(set i64:$dst, (and i64:$src1, imm16ShiftedZExt:$src2))]>, 372 isDOT; 373} 374def ORI8 : DForm_4<24, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 375 "ori $dst, $src1, $src2", IntSimple, 376 [(set i64:$dst, (or i64:$src1, immZExt16:$src2))]>; 377def ORIS8 : DForm_4<25, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 378 "oris $dst, $src1, $src2", IntSimple, 379 [(set i64:$dst, (or i64:$src1, imm16ShiftedZExt:$src2))]>; 380def XORI8 : DForm_4<26, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 381 "xori $dst, $src1, $src2", IntSimple, 382 [(set i64:$dst, (xor i64:$src1, immZExt16:$src2))]>; 383def XORIS8 : DForm_4<27, (outs g8rc:$dst), (ins g8rc:$src1, u16imm:$src2), 384 "xoris $dst, $src1, $src2", IntSimple, 385 [(set i64:$dst, (xor i64:$src1, imm16ShiftedZExt:$src2))]>; 386 387defm ADD8 : XOForm_1r<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 388 "add", "$rT, $rA, $rB", IntSimple, 389 [(set i64:$rT, (add i64:$rA, i64:$rB))]>; 390// ADD8 has a special form: reg = ADD8(reg, sym@tls) for use by the 391// initial-exec thread-local storage model. 392let isCodeGenOnly = 1 in 393def ADD8TLS : XOForm_1<31, 266, 0, (outs g8rc:$rT), (ins g8rc:$rA, tlsreg:$rB), 394 "add $rT, $rA, $rB@tls", IntSimple, 395 [(set i64:$rT, (add i64:$rA, tglobaltlsaddr:$rB))]>; 396 397defm ADDC8 : XOForm_1rc<31, 10, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 398 "addc", "$rT, $rA, $rB", IntGeneral, 399 [(set i64:$rT, (addc i64:$rA, i64:$rB))]>, 400 PPC970_DGroup_Cracked; 401let Defs = [CARRY] in 402def ADDIC8 : DForm_2<12, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 403 "addic $rD, $rA, $imm", IntGeneral, 404 [(set i64:$rD, (addc i64:$rA, imm64SExt16:$imm))]>; 405def ADDI8 : DForm_2<14, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 406 "addi $rD, $rA, $imm", IntSimple, 407 [(set i64:$rD, (add i64:$rA, imm64SExt16:$imm))]>; 408def ADDIS8 : DForm_2<15, (outs g8rc:$rD), (ins g8rc_nox0:$rA, s16imm64:$imm), 409 "addis $rD, $rA, $imm", IntSimple, 410 [(set i64:$rD, (add i64:$rA, imm16ShiftedSExt:$imm))]>; 411 412let Defs = [CARRY] in { 413def SUBFIC8: DForm_2< 8, (outs g8rc:$rD), (ins g8rc:$rA, s16imm64:$imm), 414 "subfic $rD, $rA, $imm", IntGeneral, 415 [(set i64:$rD, (subc imm64SExt16:$imm, i64:$rA))]>; 416defm SUBFC8 : XOForm_1r<31, 8, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 417 "subfc", "$rT, $rA, $rB", IntGeneral, 418 [(set i64:$rT, (subc i64:$rB, i64:$rA))]>, 419 PPC970_DGroup_Cracked; 420} 421defm SUBF8 : XOForm_1r<31, 40, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 422 "subf", "$rT, $rA, $rB", IntGeneral, 423 [(set i64:$rT, (sub i64:$rB, i64:$rA))]>; 424defm NEG8 : XOForm_3r<31, 104, 0, (outs g8rc:$rT), (ins g8rc:$rA), 425 "neg", "$rT, $rA", IntSimple, 426 [(set i64:$rT, (ineg i64:$rA))]>; 427let Uses = [CARRY] in { 428defm ADDE8 : XOForm_1rc<31, 138, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 429 "adde", "$rT, $rA, $rB", IntGeneral, 430 [(set i64:$rT, (adde i64:$rA, i64:$rB))]>; 431defm ADDME8 : XOForm_3rc<31, 234, 0, (outs g8rc:$rT), (ins g8rc:$rA), 432 "addme", "$rT, $rA", IntGeneral, 433 [(set i64:$rT, (adde i64:$rA, -1))]>; 434defm ADDZE8 : XOForm_3rc<31, 202, 0, (outs g8rc:$rT), (ins g8rc:$rA), 435 "addze", "$rT, $rA", IntGeneral, 436 [(set i64:$rT, (adde i64:$rA, 0))]>; 437defm SUBFE8 : XOForm_1rc<31, 136, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 438 "subfe", "$rT, $rA, $rB", IntGeneral, 439 [(set i64:$rT, (sube i64:$rB, i64:$rA))]>; 440defm SUBFME8 : XOForm_3rc<31, 232, 0, (outs g8rc:$rT), (ins g8rc:$rA), 441 "subfme", "$rT, $rA", IntGeneral, 442 [(set i64:$rT, (sube -1, i64:$rA))]>; 443defm SUBFZE8 : XOForm_3rc<31, 200, 0, (outs g8rc:$rT), (ins g8rc:$rA), 444 "subfze", "$rT, $rA", IntGeneral, 445 [(set i64:$rT, (sube 0, i64:$rA))]>; 446} 447 448 449defm MULHD : XOForm_1r<31, 73, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 450 "mulhd", "$rT, $rA, $rB", IntMulHW, 451 [(set i64:$rT, (mulhs i64:$rA, i64:$rB))]>; 452defm MULHDU : XOForm_1r<31, 9, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 453 "mulhdu", "$rT, $rA, $rB", IntMulHWU, 454 [(set i64:$rT, (mulhu i64:$rA, i64:$rB))]>; 455} 456} // Interpretation64Bit 457 458let isCompare = 1, neverHasSideEffects = 1 in { 459 def CMPD : XForm_16_ext<31, 0, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 460 "cmpd $crD, $rA, $rB", IntCompare>, isPPC64; 461 def CMPLD : XForm_16_ext<31, 32, (outs crrc:$crD), (ins g8rc:$rA, g8rc:$rB), 462 "cmpld $crD, $rA, $rB", IntCompare>, isPPC64; 463 def CMPDI : DForm_5_ext<11, (outs crrc:$crD), (ins g8rc:$rA, s16imm:$imm), 464 "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; 465 def CMPLDI : DForm_6_ext<10, (outs crrc:$dst), (ins g8rc:$src1, u16imm:$src2), 466 "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; 467} 468 469let neverHasSideEffects = 1 in { 470defm SLD : XForm_6r<31, 27, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 471 "sld", "$rA, $rS, $rB", IntRotateD, 472 [(set i64:$rA, (PPCshl i64:$rS, i32:$rB))]>, isPPC64; 473defm SRD : XForm_6r<31, 539, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 474 "srd", "$rA, $rS, $rB", IntRotateD, 475 [(set i64:$rA, (PPCsrl i64:$rS, i32:$rB))]>, isPPC64; 476defm SRAD : XForm_6rc<31, 794, (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB), 477 "srad", "$rA, $rS, $rB", IntRotateD, 478 [(set i64:$rA, (PPCsra i64:$rS, i32:$rB))]>, isPPC64; 479 480let Interpretation64Bit = 1 in { 481defm EXTSB8 : XForm_11r<31, 954, (outs g8rc:$rA), (ins g8rc:$rS), 482 "extsb", "$rA, $rS", IntSimple, 483 [(set i64:$rA, (sext_inreg i64:$rS, i8))]>; 484defm EXTSH8 : XForm_11r<31, 922, (outs g8rc:$rA), (ins g8rc:$rS), 485 "extsh", "$rA, $rS", IntSimple, 486 [(set i64:$rA, (sext_inreg i64:$rS, i16))]>; 487} // Interpretation64Bit 488 489defm EXTSW : XForm_11r<31, 986, (outs g8rc:$rA), (ins g8rc:$rS), 490 "extsw", "$rA, $rS", IntSimple, 491 [(set i64:$rA, (sext_inreg i64:$rS, i32))]>, isPPC64; 492let Interpretation64Bit = 1 in 493defm EXTSW_32_64 : XForm_11r<31, 986, (outs g8rc:$rA), (ins gprc:$rS), 494 "extsw", "$rA, $rS", IntSimple, 495 [(set i64:$rA, (sext i32:$rS))]>, isPPC64; 496 497defm SRADI : XSForm_1rc<31, 413, (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH), 498 "sradi", "$rA, $rS, $SH", IntRotateDI, 499 [(set i64:$rA, (sra i64:$rS, (i32 imm:$SH)))]>, isPPC64; 500defm CNTLZD : XForm_11r<31, 58, (outs g8rc:$rA), (ins g8rc:$rS), 501 "cntlzd", "$rA, $rS", IntGeneral, 502 [(set i64:$rA, (ctlz i64:$rS))]>; 503defm POPCNTD : XForm_11r<31, 506, (outs g8rc:$rA), (ins g8rc:$rS), 504 "popcntd", "$rA, $rS", IntGeneral, 505 [(set i64:$rA, (ctpop i64:$rS))]>; 506 507// popcntw also does a population count on the high 32 bits (storing the 508// results in the high 32-bits of the output). We'll ignore that here (which is 509// safe because we never separately use the high part of the 64-bit registers). 510defm POPCNTW : XForm_11r<31, 378, (outs gprc:$rA), (ins gprc:$rS), 511 "popcntw", "$rA, $rS", IntGeneral, 512 [(set i32:$rA, (ctpop i32:$rS))]>; 513 514defm DIVD : XOForm_1r<31, 489, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 515 "divd", "$rT, $rA, $rB", IntDivD, 516 [(set i64:$rT, (sdiv i64:$rA, i64:$rB))]>, isPPC64, 517 PPC970_DGroup_First, PPC970_DGroup_Cracked; 518defm DIVDU : XOForm_1r<31, 457, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 519 "divdu", "$rT, $rA, $rB", IntDivD, 520 [(set i64:$rT, (udiv i64:$rA, i64:$rB))]>, isPPC64, 521 PPC970_DGroup_First, PPC970_DGroup_Cracked; 522defm MULLD : XOForm_1r<31, 233, 0, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB), 523 "mulld", "$rT, $rA, $rB", IntMulHD, 524 [(set i64:$rT, (mul i64:$rA, i64:$rB))]>, isPPC64; 525} 526 527let neverHasSideEffects = 1 in { 528let isCommutable = 1 in { 529defm RLDIMI : MDForm_1r<30, 3, (outs g8rc:$rA), 530 (ins g8rc:$rSi, g8rc:$rS, u6imm:$SH, u6imm:$MBE), 531 "rldimi", "$rA, $rS, $SH, $MBE", IntRotateDI, 532 []>, isPPC64, RegConstraint<"$rSi = $rA">, 533 NoEncode<"$rSi">; 534} 535 536// Rotate instructions. 537defm RLDCL : MDSForm_1r<30, 8, 538 (outs g8rc:$rA), (ins g8rc:$rS, gprc:$rB, u6imm:$MBE), 539 "rldcl", "$rA, $rS, $rB, $MBE", IntRotateD, 540 []>, isPPC64; 541defm RLDICL : MDForm_1r<30, 0, 542 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 543 "rldicl", "$rA, $rS, $SH, $MBE", IntRotateDI, 544 []>, isPPC64; 545defm RLDICR : MDForm_1r<30, 1, 546 (outs g8rc:$rA), (ins g8rc:$rS, u6imm:$SH, u6imm:$MBE), 547 "rldicr", "$rA, $rS, $SH, $MBE", IntRotateDI, 548 []>, isPPC64; 549 550let Interpretation64Bit = 1 in { 551defm RLWINM8 : MForm_2r<21, (outs g8rc:$rA), 552 (ins g8rc:$rS, u5imm:$SH, u5imm:$MB, u5imm:$ME), 553 "rlwinm", "$rA, $rS, $SH, $MB, $ME", IntGeneral, 554 []>; 555 556let isSelect = 1 in 557def ISEL8 : AForm_4<31, 15, 558 (outs g8rc:$rT), (ins g8rc_nox0:$rA, g8rc:$rB, crbitrc:$cond), 559 "isel $rT, $rA, $rB, $cond", IntGeneral, 560 []>; 561} // Interpretation64Bit 562} // neverHasSideEffects = 1 563} // End FXU Operations. 564 565 566//===----------------------------------------------------------------------===// 567// Load/Store instructions. 568// 569 570 571// Sign extending loads. 572let canFoldAsLoad = 1, PPC970_Unit = 2 in { 573let Interpretation64Bit = 1 in 574def LHA8: DForm_1<42, (outs g8rc:$rD), (ins memri:$src), 575 "lha $rD, $src", LdStLHA, 576 [(set i64:$rD, (sextloadi16 iaddr:$src))]>, 577 PPC970_DGroup_Cracked; 578def LWA : DSForm_1<58, 2, (outs g8rc:$rD), (ins memrix:$src), 579 "lwa $rD, $src", LdStLWA, 580 [(set i64:$rD, 581 (aligned4sextloadi32 ixaddr:$src))]>, isPPC64, 582 PPC970_DGroup_Cracked; 583let Interpretation64Bit = 1 in 584def LHAX8: XForm_1<31, 343, (outs g8rc:$rD), (ins memrr:$src), 585 "lhax $rD, $src", LdStLHA, 586 [(set i64:$rD, (sextloadi16 xaddr:$src))]>, 587 PPC970_DGroup_Cracked; 588def LWAX : XForm_1<31, 341, (outs g8rc:$rD), (ins memrr:$src), 589 "lwax $rD, $src", LdStLHA, 590 [(set i64:$rD, (sextloadi32 xaddr:$src))]>, isPPC64, 591 PPC970_DGroup_Cracked; 592 593// Update forms. 594let mayLoad = 1, neverHasSideEffects = 1 in { 595let Interpretation64Bit = 1 in 596def LHAU8 : DForm_1<43, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 597 (ins memri:$addr), 598 "lhau $rD, $addr", LdStLHAU, 599 []>, RegConstraint<"$addr.reg = $ea_result">, 600 NoEncode<"$ea_result">; 601// NO LWAU! 602 603let Interpretation64Bit = 1 in 604def LHAUX8 : XForm_1<31, 375, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 605 (ins memrr:$addr), 606 "lhaux $rD, $addr", LdStLHAU, 607 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 608 NoEncode<"$ea_result">; 609def LWAUX : XForm_1<31, 373, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 610 (ins memrr:$addr), 611 "lwaux $rD, $addr", LdStLHAU, 612 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 613 NoEncode<"$ea_result">, isPPC64; 614} 615} 616 617let Interpretation64Bit = 1 in { 618// Zero extending loads. 619let canFoldAsLoad = 1, PPC970_Unit = 2 in { 620def LBZ8 : DForm_1<34, (outs g8rc:$rD), (ins memri:$src), 621 "lbz $rD, $src", LdStLoad, 622 [(set i64:$rD, (zextloadi8 iaddr:$src))]>; 623def LHZ8 : DForm_1<40, (outs g8rc:$rD), (ins memri:$src), 624 "lhz $rD, $src", LdStLoad, 625 [(set i64:$rD, (zextloadi16 iaddr:$src))]>; 626def LWZ8 : DForm_1<32, (outs g8rc:$rD), (ins memri:$src), 627 "lwz $rD, $src", LdStLoad, 628 [(set i64:$rD, (zextloadi32 iaddr:$src))]>, isPPC64; 629 630def LBZX8 : XForm_1<31, 87, (outs g8rc:$rD), (ins memrr:$src), 631 "lbzx $rD, $src", LdStLoad, 632 [(set i64:$rD, (zextloadi8 xaddr:$src))]>; 633def LHZX8 : XForm_1<31, 279, (outs g8rc:$rD), (ins memrr:$src), 634 "lhzx $rD, $src", LdStLoad, 635 [(set i64:$rD, (zextloadi16 xaddr:$src))]>; 636def LWZX8 : XForm_1<31, 23, (outs g8rc:$rD), (ins memrr:$src), 637 "lwzx $rD, $src", LdStLoad, 638 [(set i64:$rD, (zextloadi32 xaddr:$src))]>; 639 640 641// Update forms. 642let mayLoad = 1, neverHasSideEffects = 1 in { 643def LBZU8 : DForm_1<35, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 644 "lbzu $rD, $addr", LdStLoadUpd, 645 []>, RegConstraint<"$addr.reg = $ea_result">, 646 NoEncode<"$ea_result">; 647def LHZU8 : DForm_1<41, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 648 "lhzu $rD, $addr", LdStLoadUpd, 649 []>, RegConstraint<"$addr.reg = $ea_result">, 650 NoEncode<"$ea_result">; 651def LWZU8 : DForm_1<33, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memri:$addr), 652 "lwzu $rD, $addr", LdStLoadUpd, 653 []>, RegConstraint<"$addr.reg = $ea_result">, 654 NoEncode<"$ea_result">; 655 656def LBZUX8 : XForm_1<31, 119, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 657 (ins memrr:$addr), 658 "lbzux $rD, $addr", LdStLoadUpd, 659 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 660 NoEncode<"$ea_result">; 661def LHZUX8 : XForm_1<31, 311, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 662 (ins memrr:$addr), 663 "lhzux $rD, $addr", LdStLoadUpd, 664 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 665 NoEncode<"$ea_result">; 666def LWZUX8 : XForm_1<31, 55, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 667 (ins memrr:$addr), 668 "lwzux $rD, $addr", LdStLoadUpd, 669 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 670 NoEncode<"$ea_result">; 671} 672} 673} // Interpretation64Bit 674 675 676// Full 8-byte loads. 677let canFoldAsLoad = 1, PPC970_Unit = 2 in { 678def LD : DSForm_1<58, 0, (outs g8rc:$rD), (ins memrix:$src), 679 "ld $rD, $src", LdStLD, 680 [(set i64:$rD, (aligned4load ixaddr:$src))]>, isPPC64; 681// The following three definitions are selected for small code model only. 682// Otherwise, we need to create two instructions to form a 32-bit offset, 683// so we have a custom matcher for TOC_ENTRY in PPCDAGToDAGIsel::Select(). 684def LDtoc: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 685 "#LDtoc", 686 [(set i64:$rD, 687 (PPCtoc_entry tglobaladdr:$disp, i64:$reg))]>, isPPC64; 688def LDtocJTI: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 689 "#LDtocJTI", 690 [(set i64:$rD, 691 (PPCtoc_entry tjumptable:$disp, i64:$reg))]>, isPPC64; 692def LDtocCPT: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc:$reg), 693 "#LDtocCPT", 694 [(set i64:$rD, 695 (PPCtoc_entry tconstpool:$disp, i64:$reg))]>, isPPC64; 696 697let hasSideEffects = 1, isCodeGenOnly = 1 in { 698let RST = 2, DS = 2 in 699def LDinto_toc: DSForm_1a<58, 0, (outs), (ins g8rc:$reg), 700 "ld 2, 8($reg)", LdStLD, 701 [(PPCload_toc i64:$reg)]>, isPPC64; 702 703let RST = 2, DS = 10, RA = 1 in 704def LDtoc_restore : DSForm_1a<58, 0, (outs), (ins), 705 "ld 2, 40(1)", LdStLD, 706 [(PPCtoc_restore)]>, isPPC64; 707} 708def LDX : XForm_1<31, 21, (outs g8rc:$rD), (ins memrr:$src), 709 "ldx $rD, $src", LdStLD, 710 [(set i64:$rD, (load xaddr:$src))]>, isPPC64; 711def LDBRX : XForm_1<31, 532, (outs g8rc:$rD), (ins memrr:$src), 712 "ldbrx $rD, $src", LdStLoad, 713 [(set i64:$rD, (PPClbrx xoaddr:$src, i64))]>, isPPC64; 714 715let mayLoad = 1, neverHasSideEffects = 1 in { 716def LDU : DSForm_1<58, 1, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), (ins memrix:$addr), 717 "ldu $rD, $addr", LdStLDU, 718 []>, RegConstraint<"$addr.reg = $ea_result">, isPPC64, 719 NoEncode<"$ea_result">; 720 721def LDUX : XForm_1<31, 53, (outs g8rc:$rD, ptr_rc_nor0:$ea_result), 722 (ins memrr:$addr), 723 "ldux $rD, $addr", LdStLDU, 724 []>, RegConstraint<"$addr.ptrreg = $ea_result">, 725 NoEncode<"$ea_result">, isPPC64; 726} 727} 728 729def : Pat<(PPCload ixaddr:$src), 730 (LD ixaddr:$src)>; 731def : Pat<(PPCload xaddr:$src), 732 (LDX xaddr:$src)>; 733 734// Support for medium and large code model. 735def ADDIStocHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 736 "#ADDIStocHA", 737 [(set i64:$rD, 738 (PPCaddisTocHA i64:$reg, tglobaladdr:$disp))]>, 739 isPPC64; 740def LDtocL: Pseudo<(outs g8rc:$rD), (ins tocentry:$disp, g8rc_nox0:$reg), 741 "#LDtocL", 742 [(set i64:$rD, 743 (PPCldTocL tglobaladdr:$disp, i64:$reg))]>, isPPC64; 744def ADDItocL: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, tocentry:$disp), 745 "#ADDItocL", 746 [(set i64:$rD, 747 (PPCaddiTocL i64:$reg, tglobaladdr:$disp))]>, isPPC64; 748 749// Support for thread-local storage. 750def ADDISgotTprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 751 "#ADDISgotTprelHA", 752 [(set i64:$rD, 753 (PPCaddisGotTprelHA i64:$reg, 754 tglobaltlsaddr:$disp))]>, 755 isPPC64; 756def LDgotTprelL: Pseudo<(outs g8rc:$rD), (ins s16imm64:$disp, g8rc_nox0:$reg), 757 "#LDgotTprelL", 758 [(set i64:$rD, 759 (PPCldGotTprelL tglobaltlsaddr:$disp, i64:$reg))]>, 760 isPPC64; 761def : Pat<(PPCaddTls i64:$in, tglobaltlsaddr:$g), 762 (ADD8TLS $in, tglobaltlsaddr:$g)>; 763def ADDIStlsgdHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 764 "#ADDIStlsgdHA", 765 [(set i64:$rD, 766 (PPCaddisTlsgdHA i64:$reg, tglobaltlsaddr:$disp))]>, 767 isPPC64; 768def ADDItlsgdL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 769 "#ADDItlsgdL", 770 [(set i64:$rD, 771 (PPCaddiTlsgdL i64:$reg, tglobaltlsaddr:$disp))]>, 772 isPPC64; 773def GETtlsADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 774 "#GETtlsADDR", 775 [(set i64:$rD, 776 (PPCgetTlsAddr i64:$reg, tglobaltlsaddr:$sym))]>, 777 isPPC64; 778def ADDIStlsldHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 779 "#ADDIStlsldHA", 780 [(set i64:$rD, 781 (PPCaddisTlsldHA i64:$reg, tglobaltlsaddr:$disp))]>, 782 isPPC64; 783def ADDItlsldL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 784 "#ADDItlsldL", 785 [(set i64:$rD, 786 (PPCaddiTlsldL i64:$reg, tglobaltlsaddr:$disp))]>, 787 isPPC64; 788def GETtlsldADDR : Pseudo<(outs g8rc:$rD), (ins g8rc:$reg, tlsgd:$sym), 789 "#GETtlsldADDR", 790 [(set i64:$rD, 791 (PPCgetTlsldAddr i64:$reg, tglobaltlsaddr:$sym))]>, 792 isPPC64; 793def ADDISdtprelHA: Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 794 "#ADDISdtprelHA", 795 [(set i64:$rD, 796 (PPCaddisDtprelHA i64:$reg, 797 tglobaltlsaddr:$disp))]>, 798 isPPC64; 799def ADDIdtprelL : Pseudo<(outs g8rc:$rD), (ins g8rc_nox0:$reg, s16imm64:$disp), 800 "#ADDIdtprelL", 801 [(set i64:$rD, 802 (PPCaddiDtprelL i64:$reg, tglobaltlsaddr:$disp))]>, 803 isPPC64; 804 805let PPC970_Unit = 2 in { 806let Interpretation64Bit = 1 in { 807// Truncating stores. 808def STB8 : DForm_1<38, (outs), (ins g8rc:$rS, memri:$src), 809 "stb $rS, $src", LdStStore, 810 [(truncstorei8 i64:$rS, iaddr:$src)]>; 811def STH8 : DForm_1<44, (outs), (ins g8rc:$rS, memri:$src), 812 "sth $rS, $src", LdStStore, 813 [(truncstorei16 i64:$rS, iaddr:$src)]>; 814def STW8 : DForm_1<36, (outs), (ins g8rc:$rS, memri:$src), 815 "stw $rS, $src", LdStStore, 816 [(truncstorei32 i64:$rS, iaddr:$src)]>; 817def STBX8 : XForm_8<31, 215, (outs), (ins g8rc:$rS, memrr:$dst), 818 "stbx $rS, $dst", LdStStore, 819 [(truncstorei8 i64:$rS, xaddr:$dst)]>, 820 PPC970_DGroup_Cracked; 821def STHX8 : XForm_8<31, 407, (outs), (ins g8rc:$rS, memrr:$dst), 822 "sthx $rS, $dst", LdStStore, 823 [(truncstorei16 i64:$rS, xaddr:$dst)]>, 824 PPC970_DGroup_Cracked; 825def STWX8 : XForm_8<31, 151, (outs), (ins g8rc:$rS, memrr:$dst), 826 "stwx $rS, $dst", LdStStore, 827 [(truncstorei32 i64:$rS, xaddr:$dst)]>, 828 PPC970_DGroup_Cracked; 829} // Interpretation64Bit 830 831// Normal 8-byte stores. 832def STD : DSForm_1<62, 0, (outs), (ins g8rc:$rS, memrix:$dst), 833 "std $rS, $dst", LdStSTD, 834 [(aligned4store i64:$rS, ixaddr:$dst)]>, isPPC64; 835def STDX : XForm_8<31, 149, (outs), (ins g8rc:$rS, memrr:$dst), 836 "stdx $rS, $dst", LdStSTD, 837 [(store i64:$rS, xaddr:$dst)]>, isPPC64, 838 PPC970_DGroup_Cracked; 839def STDBRX: XForm_8<31, 660, (outs), (ins g8rc:$rS, memrr:$dst), 840 "stdbrx $rS, $dst", LdStStore, 841 [(PPCstbrx i64:$rS, xoaddr:$dst, i64)]>, isPPC64, 842 PPC970_DGroup_Cracked; 843} 844 845// Stores with Update (pre-inc). 846let PPC970_Unit = 2, mayStore = 1 in { 847let Interpretation64Bit = 1 in { 848def STBU8 : DForm_1<39, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 849 "stbu $rS, $dst", LdStStoreUpd, []>, 850 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 851def STHU8 : DForm_1<45, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 852 "sthu $rS, $dst", LdStStoreUpd, []>, 853 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 854def STWU8 : DForm_1<37, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memri:$dst), 855 "stwu $rS, $dst", LdStStoreUpd, []>, 856 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">; 857def STDU : DSForm_1<62, 1, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrix:$dst), 858 "stdu $rS, $dst", LdStSTDU, []>, 859 RegConstraint<"$dst.reg = $ea_res">, NoEncode<"$ea_res">, 860 isPPC64; 861 862def STBUX8: XForm_8<31, 247, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 863 "stbux $rS, $dst", LdStStoreUpd, []>, 864 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 865 PPC970_DGroup_Cracked; 866def STHUX8: XForm_8<31, 439, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 867 "sthux $rS, $dst", LdStStoreUpd, []>, 868 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 869 PPC970_DGroup_Cracked; 870def STWUX8: XForm_8<31, 183, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 871 "stwux $rS, $dst", LdStStoreUpd, []>, 872 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 873 PPC970_DGroup_Cracked; 874} // Interpretation64Bit 875 876def STDUX : XForm_8<31, 181, (outs ptr_rc_nor0:$ea_res), (ins g8rc:$rS, memrr:$dst), 877 "stdux $rS, $dst", LdStSTDU, []>, 878 RegConstraint<"$dst.ptrreg = $ea_res">, NoEncode<"$ea_res">, 879 PPC970_DGroup_Cracked, isPPC64; 880} 881 882// Patterns to match the pre-inc stores. We can't put the patterns on 883// the instruction definitions directly as ISel wants the address base 884// and offset to be separate operands, not a single complex operand. 885def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 886 (STBU8 $rS, iaddroff:$ptroff, $ptrreg)>; 887def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 888 (STHU8 $rS, iaddroff:$ptroff, $ptrreg)>; 889def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 890 (STWU8 $rS, iaddroff:$ptroff, $ptrreg)>; 891def : Pat<(aligned4pre_store i64:$rS, iPTR:$ptrreg, iaddroff:$ptroff), 892 (STDU $rS, iaddroff:$ptroff, $ptrreg)>; 893 894def : Pat<(pre_truncsti8 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 895 (STBUX8 $rS, $ptrreg, $ptroff)>; 896def : Pat<(pre_truncsti16 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 897 (STHUX8 $rS, $ptrreg, $ptroff)>; 898def : Pat<(pre_truncsti32 i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 899 (STWUX8 $rS, $ptrreg, $ptroff)>; 900def : Pat<(pre_store i64:$rS, iPTR:$ptrreg, iPTR:$ptroff), 901 (STDUX $rS, $ptrreg, $ptroff)>; 902 903 904//===----------------------------------------------------------------------===// 905// Floating point instructions. 906// 907 908 909let PPC970_Unit = 3, neverHasSideEffects = 1, 910 Uses = [RM] in { // FPU Operations. 911defm FCFID : XForm_26r<63, 846, (outs f8rc:$frD), (ins f8rc:$frB), 912 "fcfid", "$frD, $frB", FPGeneral, 913 [(set f64:$frD, (PPCfcfid f64:$frB))]>, isPPC64; 914defm FCTIDZ : XForm_26r<63, 815, (outs f8rc:$frD), (ins f8rc:$frB), 915 "fctidz", "$frD, $frB", FPGeneral, 916 [(set f64:$frD, (PPCfctidz f64:$frB))]>, isPPC64; 917 918defm FCFIDU : XForm_26r<63, 974, (outs f8rc:$frD), (ins f8rc:$frB), 919 "fcfidu", "$frD, $frB", FPGeneral, 920 [(set f64:$frD, (PPCfcfidu f64:$frB))]>, isPPC64; 921defm FCFIDS : XForm_26r<59, 846, (outs f4rc:$frD), (ins f8rc:$frB), 922 "fcfids", "$frD, $frB", FPGeneral, 923 [(set f32:$frD, (PPCfcfids f64:$frB))]>, isPPC64; 924defm FCFIDUS : XForm_26r<59, 974, (outs f4rc:$frD), (ins f8rc:$frB), 925 "fcfidus", "$frD, $frB", FPGeneral, 926 [(set f32:$frD, (PPCfcfidus f64:$frB))]>, isPPC64; 927defm FCTIDUZ : XForm_26r<63, 943, (outs f8rc:$frD), (ins f8rc:$frB), 928 "fctiduz", "$frD, $frB", FPGeneral, 929 [(set f64:$frD, (PPCfctiduz f64:$frB))]>, isPPC64; 930defm FCTIWUZ : XForm_26r<63, 143, (outs f8rc:$frD), (ins f8rc:$frB), 931 "fctiwuz", "$frD, $frB", FPGeneral, 932 [(set f64:$frD, (PPCfctiwuz f64:$frB))]>, isPPC64; 933} 934 935 936//===----------------------------------------------------------------------===// 937// Instruction Patterns 938// 939 940// Extensions and truncates to/from 32-bit regs. 941def : Pat<(i64 (zext i32:$in)), 942 (RLDICL (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32), 943 0, 32)>; 944def : Pat<(i64 (anyext i32:$in)), 945 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), $in, sub_32)>; 946def : Pat<(i32 (trunc i64:$in)), 947 (EXTRACT_SUBREG $in, sub_32)>; 948 949// Extending loads with i64 targets. 950def : Pat<(zextloadi1 iaddr:$src), 951 (LBZ8 iaddr:$src)>; 952def : Pat<(zextloadi1 xaddr:$src), 953 (LBZX8 xaddr:$src)>; 954def : Pat<(extloadi1 iaddr:$src), 955 (LBZ8 iaddr:$src)>; 956def : Pat<(extloadi1 xaddr:$src), 957 (LBZX8 xaddr:$src)>; 958def : Pat<(extloadi8 iaddr:$src), 959 (LBZ8 iaddr:$src)>; 960def : Pat<(extloadi8 xaddr:$src), 961 (LBZX8 xaddr:$src)>; 962def : Pat<(extloadi16 iaddr:$src), 963 (LHZ8 iaddr:$src)>; 964def : Pat<(extloadi16 xaddr:$src), 965 (LHZX8 xaddr:$src)>; 966def : Pat<(extloadi32 iaddr:$src), 967 (LWZ8 iaddr:$src)>; 968def : Pat<(extloadi32 xaddr:$src), 969 (LWZX8 xaddr:$src)>; 970 971// Standard shifts. These are represented separately from the real shifts above 972// so that we can distinguish between shifts that allow 6-bit and 7-bit shift 973// amounts. 974def : Pat<(sra i64:$rS, i32:$rB), 975 (SRAD $rS, $rB)>; 976def : Pat<(srl i64:$rS, i32:$rB), 977 (SRD $rS, $rB)>; 978def : Pat<(shl i64:$rS, i32:$rB), 979 (SLD $rS, $rB)>; 980 981// SHL/SRL 982def : Pat<(shl i64:$in, (i32 imm:$imm)), 983 (RLDICR $in, imm:$imm, (SHL64 imm:$imm))>; 984def : Pat<(srl i64:$in, (i32 imm:$imm)), 985 (RLDICL $in, (SRL64 imm:$imm), imm:$imm)>; 986 987// ROTL 988def : Pat<(rotl i64:$in, i32:$sh), 989 (RLDCL $in, $sh, 0)>; 990def : Pat<(rotl i64:$in, (i32 imm:$imm)), 991 (RLDICL $in, imm:$imm, 0)>; 992 993// Hi and Lo for Darwin Global Addresses. 994def : Pat<(PPChi tglobaladdr:$in, 0), (LIS8 tglobaladdr:$in)>; 995def : Pat<(PPClo tglobaladdr:$in, 0), (LI8 tglobaladdr:$in)>; 996def : Pat<(PPChi tconstpool:$in , 0), (LIS8 tconstpool:$in)>; 997def : Pat<(PPClo tconstpool:$in , 0), (LI8 tconstpool:$in)>; 998def : Pat<(PPChi tjumptable:$in , 0), (LIS8 tjumptable:$in)>; 999def : Pat<(PPClo tjumptable:$in , 0), (LI8 tjumptable:$in)>; 1000def : Pat<(PPChi tblockaddress:$in, 0), (LIS8 tblockaddress:$in)>; 1001def : Pat<(PPClo tblockaddress:$in, 0), (LI8 tblockaddress:$in)>; 1002def : Pat<(PPChi tglobaltlsaddr:$g, i64:$in), 1003 (ADDIS8 $in, tglobaltlsaddr:$g)>; 1004def : Pat<(PPClo tglobaltlsaddr:$g, i64:$in), 1005 (ADDI8 $in, tglobaltlsaddr:$g)>; 1006def : Pat<(add i64:$in, (PPChi tglobaladdr:$g, 0)), 1007 (ADDIS8 $in, tglobaladdr:$g)>; 1008def : Pat<(add i64:$in, (PPChi tconstpool:$g, 0)), 1009 (ADDIS8 $in, tconstpool:$g)>; 1010def : Pat<(add i64:$in, (PPChi tjumptable:$g, 0)), 1011 (ADDIS8 $in, tjumptable:$g)>; 1012def : Pat<(add i64:$in, (PPChi tblockaddress:$g, 0)), 1013 (ADDIS8 $in, tblockaddress:$g)>; 1014 1015// Patterns to match r+r indexed loads and stores for 1016// addresses without at least 4-byte alignment. 1017def : Pat<(i64 (unaligned4sextloadi32 xoaddr:$src)), 1018 (LWAX xoaddr:$src)>; 1019def : Pat<(i64 (unaligned4load xoaddr:$src)), 1020 (LDX xoaddr:$src)>; 1021def : Pat<(unaligned4store i64:$rS, xoaddr:$dst), 1022 (STDX $rS, xoaddr:$dst)>; 1023 1024