SIInstrFormats.td revision 7c52866a14e0c928e9be020b9dc8e585f0965212 
1//===-- SIInstrFormats.td - SI Instruction Formats ------------------------===//
2//
3//                     The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// SI Instruction format definitions.
11//
12// Instructions with _32 take 32-bit operands.
13// Instructions with _64 take 64-bit operands.
14//
15// VOP_* instructions can use either a 32-bit or 64-bit encoding.  The 32-bit
16// encoding is the standard encoding, but instruction that make use of
17// any of the instruction modifiers must use the 64-bit encoding.
18//
19// Instructions with _e32 use the 32-bit encoding.
20// Instructions with _e64 use the 64-bit encoding.
21//
22//===----------------------------------------------------------------------===//
23
24class VOP3b_2IN <bits<9> op, string opName, RegisterClass dstClass,
25                 RegisterClass src0Class, RegisterClass src1Class,
26                 list<dag> pattern>
27  : VOP3b <op, (outs dstClass:$vdst),
28               (ins src0Class:$src0, src1Class:$src1, InstFlag:$src2, InstFlag:$sdst,
29                    InstFlag:$omod, InstFlag:$neg),
30           opName, pattern
31>;
32
33
34class VOP3_1_32 <bits<9> op, string opName, list<dag> pattern>
35  : VOP3b_2IN <op, opName, SReg_1, AllReg_32, VReg_32, pattern>;
36
37class VOP3_32 <bits<9> op, string opName, list<dag> pattern>
38  : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
39
40class VOP3_64 <bits<9> op, string opName, list<dag> pattern>
41  : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>;
42
43
44class SOP1_32 <bits<8> op, string opName, list<dag> pattern>
45  : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>;
46
47class SOP1_64 <bits<8> op, string opName, list<dag> pattern>
48  : SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>;
49
50class SOP2_32 <bits<7> op, string opName, list<dag> pattern>
51  : SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
52
53class SOP2_64 <bits<7> op, string opName, list<dag> pattern>
54  : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
55
56class SOP2_VCC <bits<7> op, string opName, list<dag> pattern>
57  : SOP2 <op, (outs SReg_1:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
58
59class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
60                   string opName, list<dag> pattern> : 
61  VOP1 <
62    op, (outs vrc:$dst), (ins arc:$src0), opName, pattern
63  >;
64
65multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> {
66  def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>;
67  def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
68                      opName, []
69  >;
70}
71
72multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> {
73
74  def _e32 : VOP1_Helper <op, VReg_64, AllReg_64, opName, pattern>;
75
76  def _e64 : VOP3_64 <
77    {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
78    opName, []
79  >;
80}
81
82class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc,
83                   string opName, list<dag> pattern> :
84  VOP2 <
85    op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1), opName, pattern
86  >;
87
88multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> {
89
90  def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>;
91
92  def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
93                      opName, []
94  >;
95}
96
97multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> {
98  def _e32: VOP2_Helper <op, VReg_64, AllReg_64, opName, pattern>;
99
100  def _e64 : VOP3_64 <
101    {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
102    opName, []
103  >;
104}
105
106class SOPK_32 <bits<5> op, string opName, list<dag> pattern>
107  : SOPK <op, (outs SReg_32:$dst), (ins i16imm:$src0), opName, pattern>;
108
109class SOPK_64 <bits<5> op, string opName, list<dag> pattern>
110  : SOPK <op, (outs SReg_64:$dst), (ins i16imm:$src0), opName, pattern>;
111
112class VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc,
113                 string opName, list<dag> pattern> :
114  VOPC <
115    op, (ins arc:$src0, vrc:$src1), opName, pattern
116  >;
117
118multiclass VOPC_32 <bits<9> op, string opName, list<dag> pattern> {
119
120  def _e32 : VOPC_Helper <
121    {op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
122    VReg_32, AllReg_32, opName, pattern
123  >;
124
125  def _e64 : VOP3_1_32 <
126    op,
127    opName, pattern
128  >;
129}
130
131multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> {
132
133  def _e32 : VOPC_Helper <op, VReg_64, AllReg_64, opName, pattern>;
134
135  def _e64 : VOP3_64 <
136    {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
137    opName, []
138  >;
139}
140
141class SOPC_32 <bits<7> op, string opName, list<dag> pattern>
142  : SOPC <op, (outs SCCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>;
143
144class SOPC_64 <bits<7> op, string opName, list<dag> pattern>
145  : SOPC <op, (outs SCCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>;
146
147class MIMG_Load_Helper <bits<7> op, string asm> : MIMG <
148  op,
149  (outs VReg_128:$vdata),
150  (ins i32imm:$dmask, i1imm:$unorm, i1imm:$glc, i1imm:$da, i1imm:$r128,
151       i1imm:$tfe, i1imm:$lwe, i1imm:$slc, VReg_32:$vaddr,
152       GPR4Align<SReg_256>:$srsrc, GPR4Align<SReg_128>:$ssamp),
153  asm,
154  []> {
155  let mayLoad = 1;
156  let mayStore = 0;
157}
158
159class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
160  op,
161  (outs),
162  (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc,
163   i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr,
164   GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
165  asm,
166  []> {
167  let mayStore = 1;
168  let mayLoad = 0;
169}
170
171class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
172  op,
173  (outs regClass:$dst),
174  (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
175       i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc,
176       i1imm:$tfe, SReg_32:$soffset),
177  asm,
178  []> {
179  let mayLoad = 1;
180  let mayStore = 0;
181}
182
183class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF <
184  op,
185  (outs regClass:$dst),
186  (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
187       i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc,
188       i1imm:$slc, i1imm:$tfe, SReg_32:$soffset),
189  asm,
190  []> {
191  let mayLoad = 1;
192  let mayStore = 0;
193}
194
195multiclass SMRD_Helper <bits<5> op, string asm, RegisterClass dstClass> {
196  def _IMM : SMRD <
197             op, 1,
198             (outs dstClass:$dst),
199             (ins GPR2Align<SReg_64>:$sbase, i32imm:$offset),
200             asm,
201             []
202  >;
203
204  def _SGPR : SMRD <
205              op, 0,
206              (outs dstClass:$dst),
207              (ins GPR2Align<SReg_64>:$sbase, SReg_32:$soff),
208              asm,
209              []
210  >;
211}
212
213