| 7740daa8ba053294b7448556c049cf6778711d66 |
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10-Jul-2013 |
Michel Danzer <michel.daenzer@amd.com> |
R600/SI: Initial support for LDS/GDS instructions
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186009 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrFormats.td
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| fbdd3181201434598ed2cc91ba2ef37e11aae175 |
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20-May-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Use the same names for VOP3 operands and encoding fields
This makes it possible to reorder the operands without breaking the
encoding.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@182283 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrFormats.td
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| e340b7728a0936429fc1938c36fc4bdccb5fdc19 |
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06-Apr-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Use same names for corresponding MUBUF operands and encoding fields
The code emitter knows how to encode operands whose name matches one of
the encoding fields. If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding. Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.
Reviewed-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178930 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrFormats.td
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| f4632b58c7df992e77a4be3927e7aa72c1235dff |
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01-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: remove GPR*AlignEncode
It's much easier to specify the encoding with tablegen directly.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176344 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrFormats.td
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| 8c0b3a0d31f2eb04d96f63b72e189fe82f8b4a4f |
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21-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.td
Those two files got mixed up.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175746 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrFormats.td
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| e9ba1830df2efef3da113a740909195e839ebd36 |
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16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: nuke SReg_1 v3
It's completely unnecessary and can be replace with proper
SReg_64 handling instead.
This actually fixes a piglit test on SI.
v2: use correct register class in addRegisterClass,
set special classes as not allocatable
v3: revert setting special classes as not allocateable
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175355 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrFormats.td
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| 8e4eebcecf291386a321d0f8582b8a57841ea8c9 |
|
16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: replace AllReg_* with [SV]Src_* v2
Mark all the operands that can also have an immediate.
v2: SOFFSET is also an SSrc_32 operand
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175353 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrFormats.td
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| 305fefbb65c3df7bf5b3a8f6157efe24652c1e56 |
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16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: fix VOPC encoding v2
Previously it only worked because of coincident.
v2: fix 64bit versions, use 0x80 (inline 0) instead of SGPR0
for the unused SRC2
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175352 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrFormats.td
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| 7c52866a14e0c928e9be020b9dc8e585f0965212 |
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16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: move *_Helper definitions to SIInstrFormat.td
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175351 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrFormats.td
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| f98f2ce29e6e2996fa58f38979143eceaa818335 |
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11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrFormats.td
|