brw_misc_state.c revision 1e645b365900cf1c71ca5594bd6b549a1f203040
1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33 34#include "intel_batchbuffer.h" 35#include "intel_regions.h" 36 37#include "brw_context.h" 38#include "brw_state.h" 39#include "brw_defines.h" 40 41 42 43 44 45/*********************************************************************** 46 * Blend color 47 */ 48 49static void upload_blend_constant_color(struct brw_context *brw) 50{ 51 struct brw_blend_constant_color bcc; 52 53 memset(&bcc, 0, sizeof(bcc)); 54 bcc.header.opcode = CMD_BLEND_CONSTANT_COLOR; 55 bcc.header.length = sizeof(bcc)/4-2; 56 bcc.blend_constant_color[0] = brw->attribs.Color->BlendColor[0]; 57 bcc.blend_constant_color[1] = brw->attribs.Color->BlendColor[1]; 58 bcc.blend_constant_color[2] = brw->attribs.Color->BlendColor[2]; 59 bcc.blend_constant_color[3] = brw->attribs.Color->BlendColor[3]; 60 61 BRW_CACHED_BATCH_STRUCT(brw, &bcc); 62} 63 64 65const struct brw_tracked_state brw_blend_constant_color = { 66 .dirty = { 67 .mesa = _NEW_COLOR, 68 .brw = 0, 69 .cache = 0 70 }, 71 .emit = upload_blend_constant_color 72}; 73 74/** 75 * Upload the binding table pointers, which point each stage's array of surface 76 * state pointers. 77 * 78 * The binding table pointers are relative to the surface state base address, 79 * which is 0. 80 */ 81static void upload_binding_table_pointers(struct brw_context *brw) 82{ 83 struct intel_context *intel = &brw->intel; 84 85 BEGIN_BATCH(6, IGNORE_CLIPRECTS); 86 OUT_BATCH(CMD_BINDING_TABLE_PTRS << 16 | (6 - 2)); 87 OUT_BATCH(0); /* vs */ 88 OUT_BATCH(0); /* gs */ 89 OUT_BATCH(0); /* clip */ 90 OUT_BATCH(0); /* sf */ 91 OUT_RELOC(brw->wm.bind_bo, 92 I915_GEM_DOMAIN_SAMPLER, 0, 93 0); 94 ADVANCE_BATCH(); 95} 96 97const struct brw_tracked_state brw_binding_table_pointers = { 98 .dirty = { 99 .mesa = 0, 100 .brw = BRW_NEW_BATCH, 101 .cache = CACHE_NEW_SURF_BIND, 102 }, 103 .emit = upload_binding_table_pointers, 104}; 105 106 107/** 108 * Upload pointers to the per-stage state. 109 * 110 * The state pointers in this packet are all relative to the general state 111 * base address set by CMD_STATE_BASE_ADDRESS, which is 0. 112 */ 113static void upload_pipelined_state_pointers(struct brw_context *brw ) 114{ 115 struct intel_context *intel = &brw->intel; 116 117 BEGIN_BATCH(7, IGNORE_CLIPRECTS); 118 OUT_BATCH(CMD_PIPELINED_STATE_POINTERS << 16 | (7 - 2)); 119 OUT_RELOC(brw->vs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); 120 if (brw->gs.prog_active) 121 OUT_RELOC(brw->gs.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); 122 else 123 OUT_BATCH(0); 124 if (!brw->metaops.active) 125 OUT_RELOC(brw->clip.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 1); 126 else 127 OUT_BATCH(0); 128 OUT_RELOC(brw->sf.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); 129 OUT_RELOC(brw->wm.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); 130 OUT_RELOC(brw->cc.state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0); 131 ADVANCE_BATCH(); 132 133 brw->state.dirty.brw |= BRW_NEW_PSP; 134} 135 136#if 0 137/* Combined into brw_psp_urb_cbs */ 138const struct brw_tracked_state brw_pipelined_state_pointers = { 139 .dirty = { 140 .mesa = 0, 141 .brw = BRW_NEW_METAOPS | BRW_NEW_BATCH, 142 .cache = (CACHE_NEW_VS_UNIT | 143 CACHE_NEW_GS_UNIT | 144 CACHE_NEW_GS_PROG | 145 CACHE_NEW_CLIP_UNIT | 146 CACHE_NEW_SF_UNIT | 147 CACHE_NEW_WM_UNIT | 148 CACHE_NEW_CC_UNIT) 149 }, 150 .emit = upload_pipelined_state_pointers 151}; 152#endif 153 154static void upload_psp_urb_cbs(struct brw_context *brw ) 155{ 156 upload_pipelined_state_pointers(brw); 157 brw_upload_urb_fence(brw); 158 brw_upload_constant_buffer_state(brw); 159} 160 161 162const struct brw_tracked_state brw_psp_urb_cbs = { 163 .dirty = { 164 .mesa = 0, 165 .brw = BRW_NEW_URB_FENCE | BRW_NEW_METAOPS | BRW_NEW_BATCH, 166 .cache = (CACHE_NEW_VS_UNIT | 167 CACHE_NEW_GS_UNIT | 168 CACHE_NEW_GS_PROG | 169 CACHE_NEW_CLIP_UNIT | 170 CACHE_NEW_SF_UNIT | 171 CACHE_NEW_WM_UNIT | 172 CACHE_NEW_CC_UNIT) 173 }, 174 .emit = upload_psp_urb_cbs, 175}; 176 177/** 178 * Upload the depthbuffer offset and format. 179 * 180 * We have to do this per state validation as we need to emit the relocation 181 * in the batch buffer. 182 */ 183 184static int prepare_depthbuffer(struct brw_context *brw) 185{ 186 struct intel_region *region = brw->state.depth_region; 187 188 if (!region || !region->buffer) 189 return 0; 190 return dri_bufmgr_check_aperture_space(region->buffer); 191} 192 193static void emit_depthbuffer(struct brw_context *brw) 194{ 195 struct intel_context *intel = &brw->intel; 196 struct intel_region *region = brw->state.depth_region; 197 unsigned int len = (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) ? sizeof(struct brw_depthbuffer_gm45_g4x) / 4 : sizeof(struct brw_depthbuffer) / 4; 198 199 if (region == NULL) { 200 BEGIN_BATCH(len, IGNORE_CLIPRECTS); 201 OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); 202 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | 203 (BRW_SURFACE_NULL << 29)); 204 OUT_BATCH(0); 205 OUT_BATCH(0); 206 OUT_BATCH(0); 207 208 if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) 209 OUT_BATCH(0); 210 211 ADVANCE_BATCH(); 212 } else { 213 unsigned int format; 214 215 switch (region->cpp) { 216 case 2: 217 format = BRW_DEPTHFORMAT_D16_UNORM; 218 break; 219 case 4: 220 if (intel->depth_buffer_is_float) 221 format = BRW_DEPTHFORMAT_D32_FLOAT; 222 else 223 format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; 224 break; 225 default: 226 assert(0); 227 return; 228 } 229 230 BEGIN_BATCH(len, IGNORE_CLIPRECTS); 231 OUT_BATCH(CMD_DEPTH_BUFFER << 16 | (len - 2)); 232 OUT_BATCH(((region->pitch * region->cpp) - 1) | 233 (format << 18) | 234 (BRW_TILEWALK_YMAJOR << 26) | 235 ((region->tiling != I915_TILING_NONE) << 27) | 236 (BRW_SURFACE_2D << 29)); 237 OUT_RELOC(region->buffer, 238 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 239 0); 240 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) | 241 ((region->pitch - 1) << 6) | 242 ((region->height - 1) << 19)); 243 OUT_BATCH(0); 244 245 if (BRW_IS_GM45(brw) || BRW_IS_G4X(brw)) 246 OUT_BATCH(0); 247 248 ADVANCE_BATCH(); 249 } 250} 251 252const struct brw_tracked_state brw_depthbuffer = { 253 .dirty = { 254 .mesa = 0, 255 .brw = BRW_NEW_DEPTH_BUFFER | BRW_NEW_BATCH, 256 .cache = 0, 257 }, 258 .prepare = prepare_depthbuffer, 259 .emit = emit_depthbuffer, 260}; 261 262 263 264/*********************************************************************** 265 * Polygon stipple packet 266 */ 267 268static void upload_polygon_stipple(struct brw_context *brw) 269{ 270 struct brw_polygon_stipple bps; 271 GLuint i; 272 273 memset(&bps, 0, sizeof(bps)); 274 bps.header.opcode = CMD_POLY_STIPPLE_PATTERN; 275 bps.header.length = sizeof(bps)/4-2; 276 277 for (i = 0; i < 32; i++) 278 bps.stipple[i] = brw->attribs.PolygonStipple[31 - i]; /* invert */ 279 280 BRW_CACHED_BATCH_STRUCT(brw, &bps); 281} 282 283const struct brw_tracked_state brw_polygon_stipple = { 284 .dirty = { 285 .mesa = _NEW_POLYGONSTIPPLE, 286 .brw = 0, 287 .cache = 0 288 }, 289 .emit = upload_polygon_stipple 290}; 291 292 293/*********************************************************************** 294 * Polygon stipple offset packet 295 */ 296 297static void upload_polygon_stipple_offset(struct brw_context *brw) 298{ 299 __DRIdrawablePrivate *dPriv = brw->intel.driDrawable; 300 struct brw_polygon_stipple_offset bpso; 301 302 memset(&bpso, 0, sizeof(bpso)); 303 bpso.header.opcode = CMD_POLY_STIPPLE_OFFSET; 304 bpso.header.length = sizeof(bpso)/4-2; 305 306 bpso.bits0.x_offset = (32 - (dPriv->x & 31)) & 31; 307 bpso.bits0.y_offset = (32 - ((dPriv->y + dPriv->h) & 31)) & 31; 308 309 BRW_CACHED_BATCH_STRUCT(brw, &bpso); 310} 311 312#define _NEW_WINDOW_POS 0x40000000 313 314const struct brw_tracked_state brw_polygon_stipple_offset = { 315 .dirty = { 316 .mesa = _NEW_WINDOW_POS, 317 .brw = 0, 318 .cache = 0 319 }, 320 .emit = upload_polygon_stipple_offset 321}; 322 323/********************************************************************** 324 * AA Line parameters 325 */ 326static void upload_aa_line_parameters(struct brw_context *brw) 327{ 328 struct brw_aa_line_parameters balp; 329 330 if (!(BRW_IS_GM45(brw) || BRW_IS_G4X(brw))) 331 return; 332 333 /* use legacy aa line coverage computation */ 334 memset(&balp, 0, sizeof(balp)); 335 balp.header.opcode = CMD_AA_LINE_PARAMETERS; 336 balp.header.length = sizeof(balp) / 4 - 2; 337 338 BRW_CACHED_BATCH_STRUCT(brw, &balp); 339} 340 341const struct brw_tracked_state brw_aa_line_parameters = { 342 .dirty = { 343 .mesa = 0, 344 .brw = BRW_NEW_CONTEXT, 345 .cache = 0 346 }, 347 .emit = upload_aa_line_parameters 348}; 349 350/*********************************************************************** 351 * Line stipple packet 352 */ 353 354static void upload_line_stipple(struct brw_context *brw) 355{ 356 struct brw_line_stipple bls; 357 GLfloat tmp; 358 GLint tmpi; 359 360 memset(&bls, 0, sizeof(bls)); 361 bls.header.opcode = CMD_LINE_STIPPLE_PATTERN; 362 bls.header.length = sizeof(bls)/4 - 2; 363 364 bls.bits0.pattern = brw->attribs.Line->StipplePattern; 365 bls.bits1.repeat_count = brw->attribs.Line->StippleFactor; 366 367 tmp = 1.0 / (GLfloat) brw->attribs.Line->StippleFactor; 368 tmpi = tmp * (1<<13); 369 370 371 bls.bits1.inverse_repeat_count = tmpi; 372 373 BRW_CACHED_BATCH_STRUCT(brw, &bls); 374} 375 376const struct brw_tracked_state brw_line_stipple = { 377 .dirty = { 378 .mesa = _NEW_LINE, 379 .brw = 0, 380 .cache = 0 381 }, 382 .emit = upload_line_stipple 383}; 384 385 386/*********************************************************************** 387 * Misc invarient state packets 388 */ 389 390static void upload_invarient_state( struct brw_context *brw ) 391{ 392 { 393 /* 0x61040000 Pipeline Select */ 394 /* PipelineSelect : 0 */ 395 struct brw_pipeline_select ps; 396 397 memset(&ps, 0, sizeof(ps)); 398 ps.header.opcode = CMD_PIPELINE_SELECT(brw); 399 ps.header.pipeline_select = 0; 400 BRW_BATCH_STRUCT(brw, &ps); 401 } 402 403 { 404 struct brw_global_depth_offset_clamp gdo; 405 memset(&gdo, 0, sizeof(gdo)); 406 407 /* Disable depth offset clamping. 408 */ 409 gdo.header.opcode = CMD_GLOBAL_DEPTH_OFFSET_CLAMP; 410 gdo.header.length = sizeof(gdo)/4 - 2; 411 gdo.depth_offset_clamp = 0.0; 412 413 BRW_BATCH_STRUCT(brw, &gdo); 414 } 415 416 417 /* 0x61020000 State Instruction Pointer */ 418 { 419 struct brw_system_instruction_pointer sip; 420 memset(&sip, 0, sizeof(sip)); 421 422 sip.header.opcode = CMD_STATE_INSN_POINTER; 423 sip.header.length = 0; 424 sip.bits0.pad = 0; 425 sip.bits0.system_instruction_pointer = 0; 426 BRW_BATCH_STRUCT(brw, &sip); 427 } 428 429 430 { 431 struct brw_vf_statistics vfs; 432 memset(&vfs, 0, sizeof(vfs)); 433 434 vfs.opcode = CMD_VF_STATISTICS(brw); 435 if (INTEL_DEBUG & DEBUG_STATS) 436 vfs.statistics_enable = 1; 437 438 BRW_BATCH_STRUCT(brw, &vfs); 439 } 440} 441 442const struct brw_tracked_state brw_invarient_state = { 443 .dirty = { 444 .mesa = 0, 445 .brw = BRW_NEW_CONTEXT, 446 .cache = 0 447 }, 448 .emit = upload_invarient_state 449}; 450 451/** 452 * Define the base addresses which some state is referenced from. 453 * 454 * This allows us to avoid having to emit relocations in many places for 455 * cached state, and instead emit pointers inside of large, mostly-static 456 * state pools. This comes at the expense of memory, and more expensive cache 457 * misses. 458 */ 459static void upload_state_base_address( struct brw_context *brw ) 460{ 461 struct intel_context *intel = &brw->intel; 462 463 /* Output the structure (brw_state_base_address) directly to the 464 * batchbuffer, so we can emit relocations inline. 465 */ 466 BEGIN_BATCH(6, IGNORE_CLIPRECTS); 467 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2)); 468 OUT_BATCH(1); /* General state base address */ 469 OUT_BATCH(1); /* Surface state base address */ 470 OUT_BATCH(1); /* Indirect object base address */ 471 OUT_BATCH(1); /* General state upper bound */ 472 OUT_BATCH(1); /* Indirect object upper bound */ 473 ADVANCE_BATCH(); 474} 475 476const struct brw_tracked_state brw_state_base_address = { 477 .dirty = { 478 .mesa = 0, 479 .brw = BRW_NEW_CONTEXT, 480 .cache = 0, 481 }, 482 .emit = upload_state_base_address 483}; 484