| 5fe5aa8e55a8db0b80f6ff9838bad47ce0406fd0 |
|
19-Oct-2012 |
Ian Romanick <ian.d.romanick@intel.com> |
i965: Fix regression in depth texture rendering on pre-SNB
This was introduced by commit 24db6d6 (cherry-picked from a683012). The
original patch fixed potential GPU hangs on SNB, and it caused some
rendering regressions there. The benefits outweigh the costs.
However, the work-around is not necessary for pre-SNB chipsets.
Applying the work-around there gives rendering regressions with no
benefit. This patch disables the work-around on pre-SNB chipsets.
Without the original patch, the piglit test
depthstencil-render-miplevels would reliably hang an SNB GPU. On ILK
this test would not hang, and it does not hang with this patch.
NOTE: This is a candidate for the 8.0 and 9.0 branches
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 68da5dfc2c2e9c0aca47431076be0cd43406d4aa |
|
30-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.
This patch modifies intel_region_get_aligned_offset() to make the
appropriate calculation when the blorp engine sets up a W-tiled
stencil buffer using a Y-tiled SURFACE_STATE.
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit b760c9913dcff848a2aa0e60abeb48e596ae8fee)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 96fd94ba9421c7c3072988f999ee869534f2bc2a |
|
30-Aug-2012 |
Paul Berry <stereotype441@gmail.com> |
intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.
When the blorp engine is performing a blit from one stencil buffer to
another, it sets up the surface state for these buffers as Y-tiled, so
it needs to be able to force intel_region_get_tile_masks() to return
the appropriate masks for a Y-tiled region.
Acked-by: Eric Anholt <eric@anholt.net>
(cherry picked from commit 50dec7fc2d5ba813aaa822596d124098a22db301)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 68216f35814ab8d292f37b8c0fa0a5f181b7f20d |
|
18-May-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen6+: Add support for fast depth clears.
Improves citybench high-res performance 3.0% +- 0.4%, n=10. Improves
Lightsmark 1024x768 performance 0.74% +/- 0.20% (n=78). No
significant difference on openarena (n=5, didn't fast clear) or nexuiz
(n=3).
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 19e9b24626c2b9d7abef054d57bb2a52106c545b |
|
30-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/gen6: Initial implementation of MSAA.
This patch enables MSAA for Gen6, by modifying intel_mipmap_tree to
understand multisampled buffers, adapting the rendering pipeline setup
to enable multisampled rendering, and adding multisample resolve
operations to brw_blorp_blit.cpp. Some preparation work is also
included for Gen7, but it is not yet enabled.
MSAA support is still fairly preliminary. In particular, the
following are not yet supported:
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centroid interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
GL_SAMPLE_COVERAGE_INVERT).
Fixes piglit tests "EXT_framebuffer_multisample/accuracy" on
i965/Gen6.
v2:
- In intel_alloc_renderbuffer_storage(), quantize the requested number
of samples to the next higher sample count supported by the
hardware. This ensures that a query of GL_SAMPLES will return the
correct value. It also ensures that MSAA is fully disabled on Gen7
for now (since Gen7 MSAA support doesn't work yet).
- When reading from a non-MSAA surface, ensure that s_is_zero is true
so that we won't try to read from a nonexistent sample.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| a683012a80a3408b3b71f22b2a97d9eaaac11a46 |
|
26-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965/Gen6: Work around GPU hangs due to misaligned depth coordinate offsets.
In i965 Gen6, Mesa has for a long time used the "depth coordinate
offset X/Y" settings (in 3DSTATE_DEPTH_BUFFER) to cause the GPU to
render to miplevels other than 0. Unfortunately, this doesn't work,
because these offsets must be aligned to multiples of 8, and miplevels
in the depth buffer are only guaranteed to be aligned to multiples of
4. When the offsets aren't aligned to a multiple of 8, the GPU
sometimes hangs.
As a temporary measure, to avoid GPU hangs, this patch smashes the 3
LSB's of "depth coordinate offset X/Y" to 0. This results in
incorrect rendering to mipmapped depth textures, but that seems like a
reasonable stopgap while we figure out a better solution.
(Note that we have only ever observed this GPU hang on Gen6 when HiZ
is enabled, so another possible stopgap would be to disable HiZ).
Avoids GPU hangs in piglit test "depthstencil-render-miplevels" at
texture sizes that are not powers of 2.
Reviewed-by: Chad Verace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 3ec0e55b63db3c1067f3bbf4563beb3b98a19288 |
|
15-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Fix mipmap offsets for HiZ and separate stencil buffers.
When rendering to a miplevel other than 0 within a color, depth,
stencil, or HiZ buffer, we need to tell the GPU to render to an offset
within the buffer, so that the data is written into the correct
miplevel. We do this using a coarse offset (in pages), and a fine
adjustment (the so-called "tile_x" and "tile_y" values, which are
measured in pixels).
We have always computed the coarse offset and fine adjustment using
intel_renderbuffer_tile_offsets() function. This worked fine for
color and combined depth/stencil buffers, but failed to work properly
when HiZ and separate stencil were in use. It failed to work because
there is only one set of fine adjustment controls shared by the HiZ,
depth, and stencil buffers, so we need to choose tile_x and tile_y
values that are compatible with the tiling of all three buffers, and
then compute separate coarse offsets for each buffer.
This patch fixes the HiZ and separate stencil case by replacing the
call to intel_renderbuffer_tile_offsets() with calls to two functions:
intel_region_get_tile_masks(), which determines how much of the
adjustment can be performed using offsets and how much can be
performed using tile_x and tile_y, and
intel_region_get_aligned_offset(), which computes the coarse offset.
intel_region_get_tile_offsets() is still used for color renderbuffers,
so to avoid code duplication, I've re-worked it to use
intel_region_get_tile_masks() and intel_region_get_aligned_offset().
On i965 Gen6, fixes piglit tests
"texturing/depthstencil-render-miplevels 1024 X" where X is one of
(depth, depth_and_stencil, depth_stencil_single_binding, depth_x,
depth_x_and_stencil, stencil, stencil_and_depth, stencil_and_depth_x).
On i965 Gen7, the variants of
"texturing/depthstencil-render-miplevels" that contain a stencil
buffer still fail, due to another problem: Gen7 seems to ignore the 3
LSB's of the tile_y adjustment (and possibly also tile_x).
v2: Removed spurious comments. Added assertions to check
preconditions of intel_region_get_aligned_offset().
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 4433b0302d0aa9dc61002e8bb4fd1b752b0be338 |
|
20-Apr-2012 |
Brian Paul <brianp@vmware.com> |
intel: use _mesa_is_winsys/user_fbo() helpers
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| a27c7d80afc3160a0face4b8781bf921229bc3cc |
|
06-Apr-2012 |
Paul Berry <stereotype441@gmail.com> |
i965: Stop lying about cpp and height of a stencil buffer.
When using a separate stencil buffer, i965 requires that the pitch of
the buffer (in the 3DSTATE_STENCIL_BUFFER command) be specified as 2x
the actual pitch.
Previously this was accomplished by doubling the "cpp" and "pitch"
values stored in the intel_region data structure, and halving the
height. However, this was confusing, and it led to a subtle (but
benign) bug: since a stencil buffer is W-tiled, its true height must
be aligned to a multiple of 64; we were accidentally aligning its faux
height to a multiple of 64, causing memory to be wasted.
Note that for window system stencil buffers, the DDX also doubles the
cpp and pitch values. To facilitate fixing this DDX server bug in the
future, we fix the cpp and pitch values we receive from the X server
only if cpp has the "incorrect" value of 2.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
v2: Clarify comments about the DDX.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| b2ace06cbbbb1021e2d7ace12a985c6406821939 |
|
29-Feb-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix Gen6+ dynamic state upper bound on older kernels.
Kernels prior to 271d81b84171d84723357ae6d172ec16b0d8139c (March 2011)
don't support relocations outside of the target buffer object. Rather
than guarding this with a I915_PARAM_HAS_RELAXED_DELTA check, just
smash the bound to 0xfffff001 like we do on Ironlake.
This effectively gives us no upper bound check, just like we did prior
to commit 271d81b84171d84723357ae6d172ec16b0d8139c.
Daniel Vetter would also like to mention that this relies on the guard
page at the end of the GTT.
NOTE: This is a candidate for release branches.
Fixes a regression since 271d81b84171d84723357ae6d172ec16b0d8139c.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=46766
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 5a7942c2f1e3af4daedd92c1ddf21fa6a0e4e752 |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Rename the original binding table to mention that it's the WM now.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| f9c3ea32cd9b243050ee16f10d6eb9d9c8b3a8ea |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Split the gen6 GS binding table to a separate table.
Improves VS state change microbenchmark performance by 7.08729% +/-
1.22289% (n=10) on gen7, because we don't upload the 64 dwords of
unused binding table any more.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 07e00b3040d6da381595c65db5afe597f20d99fc |
|
15-Feb-2012 |
Eric Anholt <eric@anholt.net> |
i965: Split the VS binding table to a separate table.
This is a step toward making the samplers/binding tables reflect
sampler uniform mappings instead of embedding those in the programs.
No significant performance difference on the microbenchmark (n=10).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 3340b47c2280346ba2f44dde44466f09d898b9d8 |
|
09-Feb-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix border color on Ironlake.
Ironlake appears to check our pointer against the General State Base
Address upper bound, rather than ignoring the zero bound as it ought.
Unfortunately, since we leave GSBA set to zero, there is no logical
upper bound. Set it to the maximum possible value, which should work
since our virtual addresses only go up to 2GB.
+94 piglits.
NOTE: This is a candidate for stable release branches.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28924
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 9f8ed9d66298e2dc5dff508e3ea723469fe06d93 |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: derive intel_renderbuffer from swrast_renderbuffer
Drivers that rely on swrast need to do this, as with swrast_texture_image.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 924de7dc96f4607cb3d833637b5f69f4b9e2a6d0 |
|
16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: use intel_rb_format() to get renderbuffer format
This will make future changes cleaner and less invasive.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| c25e5300cba7628b58df93ead14ebc3cc32f338c |
|
20-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Fix border color on Sandybridge and Ivybridge.
While reading through the simulator, I found some interesting code that
looks like it checks the sampler default color pointer against the bound
set in STATE_BASE_ADDRESS. On failure, it appears to program it to the
base address itself.
So I decided to try programming a legitimate bound, and lo and behold,
border color worked.
+92 piglits on Sandybridge. Also fixes Lightsmark on Ivybridge.
NOTE: This is a candidate for stable release branches.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=28924
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38868
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| a6dd4bf5fcce2520ab199201fdd1ad155457d781 |
|
18-Jan-2012 |
Chad Versace <chad.versace@linux.intel.com> |
i965/gen5: Fix rendering of depth buffers without stencil [v2]
Fixes the following OGLConform tests on gen5:
depth-stencil(misc.state_on.depth_int)
fbo_db_ARBfp(basic.OnlyDepthBuffDrawBufferRender)
The problem was that, if the depth buffer's Mesa format was X8_Z24, then
we emitted the hardware format D24_UNORM_X8. But, on gen5, D24_UNORM_S8
must be emitted.
This bug was introduced by:
commit d84a180417d1eabd680554970f1eaaa93abcd41e
Author: Eric Anholt <eric@anholt.net>
i965: Base HW depth format setup based on MESA_FORMAT, not bpp.
v2: Deref 'intel' directly. Move the branch for newer chipset to top.
Quote the PRM. As requested by Ken.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=43408
Note: This is a candidate for the 8.0 branch.
Reported-by: Xunx Fang <xunx.fang@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| e6d6a10c5a2962f93d4adcd251b9a47a4e438121 |
|
12-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Fix depth buffer rendering to tile offsets.
Previously, we were saying that everything from the starting tile to
region width+height was part of the limits of our depthbuffer, even if
the tile was near the bottom of the depthbuffer. This mean that our
range was not clipping to buffer buonds if the start tile was anything
but the start of the buffer.
In bebc91f0f3a1f2d19d36a7f1a4f7c992ace064e9, this was changed to
saying that we're just rendering to a region of the size of the
renderbuffer. This is great -- we get a range that should actually
match what we want. However, the hardware's range checking occurs
after the X/Y offset addition, so we were clipping out rendering to
small depth mip levels when an X/Y offset was present. Just add
tile_x/y to the width in that case -- the WM won't produce negative
x/y values pre-offset, so we just need to get the left/bottom sides of
the region to cover our buffer.
Fixes the following Piglit regressions on gen7:
spec/ARB_depth_buffer_float/fbo-clear-formats
spec/ARB_depth_texture/fbo-clear-formats
spec/EXT_packed_depth_stencil/fbo-clear-formats
NOTE: This is a candidate for the 8.0 branch.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 254b24f19511014cdf4741b73d69349ac9e931a2 |
|
11-Jan-2012 |
Eric Anholt <eric@anholt.net> |
i965: Fix compiler warnings from hiz changes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| bebc91f0f3a1f2d19d36a7f1a4f7c992ace064e9 |
|
22-Dec-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965: Replace references to stencil region size with buffer size
It is unwise to use a stencil region's size to determine its
renderbuffer's size, because at region creation we fudge the width and
height to accomodate interleaved rows. (See the comment for MESA_FORMAT_S8
in intel_miptree_create()). Most users of stencil_region->{width,height}
should be converted to use stencil_rb->{Width,Height}.
We have already done the replacement in several locations. This patch
continues the replacement in {brw,gen7}_emit_depthbuffer(). To make those
functions look consistent, I've also done the equivalent replacement for
the depth buffer.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 6a26005c1e298ec205c339b1b53b3dff6e1fd03c |
|
08-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Correct misspellings of "invariant".
$ dict invarient
No definitions found for "invarient", perhaps you mean:
gcide: Invariant
wn: invariant
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 9df8662e28ff6b60e5296dc4583372e0771a3263 |
|
21-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Don't use BRW_DEPTHFORMAT_D24_UNORM_X8_UINT on Gen4.
X8 depth formats weren't supported until Ironlake (Gen 5).
Fixes GPU hangs introduced in d84a180417d1eabd680554970f1eaaa93abcd41e.
One example test case was "fbo-missing-attachment-blit from".
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 9308f298300beaa757194a0db8ed50924754c011 |
|
28-Nov-2011 |
Paul Berry <stereotype441@gmail.com> |
i965 gen6: Initial implementation of transform feedback.
This patch adds basic transform feedback capability for Gen6 hardware.
This consists of several related pieces of functionality:
(1) In gen6_sol.c, we set up binding table entries for use by
transform feedback. We use one binding table entry per transform
feedback varying (this allows us to avoid doing pointer arithmetic in
the shader, since we can set up the binding table entries with the
appropriate offsets and surface pitches to place each varying at the
correct address).
(2) In brw_context.c, we advertise the hardware capabilities, which
are as follows:
MAX_TRANSFORM_FEEDBACK_INTERLEAVED_COMPONENTS 64
MAX_TRANSFORM_FEEDBACK_SEPARATE_ATTRIBS 4
MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS 16
OpenGL 3.0 requires these values to be at least 64, 4, and 4,
respectively. The reason we advertise a larger value than required
for MAX_TRANSFORM_FEEDBACK_SEPARATE_COMPONENTS is that we have already
set aside 64 binding table entries, so we might as well make them all
available in both separate attribs and interleaved modes.
(3) We set aside a single SVBI ("streamed vertex buffer index") for
use by transform feedback. The hardware supports four independent
SVBI's, but we only need one, since vertices are added to all
transform feedback buffers at the same rate. Note: at the moment this
index is reset to 0 only when the driver is initialized. It needs to
be reset to 0 whenever BeginTransformFeedback() is called, and
otherwise preserved.
(4) In brw_gs_emit.c and brw_gs.c, we modify the geometry shader
program to output transform feedback data as a side effect.
(5) In gen6_gs_state.c, we configure the geometry shader stage to
handle the SVBI pointer correctly.
Note: ordering of vertices is not yet correct for triangle strips
(alternate triangles are improperly oriented). This will be addressed
in a future patch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 507e71e45a2e46c6e01423ab00948a72f435396c |
|
18-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for GL_ARB_depth_buffer_float under 3.0 override.
This is not exposed generally yet because some of the swrast paths hit
in piglit (drawpixels, copypixels, blit) aren't yet converted to
MapRenderbuffer.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 4790c4ae2489b8c72e6d98f3f80b5a9e7f799203 |
|
07-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add separate stencil/HiZ setup for MESA_FORMAT_Z32_FLOAT_X24S8.
This is a little more unusual than the separate MESA_FORMAT_S8_Z24
support, because in addition to storing the real stencil data in a
MESA_FORMAT_S8 miptree, we also make the Z miptree be
MESA_FORMAT_Z32_FLOAT instead of the requested format.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 0b8b6c7e974930daf12e97fb8f0b2a2cc29396d9 |
|
08-Dec-2011 |
Eric Anholt <eric@anholt.net> |
intel: Stop creating the wrapped stencil irb.
There were only two places it was really used at this point, which was
in the batchbuffer emit of the separate stencil packets for gen6/7.
Just write in the ->stencil_mt reference in those two places and ditch
all this flailing around with allocation and refcounts.
v2: Fix separate stencil on gen7.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| d464a21e2d796e396e7e4c0cfe971b41003e2d2a |
|
07-Dec-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Return BRW_DEPTHBUFFER_D32_FLOAT as the null-depthbuffer format.
Fixes many crashes on Ivybridge due to upload_sf_state calling
brw_depthbuffer_format without an actual depth buffer. This was a
recent regression on master.
+3992 piglits on Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| d84a180417d1eabd680554970f1eaaa93abcd41e |
|
17-Nov-2011 |
Eric Anholt <eric@anholt.net> |
i965: Base HW depth format setup based on MESA_FORMAT, not bpp.
This will make handling new formats (like actually exposing Z32F)
easier and more reliable.
v2: Remove the check for hiz buffer -- the MESA_FORMAT should really
be giving us the value we want even for hiz.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| f99d5af03b0f97d7a1b7076b2142069770879471 |
|
23-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
i965/gen6: Fix GPU hang when using stencil buffer without depth
Enable the bit 3DSTATE_DEPTH_BUFFER.Tiled_Surface. From the Sandybridge
PRM, Volume 2, Part 1, Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27
Tiled Surface:
[DevGT+]: This field must be set to TRUE.
Fixes GPU hangs on the following Piglit tests:
hiz-stencil-test-fbo-d0-s8
hiz-stencil-read-fbo-d0-s8
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| a2e44b0813e956440c451c107cf5564b56cbe98e |
|
17-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_mipmap_tree::hiz_region with a miptree [v2]
This is required to correctly implement HiZ for mipmapped and
multi-layered textures.
v2: Accomodate refcount fixes in intel_process_dri2_buffer_*() that were
introduced in v2 of commit
intel: Replace intel_renderbuffer::region with a miptree [v2]
Reviewed-by: Eric Anholt <eric@anholt>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| da2816a45e6e3a33246a341fee72e6f893f315d9 |
|
16-Nov-2011 |
Chad Versace <chad.versace@linux.intel.com> |
intel: Replace intel_renderbuffer::region with a miptree [v3]
Essentially, this patch just globally substitutes `irb->region` with
`irb->mt->region` and then does some minor cleanups to avoid segfaults
and other problems.
This is in preparation for
1. Fixing scatter/gather for mipmapped separate stencil textures.
2. Supporting HiZ for mipmapped depth textures.
As a nice benefit, this lays down some preliminary groundwork for easily
texturing from any renderbuffer, even those of the window system.
A future commit will replace intel_mipmap_tree::hiz_region with a miptree.
v2:
- Return early in intel_process_dri2_buffer_*() if region allocation
fails.
- Fix double semicolon.
- Fix miptree reference leaks in the following functions:
intel_process_dri2_buffer_with_separate_stencil()
intel_image_target_renderbuffer_storage()
v3:
- [anholt] Fix check for hiz allocation failure. Replace
``if (!irb->mt)` with ``if(!irb->mt->hiz_region)``.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| e7c29c5de82f6de3d30ed1143d9672dd2e25f0e7 |
|
31-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Use a single binding table for all pipeline stages.
Although the hardware supports separate binding tables for each pipeline
stage, we don't see much advantage over a single shared table.
Consider the contents of the binding table:
- Textures (16)
- Draw buffers (8)
- Pull constant buffers (1 for VS, 1 for WM)
OpenGL's texture bindings are global: the same set of textures is
available to all shader targets. So our binding table entries for
textures would be exactly the same in every table.
There are only two pull constant buffers (not many), and although draw
buffers aren't interesting to the VS, it shouldn't hurt to have them in
the table. The hardware supports up to 254 binding table entries, and
we currently only use 26.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| eaf4d3e6e2493a6e0b20d1205a5fb33ce500c9c2 |
|
22-Oct-2011 |
Eric Anholt <eric@anholt.net> |
i965: Remove the validated BO list, now that it's unused.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 8004a1cb95b8a195f3f4bbaa8d39d2f3297167de |
|
22-Sep-2011 |
Eric Anholt <eric@anholt.net> |
intel: Rename region->buffer to region->bo, and remove accessor function.
We call all the other drm_intel_bo pointers in intel/*.h "bo", so this
one was rather out of place.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 8bd27a5b080157cb1d5fc0383ce45574c7b16aa5 |
|
01-Sep-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit depth stalls and flushes before changing depth state on Gen6+.
Fixes OpenArena on Gen7. Technically, adding only the first depth stall
fixes it, but the documentation says to do all three, and the Windows
driver seems to do it.
Not observed to fix anything on Gen6 yet.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38863
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 7288d010e0afeade5357502fdc018fc4928330f6 |
|
19-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix polygon stipple offset state flagging.
_NEW_WINDOW_POS wasn't a real Mesa state flag, but we were missing
_NEW_BUFFERS to update the stipple offset when FBO binding or window
size changed, and _NEW_POLYGON to update when stippling gets enabled.
Fixes oglconform's tristrip test.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 4c9b09d3c2cc50b1dd46b9eb8a89d6086016484b |
|
19-Sep-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add missing _NEW_POLYGON flag to polygon stipple upload.
Because we skip the pattern upload when stippling is disabled, we need
to check again when it might have been turned on.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Yuanhan Liu <yuanhan.liu@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| fb5ff51f422e1718c09da01f3c5bb5baecc9d68e |
|
19-Jul-2011 |
Eric Anholt <eric@anholt.net> |
i965: Fix regression in 29a911c50e4443dfebef0a2e32c39b64992fa3cc.
The previous define was the full 32-bit header, while the new define
was just the top 16 bits.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 29a911c50e4443dfebef0a2e32c39b64992fa3cc |
|
13-Jul-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename 3DSTATE_DRAWRECT_INFO_I965 to 3DSTATE_DRAWING_RECTANGLE.
The documentation uses 3DSTATE_DRAWING_RECTANGLE, and we already had it
defined in brw_defines.h; we were simply using an old #define from
intel_reg.h.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 247e4c69ce6389805437256524d043019abfa6d1 |
|
30-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Convert system instruction pointer to OUT_BATCH style.
Also rename it from CMD_STATE_INSN_POINTER to CMD_STATE_SIP to match the
documentation.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 87de78523ae96737a39267aaa135ddabff05f2f2 |
|
30-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Convert PIPELINE_SELECT to OUT_BATCH style.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 473a519d20c97b54504ff61aaedc0665529c14b7 |
|
30-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit 3DSTATE_VF_STATISTICS in OUT_BATCH style.
This is a little different from most because it's a single DWord;
there's no length field.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| a68c5e6b71ac9abf70eb443637d4e79ffba66595 |
|
30-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Convert 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP to OUT_BATCH style.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| a09c5c2e3053c48a33134cf28229105bfef52e6f |
|
19-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965: Reissue PIPELINE_POINTERS and BINDING_TABLE_POINTERS on SBA change.
This was a requirement we didn't run into until we started using
STATE_BASE_ADDRESS for instruction data.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| babe1fc004b56202b2bd54d9689f5208dc4fd607 |
|
20-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Add a couple more packets to the nonpipelined workaround list.
All the packets chosen before came from grepping the pdf for
nonpipelined, and these two came from grepping for non.pipelined. We
could stand a review by looking at all packets emitted and identifying
what kind they are.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| f6e5230b2614cc91e4c849c07781b2230878d274 |
|
18-Jun-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Apply documented workaround for nonpipelined state packets.
Fixes a 100% reproducible GPU hang in topogun-1.06-orc-84k.trace.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| c173541d9769d41a85cc899bc49699a3587df4bf |
|
27-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965: Use state streaming on programs, and state base address on gen5+.
There will be a little bit of thrashing of the program cache BO as the
cache warms up, but once the application is in steady state, this
reduces relocations on gen5 and later.
On my T420 laptop, cairogl firefox-talos-gfx performance improves 2.6%
+/- 1.3% (n=6). No statistically significant performance difference
on nexuiz (n=5).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| d105f6684dfbfe596e57ddeb9377e7f9e4e57dcb |
|
09-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
i965/gen5,6: Fix hang when emitting hiz buffer without stencil buffer
When emitting either a hiz or stencil buffer, the 'separate stencil
enable' and 'hiz enable' bits are set in 3DSTATE_DEPTH_BUFFER. Therefore
we must emit both 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER.
Even if there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be
emitted; failure to do so causes a hang on gen5 and a stall on gen6.
This also fixes a silly, obvious segfault that occured when a hiz buffer
xor separate stencil buffer existed.
Fixes the piglit tests below on Gen5 when hiz and separate stencil are
manually enabled:
fbo-alphatest-nocolor
fbo-depth-sample-compare
fbo
hiz-depth-read-fbo-d24-s0
hiz-depth-stencil-test-fbo-d24-s0
hiz-depth-test-fbo-d24-s0
hiz-stencil-read-fbo-d0-s8
hiz-stencil-test-fbo-d0-s8
fbo-missing-attachment-clear
fbo-clear-formats
fbo-depth-*
Changes piglit test result from crash to fail:
hiz-depth-stencil-test-fbo-d0-s8
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| b17aab5753a6d14c9e757bedb186963b2dae8823 |
|
31-May-2011 |
Eric Anholt <eric@anholt.net> |
intel: Move the draw_x/draw_y to the renderbuffer where it belongs.
It was originally located in the region because the tracking of
depth/color buffers was on the regions, and getting back to the irb
would have been tricky. Now, we're keying off of the renderbuffer in
more places, which means we can move these fields where they belong.
This could fix potential rendering failure with a single texture
having multiple images attached to different renderbuffers across
shareCtx (as far as I can tell, this was the only failure we could
cause, since anything else should trigger intel_render_texture in
between, for example a BindFramebuffer).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 97d230b0bcf8ed001f685ebac314fbd8e1955718 |
|
10-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
i965/brw: Fix emit_depthbuffer() when packed depth/stencil texture is attached
If either depth or stencil buffer has packed depth/stencil format, then do
not use separate stencil.
Before this commit, emit_depthbuffer() incorrectly assumed that the
texture's stencil renderbuffer wrapper was a *separate* stencil buffer,
because the depth and stencil renderbuffer wrappers are distinct for
depth/stencil textures (that is, depth_irb != stencil_irb).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38134
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 2a638076165eaa1294708a7e4518c2d72560e066 |
|
06-Jun-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/gen7: Don't emit 3DSTATE_GS_SVB_INDEX on Ivybridge.
According to vol2a.07, it only applies from Cantiga to Sandybridge.
I found this in my ringbuffers while investigating various GPU hangs.
While it may not have been the cause, it seemed wise to remove it.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 2abc8cae87b4cd037ebde68b4b9a1d02254657df |
|
23-May-2011 |
Chad Versace <chad@chad-versace.us> |
i965/brw: Emit state for hiz and separate stencil buffers
When emitting 3DSTATE_DEPTH_BUFFER, also emit 3DSTATE_HIER_DEPTH_BUFFER if
there is a hiz buffer. Ditto for 3DSTATE_STENCIL_BUFFER and a separate
stencil buffer.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 3e43adef95ee24dd218279d2de56939b90edcb4c |
|
13-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Add support for rendering to depthbuffer mipmap levels > 0.
Fixes
GL_ARB_depth_texture/fbo-clear-formats
GL_EXT_packed_depth_stencil/fbo-clear-formats
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| a98dd64af750fb6dae54b2dc02e0c5a3711156af |
|
13-May-2011 |
Eric Anholt <eric@anholt.net> |
i965: Stop caching the combined depth/stencil region in brw_context.c.
This was going to get in the way of separate depth/stencil (which
wants to know about both, and whether they are the same rb), and also
wasn't a sufficient flag for the fix in the following commit.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| d58400eb4a2605640267436f63d9e856fb3c1f96 |
|
09-Apr-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Emit extra 0's in 3DSTATE_MULTISAMPLE on Ivybridge.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| e0e2c045965f7bd4becae3dce8394f8455184e0d |
|
22-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Split BRW_NEW_BINDING_TABLE dirty bit into one per stage.
Ivybridge can update each stage's binding table pointer independently,
so we want separate dirty bits. Previous generations can simply
subscribe to all three dirty bits and emit as usual.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| acb4d5cd96d91320b8e5edb727ff3a268f04587f |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move the GS state to state streaming.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 8ba0c025a4e0aba97ae596e2121416cf04c0c300 |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move clip state to state streaming
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 588cebce2d5b6afd24b72603d744d390481310dd |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move VS state to state streaming.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| a82a43e8d99e1715dd11c9c091b5ab734079b6a6 |
|
23-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Use the dynamic state base address to reduce relocations.
Now that all the dynamic state is streamed through the top of the
batchbuffer, we can cut out many of our relocations to that state by
using the base address.
Improves 3DMMES taiji performance 3.3% +/- 0.4% (n=15).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 855f56ca13c1003396a81da1a110357d624a2101 |
|
25-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen6: Move scissor state to state streaming.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 1a447749ed421db8eb6ba20012630785aef9bb12 |
|
23-Apr-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen4: Move WM state to state streaming.
The samplers are about to become streamed for gen6 performance, which
would cause this unit to blow out the state cache.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| d3cc3901ab67823af3aba08efc863daa22ed1408 |
|
07-Apr-2011 |
Chad Versace <chad.versace@intel.com> |
i965: Change assertion condition from implicit to explicit
... because grokking explicit assertions requires fewer neurons.
In brw_misc_state.c:emit_depthbuffer, change assertion condition
tiling != I915_TILING_X && tiling != I915_TILING_NONE
to
tiling == I915_TILING_Y
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 05173c61c7cb987d08681f182ac78a1a179e02a4 |
|
08-Apr-2011 |
Chad Versace <chad.versace@intel.com> |
i965: Document brw_context.state.depth_region
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad.versace@intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| b1be5bd205d3efcaf4012d2c9a12831da57fc7fb |
|
09-Mar-2011 |
Eric Anholt <eric@anholt.net> |
i965: Change the SF unit from state caching to state streaming.
This is a 28.1% +/- 1.4% (n=10) performance improvement for the
hacked-up-for-cache-misses scissor-many (n=10), and no statistically
significant wall-time performance difference for the
hacked-up-for-cache-hits version (n=9, first outlier in each removed
since IPS was warming up. User time increased by about 4.7%, but
kernel time decreased equivalently).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| aac120977d1ead319141d48d65c9bba626ec03b8 |
|
20-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Move repeat-instruction-suppression to batchbuffer core
Move the tracking of the last emitted instructions into the core
batchbuffer routines and take advantage of the shadow batch copy to
avoid extra memory allocations and copies.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 8d68a90e225d831a395ba788e425cb717eec1f9a |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
intel: use pwrite for batch
It's faster. Not only is the memcpy more efficiently performed in the
kernel (making up for the system call overhead), but by not using mmap
we remove the greater overhead of tracking the vma of every batch.
And it means we can read back from the batch buffer without incurring
the cost of a uncached read through the GTT.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 3f55683927278e57f3ef8a151d15f4cffdc060dc |
|
10-Feb-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: drop state_bo references to batch_bo
As we use state relocations and we know that all the state belongs to
the same bo, we can drop the multiple references to the same bo.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 71acbb54f49089b03d3498b6f88c1681d3f649ac |
|
09-Feb-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename a few more commands to match the documentation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 1feee7b1b39e54c279ffdc3c27f3911c04658430 |
|
10-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename more #defines to 3DSTATE rather than CMD or CMD_3D.
Again, this makes it match the documentation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| e31defc825ee94f1d1092e277954abad7097c552 |
|
04-Jan-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Rename various gen6 #defines to match the documentation.
This should make it easier to cross-reference the code and hardware
documentation, as well as clear up any confusion on whether constants
like CMD_3D_WM_STATE mean WM_STATE (pre-gen6) or 3DSTATE_WM (gen6+).
This does not rename any pre-gen6 defines.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 59fa8600d8efa803a4f86a41beaca78f7be41d7c |
|
28-Dec-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
Revert "i965: upload multisample state for fragment program change"
This reverts commit de6fd527a545f8344e074312544517d05573fb72.
Revert this workaround as it seems the real trouble is caused by
lineloop, which doesn't require GS convert on sandybridge actually.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| de6fd527a545f8344e074312544517d05573fb72 |
|
23-Dec-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: upload multisample state for fragment program change
This makes conformance tests stable on sandybridge D0 to track
multisample state before SF/WM state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 8a7cf99457f5061c3c5aae48f14fb23b2ca07503 |
|
19-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't upload line smooth params unless we're line smoothing.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 008fd3779bc7adf603b27f49f4c90b21cee814e0 |
|
19-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't upload line stipple pattern unless we're stippling.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| e29e3c32d9d52fc206ab3ccc8674683adc880e82 |
|
19-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Don't upload polygon stipple unless required.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 7720bfffa3fd537789b5ded30ecc23afa21dc410 |
|
19-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move gen4 blend constant color to the gen4 blending file.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 2595589f1df351895bc5b1a92f19e995a19da15b |
|
19-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove the gen6 emit_mi_flushes I sprinkled around the driver.
These were for debugging in bringup. Now that relatively complicated
apps are working, they haven't helped debug anything in quite a while.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| f9995b30756140724f41daf963fa06167912be7f |
|
12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| d4da253b298677c63def5f2f774608d660be31a1 |
|
29-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
Revert "i965: Always set tiling for depth buffer on sandybridge"
This reverts commit 0a1910c26760762eb8d67f68dfd87494ab479e38.
oops, shouldn't apply tiling depth buffer for other chips as well.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 0a1910c26760762eb8d67f68dfd87494ab479e38 |
|
29-Sep-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: Always set tiling for depth buffer on sandybridge
Sandybridge only support tiling depth buffer, always set tiling bit.
Fix 'fbo_firecube' demo.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 24ff42e7d56ac489caeca6b5ffcc3091cc8194b5 |
|
31-Aug-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
i965: fix depth test on sandybridge
This includes several corrections for fixing depth test on sandybridge.
Fix wrong bits definition in depth stencil state. Fix wrong order of
state buffer offset in 3DSTATE_CC_STATE_POINTERS command. Correctly use
buffer width parameter in depth buffer setting.
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 527a9a4de218cae89d7faf92788f88ce1f9387b6 |
|
22-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use intel->gen >= 6 instead of IS_GEN6.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 7ad26b0030f6b14e6ec069eafdec6faf75e8007c |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Stream out CC unit state.
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 31.791 32.287 1.11% 6/6
after:
[ 0] gl firefox-talos-gfx 31.198 31.675 0.96% 6/6
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 27bc2de5461c1d66c8e005b35de77e7b9e214754 |
|
11-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Use the state base address to avoid relocations.
This makes the binding table code simpler, and is required for gen6,
which requires binding table addresses to be under 64k offset from the
surface state base addr.
No significant change in performance on firefox-talos-gfx.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 73de09f265cb1c66d70fd9eb92021882bfbbbef6 |
|
07-Jun-2010 |
Eric Anholt <eric@anholt.net> |
i965: Convert the binding table to streamed indirect state.
This slightly reduces reduces cairo-gl firefox-talos-gfx runtime on my
Ironlake:
before:
[ # ] backend test min(s) median(s) stddev. count
[ 0] gl firefox-talos-gfx 38.236 38.383 0.43% 5/6
after:
[ 0] gl firefox-talos-gfx 37.799 38.203 0.39% 6/6
It turns out the cost of caching these objects and looking them up in
the cache again is greater than the cost of just computing the object
again, particularly when the overhead of having a separate BO to pin
is removed.
(Those that are paying close attention will note that this is a
reversal of the path I was moving the driver in a couple of years ago.
The major thing that has changed is that back then all state was
recomputed when we wrapped the streaming state buffer, including
recompiling our precious programs. Now, we're uncaching just the
objects that are cheap to compute, and retaining caching of expensive
objects)
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| ddb10c3e603ee03e1287a992d23a5507779b7ffd |
|
24-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move Gen6 debugging emit_mi_flush into the Gen6 block.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 6e2330daa6d7872405485ffabfe613a7c053d890 |
|
24-May-2010 |
Eric Anholt <eric@anholt.net> |
i965: Emit MI_FLUSH before PSP on Ironlake for clip max threads errata.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| cdcef6cbf4dd80047819e9098e34a3b98bd502a4 |
|
19-Apr-2010 |
Zhenyu Wang <zhenyuw@linux.intel.com> |
intel: Clean up chipset name and gen num for Ironlake
Rename old IGDNG to Ironlake, and set 'gen' number for
Ironlake as 5, so tracking the features with generation num
instead of special is_ironlake flag.
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| f69d46150c308285a518391db02cc9cba0f2a12d |
|
01-Feb-2010 |
Eric Anholt <eric@anholt.net> |
i965: Add a couple SNB state packets I saw in other batchbuffer dumps.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 737fac7ba220e4a2d66a8e2100ae0af620c274df |
|
21-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Hook up remaining Sandybridge state packets besides WM.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| a38096aa94ef62dba73792f1680098059b697662 |
|
14-Dec-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set the state base address on Sandybridge.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 9dce60f35b25f4f5605b22d75447bac5d9f55515 |
|
03-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set up sandybridge binding table pointers but don't enable it yet.
It hangs the GPU at the clipper stage, presumably because we're lacking
other setup.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 719f2b1d8570aa58b970bd28941221ee6c34af9b |
|
03-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Set up sandybridge depthbuffer.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| a3d8e7e48152d88217a409bf366e10497ee75763 |
|
27-Jan-2010 |
Eric Anholt <eric@anholt.net> |
i965: Remove DRI1 leftovers from stipple offset handling.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 2861d9200be15cc44e8825387d3bd79086523c67 |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop more cliprect bookkeeping
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 5203b7227ccb6b618fa42f08434d4a3cf123dca2 |
|
02-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Drop batchbuffer cliprect_mode tracking
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| d61f07318c8678901b948fdaa8ccdf37aa3203e9 |
|
01-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Remove leftover __DRI{screen,drawable,context}Private references
As part of the DRI driver interface rewrite I merged __DRIscreenPrivate
and __DRIscreen, and likewise for __DRIdrawablePrivate and
__DRIcontextPrivate. I left typedefs in place though, to avoid renaming
all the *Private use internal to the driver. That was probably a
mistake, and it turns out a one-line find+sed combo can do the mass
rename. Better late than never.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| cb3810dd19760797e699c47929f655b829c4d339 |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_965 checks with context structure usage.
Saves another 600 bytes or so of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 0b87f143c466f7e5bd730895ee29f1cd20a68f9b |
|
17-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_G4X() across the driver with context structure usage.
Saves ~2KB of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 1c96e85c9d6b8c636b0636f3320d1057ab5357b3 |
|
16-Dec-2009 |
Eric Anholt <eric@anholt.net> |
intel: Replace IS_IGDNG checks with intel->is_ironlake or needs_ff_sync.
Saves ~480 bytes of code.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 99077e77927ec26edf85bfef81a6d433171c3a1e |
|
13-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: Flag BRW_NEW_CONTEXT on some context state.
Fixing this is a prereq for avoiding flagging all state at new
batch time. Eliminating that still causes problems, though (notably
glean logicOp fails on my GM965).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| f5539b6991e336aa1cf302dbdb1a29b3e85cff36 |
|
20-Aug-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: validate sf state
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 2995bf0d68f1b28ba68b81e9dc79e3ab52bc2795 |
|
13-Jul-2009 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: add support for new chipsets
1. new PCI ids
2. fix some 3D commands on new chipset
3. fix send instruction on new chipset
4. new VUE vertex header
5. ff_sync message (added by Zou Nan Hai <nanhai.zou@intel.com>)
6. the offset in JMPI is in unit of 64bits on new chipset
7. new cube map layout
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| e0a4e25f938953201fef2bf702e2e709451200f4 |
|
23-Jun-2009 |
Eric Anholt <eric@anholt.net> |
i965: Fix packed depth/stencil textures to be Y-tiled as well.
Fixes shadowtex.c. And an assert is added to catch this sooner next time.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 9490d86808300e5819941a40784e272c290e05ee |
|
05-May-2009 |
Eric Anholt <eric@anholt.net> |
i965: Disentangle VS constant surface state from WM surface state.
Also, only create VS surface state if there's a VS constant buffer to be
uploaded, and set the contents of the buffer at the same time as creation.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| cafea7528052624c8d3e4cd1c5b26a61bf04d1d0 |
|
14-Apr-2009 |
Brian Paul <brianp@vmware.com> |
i965: checkpoint commit: VS constant buffers
Hook up a constant buffer, binding table, etc for the VS unit.
This will allow using large constant buffers with vertex shaders.
The new code is disabled at this time (use_const_buffer=FALSE).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 29309b45b011b4c44721b8f7346272fb22a4d4c2 |
|
12-Mar-2009 |
Robert Ellison <papillo@vmware.com> |
i965: fix polygon stipple when rendering to FBO
The polygon stipple pattern, like the viewport and the
polygon face orientation, must be inverted on the i965
when rendering to a FBO (which itself has an inverted pixel
coordinate system compared to raw Mesa).
In addition, the polygon stipple offset, which orients
the stipple to the window system, disappears when rendering
to an FBO (because the window system offset doesn't apply,
and there's no associated FBO offset).
With these fixes, the conform triangle and polygon stipple
tests pass when rendering to texture.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| d0415a5a01c1a8c2c2a389d977401a7f6cee031b |
|
25-Feb-2009 |
Eric Anholt <eric@anholt.net> |
i965: Rename CMD_CONST_BUFFER_STATE to the CS_URB_STATE used in the docs.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 052c1d66a1ab1f2665870dc77dab28d20416cdf1 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Remove brw->attribs now that we can just always look in the GLcontext.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 14321fcfde9e30d0b9f15aab3c9a057271ae6295 |
|
30-Jan-2009 |
Eric Anholt <eric@anholt.net> |
i965: Delete old metaops code now that there are no remaining consumers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 34b1776e8d965605d12807884c9c447214d57281 |
|
02-Nov-2008 |
Eric Anholt <eric@anholt.net> |
i965: Merge GM45 into the G4X chipset define.
The mobile and desktop chipsets are the same, and having them separate is
more typing and more chances to screw up.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 59b2c2adbbece27ccf54e58b598ea29cb3a5aa85 |
|
24-Oct-2008 |
Eric Anholt <eric@anholt.net> |
i965: Fix check_aperture calls to cover everything needed for the prim at once.
Previously, since my check_aperture API change, we would check each piece of
state against the batchbuffer individually, but not all the state against the
batchbuffer at once. In addition to not being terribly useful in assuring
success, it probably also increased CPU load by calling check_aperture many
times per primitive.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 0cade4de4f74f6b0e86fb6622e2fc370c73fd840 |
|
20-Oct-2008 |
Eric Anholt <eric@anholt.net> |
intel: Don't keep intel->pClipRects, and instead just calculate it when needed.
This avoids issues with dereferencing stale cliprects around intel_draw_buffer
time. Additionally, take advantage of cliprects staying constant for FBOs and
DRI2, and emit cliprects in the batchbuffer instead of having to flush batch
each time they change.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| ec8076264ea2390d4cb749be5c88bbf2bf5d4847 |
|
24-Oct-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: don't emit state when dri_bufmgr_check_aperture_space fails.
This ensures there is an unfilled batchbuffer used for emitting states again. Partial fix for #17964.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| d2796939f18815935c8fe1effb01fa9765d6c7d8 |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Update to new check_aperture API for classic mode.
To do this, I had to clean up some of 965 state upload stuff. We may end
up over-emitting state in the aperture overflow case, but that should be rare,
and I'd rather have the simplification of state management.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 527e1cf172cb0a4d1f2891a351498669be1620cd |
|
08-Aug-2008 |
Eric Anholt <eric@anholt.net> |
965: cleanups to state emission from aperture checking and state ordering.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 1e645b365900cf1c71ca5594bd6b549a1f203040 |
|
26-Jul-2008 |
Ian Romanick <ian.d.romanick@intel.com> |
Merge branch 'master' into drm-gem
Conflicts:
src/mesa/drivers/dri/common/dri_bufmgr.c
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
|
| 2e841880cfc1006a2818d4a8bfefd21136dc39a9 |
|
11-Jul-2008 |
Eric Anholt <eric@anholt.net> |
drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 92c075eeb7c330ea420400d1c2bae57356b19f03 |
|
08-Jul-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: official name for GM45 chipset
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| 407ce3da3c53c9ebba0fbf827d7b0f610122d44b |
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11-Jun-2008 |
Eric Anholt <eric@anholt.net> |
[intel-gem] Chase domain flag renaming in the DRM.
This is an API breakage only.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| ead798eb103e4cfe801704bc15eb4fe8df078fa8 |
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07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Remove already-disabled PIPE_CONTROL command.
This existed to get the icache flushed. However, GEM handles this for us
now for sure, and we had disabled it prematurely anyway.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| ab50ddaa9173ae108833db0edb209045788efc41 |
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07-May-2008 |
Eric Anholt <eric@anholt.net> |
GEM: Make dri_emit_reloc take GEM domain flags instead of TTM flags.
The GEM flags are much more descriptive for what we need. Since this makes
bufmgr_fake rather device-specific, move it to the intel common directory.
We've wanted to do device-specific stuff to it before.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| 27e06a52342b94b4fb1d60a57c3bdaa2b30607cf |
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18-Apr-2008 |
Dave Airlie <airlied@panoply-rh.(none)> |
i965: fixup depth buffer check
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| 008653ac55776d6b1c6d1627ad20937aa1c4dbda |
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17-Apr-2008 |
Dave Airlie <airlied@redhat.com> |
i965: initial attempt at fixing the aperture overflow
Makes state emission into a 2 phase, prepare sets things up and accounts
the size of all referenced buffer objects. The emit stage then actually
does the batchbuffer touching for emitting the objects.
There is an assert in dri_emit_reloc if a reloc occurs for a buffer
that hasn't been accounted yet.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| c99fa92ff84e927c82e1231d96921fda9a2b0852 |
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22-Feb-2008 |
Kristian Høgsberg <krh@redhat.com> |
Merge {i915,i965}/intel_context.h as intel/intel_context.h
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| 70908a793b7755c973fe024844185ff9e14924ea |
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07-Feb-2008 |
Eric Anholt <eric@anholt.net> |
[965] Flush icache on new batch, not just new context.
This is required since our buffer manager may now move our
instruction-containing buffers at any batchbuffer emit.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| 8e444fb9e2685e3eac42beb848b08e91dc20c88a |
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29-Jan-2008 |
Xiang, Haihao <haihao.xiang@intel.com> |
i965: new integrated graphics chipset support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| a04b632350e5d0e9994fc667afc59407a39da0ba |
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10-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[intel] Add more cliprect modes to cover other meanings for batch emits.
The previous change gave us only two modes, one which looped over the batch
per cliprect (3d drawing) and one that didn't (state updeast).
However, we really want 4:
- Batch doesn't care about cliprects (state updates)
- Batch needs DRAWING_RECTANGLE looping per cliprect (3d drawing)
- Batch needs to be executed just once (region fills, copies, etc.)
- Batch already includes cliprect handling, and must be flushed by unlock time
(copybuffers, clears).
All callers should now be fixed to use one of these states for any batchbuffer
emits. Thanks to Keith Whitwell for pointing out the failure.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| dc1608ae9d90a490ce32aa005488e3591a6d8369 |
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09-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Replace the always_update dirty flag with BRW_NEW_BATCH.
This allows us to avoid re-emitting some state when validate_state happens
multiple times per batchbuffer. Even though we flush batch per primitive
currently, that may still happen already if the primitive changed (this should
probably be fixed as well).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| d9edd8e90588417e3d549f25132dab2f21445792 |
|
09-Jan-2008 |
Eric Anholt <eric@anholt.net> |
[965] Remove drawing rect upload, which is handled (better) by the kernel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| bea6b5fe5aa3138cec8d057766ae48da4aa57dee |
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20-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Enable EXT_framebuffer_object.
To do so, merge the remainnig necessary code from the buffers, blit, span, and
screen code to shared, and replace it with those.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| 146030aad2c41eb8303935a13333c93fdc7c4a58 |
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18-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Allow draw or depth regions to be NULL.
With FBOs, we end up wanting to do 3D metaops against one or the other without
having to find the other one to fill in if we're not going to draw to it.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| 38bad7677e57d629eeffd4ef39a7fc254db12735 |
|
14-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Replace the state cache suballocator with direct dri_bufmgr use.
The user-space suballocator that was used avoided relocation computations by
using the general and surface state base registers and allocating those types
of buffers out of pools built on top of single buffer objects. It also
avoided calls into the buffer manager for these small state allocations, since
only one buffer object was being used.
However, the buffer allocation cost appears to be low, and with relocation
caching, computing relocations for buffers is essentially free. Additionally,
implementing the suballocator required a don't-fence-subdata flag to disable
waiting on buffer maps so that writing new data didn't block on rendering using
old data, and careful handling when mapping to update old data (which we need
to do for unavoidable relocations with FBOs). More importantly, when the
suballocator filled, it had no replacement algorithm and just threw out all
of the contents and forced them to be recomputed, which is a significant cost.
This is the first step, which just changes the buffer type, but doesn't yet
improve the hash table to not result in full recompute on overflow. Because
the buffers are all allocated out of the general buffer allocator, we can
no longer use the general/surface state bases to avoid relocations, and they
are set to 0 instead.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| e3a6e60040b7f6ea7965e52f8f9881ed31e0347c |
|
08-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[965] Convert the driver to dri_bufmgr interface and enable TTM.
This is currently believed to work but be a significant performance loss.
Performance recovery should be soon to follow.
The dri_bo_fake_disable_backing_store() call was added to allow backing store
disable like bufmgr_fake.c did, which is a significant performance win (though
it's missing the no-fence-subdata part).
This commit is a squash merge of the 965-ttm branch, which had some history
I wanted to avoid pulling due to noisiness and brokenness at many points
for git-bisecting.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| f79360858d4c94629ef543a35e4e44a13419ac0e |
|
08-Dec-2006 |
Xiang, Haihao <haihao.xiang@intel.com> |
fix bug#9237
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|
| 759facb4d87843f6368fad9c5f20a5b1b3d95055 |
|
23-Oct-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Emit cliprects in the userspace driver as required, rather than
passing them to the kernel. This works because all drawing commands
in the 965 driver are emitted with the lock held and the batchbuffer
is always flushed prior to releasing the lock. This allows multiple
cliprects to be dealt with, without replaying entire batchbuffers and
redundantly re-emitting state.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| 133f14168009393c5f396d218521625cb79b653f |
|
07-Sep-2006 |
Keith Whitwell <keith@tungstengraphics.com> |
Make sure bmBufferOffset is called for all active buffers every time
we render. Currenly requires that some state be re-examined after
every LOCK_HARDWARE().
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
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| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_misc_state.c
|