brw_misc_state.c revision 2abc8cae87b4cd037ebde68b4b9a1d02254657df
1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33 34#include "intel_batchbuffer.h" 35#include "intel_fbo.h" 36#include "intel_regions.h" 37 38#include "brw_context.h" 39#include "brw_state.h" 40#include "brw_defines.h" 41 42/* Constant single cliprect for framebuffer object or DRI2 drawing */ 43static void upload_drawing_rect(struct brw_context *brw) 44{ 45 struct intel_context *intel = &brw->intel; 46 struct gl_context *ctx = &intel->ctx; 47 48 BEGIN_BATCH(4); 49 OUT_BATCH(_3DSTATE_DRAWRECT_INFO_I965); 50 OUT_BATCH(0); /* xmin, ymin */ 51 OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) | 52 ((ctx->DrawBuffer->Height - 1) << 16)); 53 OUT_BATCH(0); 54 ADVANCE_BATCH(); 55} 56 57const struct brw_tracked_state brw_drawing_rect = { 58 .dirty = { 59 .mesa = _NEW_BUFFERS, 60 .brw = BRW_NEW_CONTEXT, 61 .cache = 0 62 }, 63 .emit = upload_drawing_rect 64}; 65 66/** 67 * Upload the binding table pointers, which point each stage's array of surface 68 * state pointers. 69 * 70 * The binding table pointers are relative to the surface state base address, 71 * which points at the batchbuffer containing the streamed batch state. 72 */ 73static void upload_binding_table_pointers(struct brw_context *brw) 74{ 75 struct intel_context *intel = &brw->intel; 76 77 BEGIN_BATCH(6); 78 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2)); 79 OUT_BATCH(brw->vs.bind_bo_offset); 80 OUT_BATCH(0); /* gs */ 81 OUT_BATCH(0); /* clip */ 82 OUT_BATCH(0); /* sf */ 83 OUT_BATCH(brw->wm.bind_bo_offset); 84 ADVANCE_BATCH(); 85} 86 87const struct brw_tracked_state brw_binding_table_pointers = { 88 .dirty = { 89 .mesa = 0, 90 .brw = BRW_NEW_BATCH 91 | BRW_NEW_VS_BINDING_TABLE 92 | BRW_NEW_GS_BINDING_TABLE 93 | BRW_NEW_PS_BINDING_TABLE, 94 .cache = 0, 95 }, 96 .emit = upload_binding_table_pointers, 97}; 98 99/** 100 * Upload the binding table pointers, which point each stage's array of surface 101 * state pointers. 102 * 103 * The binding table pointers are relative to the surface state base address, 104 * which points at the batchbuffer containing the streamed batch state. 105 */ 106static void upload_gen6_binding_table_pointers(struct brw_context *brw) 107{ 108 struct intel_context *intel = &brw->intel; 109 110 BEGIN_BATCH(4); 111 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | 112 GEN6_BINDING_TABLE_MODIFY_VS | 113 GEN6_BINDING_TABLE_MODIFY_GS | 114 GEN6_BINDING_TABLE_MODIFY_PS | 115 (4 - 2)); 116 OUT_BATCH(brw->vs.bind_bo_offset); /* vs */ 117 OUT_BATCH(0); /* gs */ 118 OUT_BATCH(brw->wm.bind_bo_offset); /* wm/ps */ 119 ADVANCE_BATCH(); 120} 121 122const struct brw_tracked_state gen6_binding_table_pointers = { 123 .dirty = { 124 .mesa = 0, 125 .brw = BRW_NEW_BATCH 126 | BRW_NEW_VS_BINDING_TABLE 127 | BRW_NEW_GS_BINDING_TABLE 128 | BRW_NEW_PS_BINDING_TABLE, 129 .cache = 0, 130 }, 131 .emit = upload_gen6_binding_table_pointers, 132}; 133 134/** 135 * Upload pointers to the per-stage state. 136 * 137 * The state pointers in this packet are all relative to the general state 138 * base address set by CMD_STATE_BASE_ADDRESS, which is 0. 139 */ 140static void upload_pipelined_state_pointers(struct brw_context *brw ) 141{ 142 struct intel_context *intel = &brw->intel; 143 144 if (intel->gen == 5) { 145 /* Need to flush before changing clip max threads for errata. */ 146 BEGIN_BATCH(1); 147 OUT_BATCH(MI_FLUSH); 148 ADVANCE_BATCH(); 149 } 150 151 BEGIN_BATCH(7); 152 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2)); 153 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 154 brw->vs.state_offset); 155 if (brw->gs.prog_active) 156 OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 157 brw->gs.state_offset | 1); 158 else 159 OUT_BATCH(0); 160 OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 161 brw->clip.state_offset | 1); 162 OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 163 brw->sf.state_offset); 164 OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 165 brw->wm.state_offset); 166 OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 167 brw->cc.state_offset); 168 ADVANCE_BATCH(); 169 170 brw->state.dirty.brw |= BRW_NEW_PSP; 171} 172 173static void upload_psp_urb_cbs(struct brw_context *brw ) 174{ 175 upload_pipelined_state_pointers(brw); 176 brw_upload_urb_fence(brw); 177 brw_upload_cs_urb_state(brw); 178} 179 180const struct brw_tracked_state brw_psp_urb_cbs = { 181 .dirty = { 182 .mesa = 0, 183 .brw = BRW_NEW_URB_FENCE | BRW_NEW_BATCH, 184 .cache = (CACHE_NEW_VS_UNIT | 185 CACHE_NEW_GS_UNIT | 186 CACHE_NEW_GS_PROG | 187 CACHE_NEW_CLIP_UNIT | 188 CACHE_NEW_SF_UNIT | 189 CACHE_NEW_WM_UNIT | 190 CACHE_NEW_CC_UNIT) 191 }, 192 .emit = upload_psp_urb_cbs, 193}; 194 195static void prepare_depthbuffer(struct brw_context *brw) 196{ 197 struct intel_context *intel = &brw->intel; 198 struct gl_context *ctx = &intel->ctx; 199 struct gl_framebuffer *fb = ctx->DrawBuffer; 200 struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH); 201 struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL); 202 203 if (drb) 204 brw_add_validated_bo(brw, drb->region->buffer); 205 if (drb && drb->hiz_region) 206 brw_add_validated_bo(brw, drb->hiz_region->buffer); 207 if (srb) 208 brw_add_validated_bo(brw, srb->region->buffer); 209} 210 211static void emit_depthbuffer(struct brw_context *brw) 212{ 213 struct intel_context *intel = &brw->intel; 214 struct gl_context *ctx = &intel->ctx; 215 struct gl_framebuffer *fb = ctx->DrawBuffer; 216 /* _NEW_BUFFERS */ 217 struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); 218 struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL); 219 struct intel_region *hiz_region = depth_irb ? depth_irb->hiz_region : NULL; 220 unsigned int len; 221 222 /* 223 * If depth and stencil buffers are identical, then don't use separate 224 * stencil. 225 */ 226 if (depth_irb && depth_irb == stencil_irb) { 227 stencil_irb = NULL; 228 } 229 230 /* 231 * If stencil buffer uses combined depth/stencil format, but no depth buffer 232 * is attached, then use stencil buffer as depth buffer. 233 */ 234 if (!depth_irb && stencil_irb 235 && stencil_irb->Base.Format == MESA_FORMAT_S8_Z24) { 236 depth_irb = stencil_irb; 237 stencil_irb = NULL; 238 } 239 240 if (intel->gen >= 6) 241 len = 7; 242 else if (intel->is_g4x || intel->gen == 5) 243 len = 6; 244 else 245 len = 5; 246 247 if (!depth_irb && !stencil_irb) { 248 BEGIN_BATCH(len); 249 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); 250 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | 251 (BRW_SURFACE_NULL << 29)); 252 OUT_BATCH(0); 253 OUT_BATCH(0); 254 OUT_BATCH(0); 255 256 if (intel->is_g4x || intel->gen >= 5) 257 OUT_BATCH(0); 258 259 if (intel->gen >= 6) 260 OUT_BATCH(0); 261 262 ADVANCE_BATCH(); 263 264 } else if (!depth_irb && stencil_irb) { 265 /* 266 * There exists a separate stencil buffer but no depth buffer. 267 * 268 * The stencil buffer inherits most of its fields from 269 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and 270 * height. 271 * 272 * Since the stencil buffer has quirky pitch requirements, its region 273 * was allocated with half height and double cpp. So we need 274 * a multiplier of 2 to obtain the surface's real height. 275 * 276 * Enable the hiz bit because it and the separate stencil bit must have 277 * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit 278 * 1.21 "Separate Stencil Enable": 279 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer 280 * Enable must also be enabled. 281 * 282 * [DevGT]: This field must be set to the same value (enabled or 283 * disabled) as Hierarchical Depth Buffer Enable 284 */ 285 assert(intel->has_separate_stencil); 286 assert(stencil_irb->Base.Format == MESA_FORMAT_S8); 287 288 BEGIN_BATCH(len); 289 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); 290 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | 291 (1 << 21) | /* separate stencil enable */ 292 (1 << 22) | /* hiz enable */ 293 (BRW_TILEWALK_YMAJOR << 26) | 294 (BRW_SURFACE_2D << 29)); 295 OUT_BATCH(0); 296 OUT_BATCH(((stencil_irb->region->width - 1) << 6) | 297 (2 * stencil_irb->region->height - 1) << 19); 298 OUT_BATCH(0); 299 OUT_BATCH(0); 300 301 if (intel->gen >= 6) 302 OUT_BATCH(0); 303 304 ADVANCE_BATCH(); 305 306 } else { 307 struct intel_region *region = depth_irb->region; 308 unsigned int format; 309 uint32_t tile_x, tile_y, offset; 310 311 /* If using separate stencil, hiz must be enabled. */ 312 assert(!stencil_irb || hiz_region); 313 314 switch (region->cpp) { 315 case 2: 316 format = BRW_DEPTHFORMAT_D16_UNORM; 317 break; 318 case 4: 319 if (intel->depth_buffer_is_float) 320 format = BRW_DEPTHFORMAT_D32_FLOAT; 321 else if (hiz_region) 322 format = BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; 323 else 324 format = BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; 325 break; 326 default: 327 assert(0); 328 return; 329 } 330 331 offset = intel_region_tile_offsets(region, &tile_x, &tile_y); 332 333 assert(intel->gen < 6 || region->tiling == I915_TILING_Y); 334 assert(!hiz_region || region->tiling == I915_TILING_Y); 335 336 BEGIN_BATCH(len); 337 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); 338 OUT_BATCH(((region->pitch * region->cpp) - 1) | 339 (format << 18) | 340 ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */ 341 ((hiz_region ? 1 : 0) << 22) | /* hiz enable */ 342 (BRW_TILEWALK_YMAJOR << 26) | 343 ((region->tiling != I915_TILING_NONE) << 27) | 344 (BRW_SURFACE_2D << 29)); 345 OUT_RELOC(region->buffer, 346 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 347 offset); 348 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) | 349 ((region->width - 1) << 6) | 350 ((region->height - 1) << 19)); 351 OUT_BATCH(0); 352 353 if (intel->is_g4x || intel->gen >= 5) 354 OUT_BATCH(tile_x | (tile_y << 16)); 355 else 356 assert(tile_x == 0 && tile_y == 0); 357 358 if (intel->gen >= 6) 359 OUT_BATCH(0); 360 361 ADVANCE_BATCH(); 362 } 363 364 /* Emit hiz buffer. */ 365 if (hiz_region || stencil_irb) { 366 BEGIN_BATCH(3); 367 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); 368 OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1); 369 OUT_RELOC(hiz_region->buffer, 370 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 371 0); 372 ADVANCE_BATCH(); 373 } 374 375 /* Emit stencil buffer. */ 376 if (hiz_region || stencil_irb) { 377 BEGIN_BATCH(3); 378 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); 379 OUT_BATCH(stencil_irb->region->pitch * stencil_irb->region->cpp - 1); 380 OUT_RELOC(stencil_irb->region->buffer, 381 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 382 0); 383 ADVANCE_BATCH(); 384 } 385 386 /* 387 * On Gen >= 6, emit clear params for safety. If using hiz, then clear 388 * params must be emitted. 389 * 390 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS: 391 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet 392 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes. 393 */ 394 if (intel->gen >= 6 || hiz_region) { 395 BEGIN_BATCH(2); 396 OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2)); 397 OUT_BATCH(0); 398 ADVANCE_BATCH(); 399 } 400} 401 402const struct brw_tracked_state brw_depthbuffer = { 403 .dirty = { 404 .mesa = _NEW_BUFFERS, 405 .brw = BRW_NEW_BATCH, 406 .cache = 0, 407 }, 408 .prepare = prepare_depthbuffer, 409 .emit = emit_depthbuffer, 410}; 411 412 413 414/*********************************************************************** 415 * Polygon stipple packet 416 */ 417 418static void upload_polygon_stipple(struct brw_context *brw) 419{ 420 struct intel_context *intel = &brw->intel; 421 struct gl_context *ctx = &brw->intel.ctx; 422 GLuint i; 423 424 if (!ctx->Polygon.StippleFlag) 425 return; 426 427 BEGIN_BATCH(33); 428 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2)); 429 430 /* Polygon stipple is provided in OpenGL order, i.e. bottom 431 * row first. If we're rendering to a window (i.e. the 432 * default frame buffer object, 0), then we need to invert 433 * it to match our pixel layout. But if we're rendering 434 * to a FBO (i.e. any named frame buffer object), we *don't* 435 * need to invert - we already match the layout. 436 */ 437 if (ctx->DrawBuffer->Name == 0) { 438 for (i = 0; i < 32; i++) 439 OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */ 440 } 441 else { 442 for (i = 0; i < 32; i++) 443 OUT_BATCH(ctx->PolygonStipple[i]); 444 } 445 CACHED_BATCH(); 446} 447 448const struct brw_tracked_state brw_polygon_stipple = { 449 .dirty = { 450 .mesa = _NEW_POLYGONSTIPPLE, 451 .brw = BRW_NEW_CONTEXT, 452 .cache = 0 453 }, 454 .emit = upload_polygon_stipple 455}; 456 457 458/*********************************************************************** 459 * Polygon stipple offset packet 460 */ 461 462static void upload_polygon_stipple_offset(struct brw_context *brw) 463{ 464 struct intel_context *intel = &brw->intel; 465 struct gl_context *ctx = &brw->intel.ctx; 466 467 if (!ctx->Polygon.StippleFlag) 468 return; 469 470 BEGIN_BATCH(2); 471 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2)); 472 473 /* If we're drawing to a system window (ctx->DrawBuffer->Name == 0), 474 * we have to invert the Y axis in order to match the OpenGL 475 * pixel coordinate system, and our offset must be matched 476 * to the window position. If we're drawing to a FBO 477 * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate 478 * system works just fine, and there's no window system to 479 * worry about. 480 */ 481 if (brw->intel.ctx.DrawBuffer->Name == 0) 482 OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31); 483 else 484 OUT_BATCH(0); 485 CACHED_BATCH(); 486} 487 488#define _NEW_WINDOW_POS 0x40000000 489 490const struct brw_tracked_state brw_polygon_stipple_offset = { 491 .dirty = { 492 .mesa = _NEW_WINDOW_POS | _NEW_POLYGONSTIPPLE, 493 .brw = BRW_NEW_CONTEXT, 494 .cache = 0 495 }, 496 .emit = upload_polygon_stipple_offset 497}; 498 499/********************************************************************** 500 * AA Line parameters 501 */ 502static void upload_aa_line_parameters(struct brw_context *brw) 503{ 504 struct intel_context *intel = &brw->intel; 505 struct gl_context *ctx = &brw->intel.ctx; 506 507 if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters) 508 return; 509 510 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2)); 511 /* use legacy aa line coverage computation */ 512 OUT_BATCH(0); 513 OUT_BATCH(0); 514 CACHED_BATCH(); 515} 516 517const struct brw_tracked_state brw_aa_line_parameters = { 518 .dirty = { 519 .mesa = _NEW_LINE, 520 .brw = BRW_NEW_CONTEXT, 521 .cache = 0 522 }, 523 .emit = upload_aa_line_parameters 524}; 525 526/*********************************************************************** 527 * Line stipple packet 528 */ 529 530static void upload_line_stipple(struct brw_context *brw) 531{ 532 struct intel_context *intel = &brw->intel; 533 struct gl_context *ctx = &brw->intel.ctx; 534 GLfloat tmp; 535 GLint tmpi; 536 537 if (!ctx->Line.StippleFlag) 538 return; 539 540 BEGIN_BATCH(3); 541 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2)); 542 OUT_BATCH(ctx->Line.StipplePattern); 543 tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor; 544 tmpi = tmp * (1<<13); 545 OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor); 546 CACHED_BATCH(); 547} 548 549const struct brw_tracked_state brw_line_stipple = { 550 .dirty = { 551 .mesa = _NEW_LINE, 552 .brw = BRW_NEW_CONTEXT, 553 .cache = 0 554 }, 555 .emit = upload_line_stipple 556}; 557 558 559/*********************************************************************** 560 * Misc invarient state packets 561 */ 562 563static void upload_invarient_state( struct brw_context *brw ) 564{ 565 struct intel_context *intel = &brw->intel; 566 567 { 568 /* 0x61040000 Pipeline Select */ 569 /* PipelineSelect : 0 */ 570 struct brw_pipeline_select ps; 571 572 memset(&ps, 0, sizeof(ps)); 573 ps.header.opcode = brw->CMD_PIPELINE_SELECT; 574 ps.header.pipeline_select = 0; 575 BRW_BATCH_STRUCT(brw, &ps); 576 } 577 578 if (intel->gen < 6) { 579 struct brw_global_depth_offset_clamp gdo; 580 memset(&gdo, 0, sizeof(gdo)); 581 582 /* Disable depth offset clamping. 583 */ 584 gdo.header.opcode = _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP; 585 gdo.header.length = sizeof(gdo)/4 - 2; 586 gdo.depth_offset_clamp = 0.0; 587 588 BRW_BATCH_STRUCT(brw, &gdo); 589 } 590 591 if (intel->gen >= 6) { 592 int i; 593 int len = intel->gen >= 7 ? 4 : 3; 594 595 BEGIN_BATCH(len); 596 OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2)); 597 OUT_BATCH(MS_PIXEL_LOCATION_CENTER | 598 MS_NUMSAMPLES_1); 599 OUT_BATCH(0); /* positions for 4/8-sample */ 600 if (intel->gen >= 7) 601 OUT_BATCH(0); 602 ADVANCE_BATCH(); 603 604 BEGIN_BATCH(2); 605 OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2)); 606 OUT_BATCH(1); 607 ADVANCE_BATCH(); 608 609 for (i = 0; i < 4; i++) { 610 BEGIN_BATCH(4); 611 OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2)); 612 OUT_BATCH(i << SVB_INDEX_SHIFT); 613 OUT_BATCH(0); 614 OUT_BATCH(0xffffffff); 615 ADVANCE_BATCH(); 616 } 617 } 618 619 /* 0x61020000 State Instruction Pointer */ 620 { 621 struct brw_system_instruction_pointer sip; 622 memset(&sip, 0, sizeof(sip)); 623 624 sip.header.opcode = CMD_STATE_INSN_POINTER; 625 sip.header.length = 0; 626 sip.bits0.pad = 0; 627 sip.bits0.system_instruction_pointer = 0; 628 BRW_BATCH_STRUCT(brw, &sip); 629 } 630 631 632 { 633 struct brw_vf_statistics vfs; 634 memset(&vfs, 0, sizeof(vfs)); 635 636 vfs.opcode = brw->CMD_VF_STATISTICS; 637 if (unlikely(INTEL_DEBUG & DEBUG_STATS)) 638 vfs.statistics_enable = 1; 639 640 BRW_BATCH_STRUCT(brw, &vfs); 641 } 642} 643 644const struct brw_tracked_state brw_invarient_state = { 645 .dirty = { 646 .mesa = 0, 647 .brw = BRW_NEW_CONTEXT, 648 .cache = 0 649 }, 650 .emit = upload_invarient_state 651}; 652 653/** 654 * Define the base addresses which some state is referenced from. 655 * 656 * This allows us to avoid having to emit relocations for the objects, 657 * and is actually required for binding table pointers on gen6. 658 * 659 * Surface state base address covers binding table pointers and 660 * surface state objects, but not the surfaces that the surface state 661 * objects point to. 662 */ 663static void upload_state_base_address( struct brw_context *brw ) 664{ 665 struct intel_context *intel = &brw->intel; 666 667 if (intel->gen >= 6) { 668 BEGIN_BATCH(10); 669 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); 670 /* General state base address: stateless DP read/write requests */ 671 OUT_BATCH(1); 672 /* Surface state base address: 673 * BINDING_TABLE_STATE 674 * SURFACE_STATE 675 */ 676 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1); 677 /* Dynamic state base address: 678 * SAMPLER_STATE 679 * SAMPLER_BORDER_COLOR_STATE 680 * CLIP, SF, WM/CC viewport state 681 * COLOR_CALC_STATE 682 * DEPTH_STENCIL_STATE 683 * BLEND_STATE 684 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset 685 * Disable is clear, which we rely on) 686 */ 687 OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER | 688 I915_GEM_DOMAIN_INSTRUCTION), 0, 1); 689 690 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */ 691 OUT_BATCH(1); /* Instruction base address: shader kernels (incl. SIP) */ 692 OUT_BATCH(1); /* General state upper bound */ 693 OUT_BATCH(1); /* Dynamic state upper bound */ 694 OUT_BATCH(1); /* Indirect object upper bound */ 695 OUT_BATCH(1); /* Instruction access upper bound */ 696 ADVANCE_BATCH(); 697 } else if (intel->gen == 5) { 698 BEGIN_BATCH(8); 699 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2)); 700 OUT_BATCH(1); /* General state base address */ 701 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 702 1); /* Surface state base address */ 703 OUT_BATCH(1); /* Indirect object base address */ 704 OUT_BATCH(1); /* Instruction base address */ 705 OUT_BATCH(1); /* General state upper bound */ 706 OUT_BATCH(1); /* Indirect object upper bound */ 707 OUT_BATCH(1); /* Instruction access upper bound */ 708 ADVANCE_BATCH(); 709 } else { 710 BEGIN_BATCH(6); 711 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2)); 712 OUT_BATCH(1); /* General state base address */ 713 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 714 1); /* Surface state base address */ 715 OUT_BATCH(1); /* Indirect object base address */ 716 OUT_BATCH(1); /* General state upper bound */ 717 OUT_BATCH(1); /* Indirect object upper bound */ 718 ADVANCE_BATCH(); 719 } 720} 721 722const struct brw_tracked_state brw_state_base_address = { 723 .dirty = { 724 .mesa = 0, 725 .brw = BRW_NEW_BATCH, 726 .cache = 0, 727 }, 728 .emit = upload_state_base_address 729}; 730