brw_misc_state.c revision 9308f298300beaa757194a0db8ed50924754c011
1/* 2 Copyright (C) Intel Corp. 2006. All Rights Reserved. 3 Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to 4 develop this 3D driver. 5 6 Permission is hereby granted, free of charge, to any person obtaining 7 a copy of this software and associated documentation files (the 8 "Software"), to deal in the Software without restriction, including 9 without limitation the rights to use, copy, modify, merge, publish, 10 distribute, sublicense, and/or sell copies of the Software, and to 11 permit persons to whom the Software is furnished to do so, subject to 12 the following conditions: 13 14 The above copyright notice and this permission notice (including the 15 next paragraph) shall be included in all copies or substantial 16 portions of the Software. 17 18 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 19 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 20 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. 21 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE 22 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION 23 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 24 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 25 26 **********************************************************************/ 27 /* 28 * Authors: 29 * Keith Whitwell <keith@tungstengraphics.com> 30 */ 31 32 33 34#include "intel_batchbuffer.h" 35#include "intel_fbo.h" 36#include "intel_mipmap_tree.h" 37#include "intel_regions.h" 38 39#include "brw_context.h" 40#include "brw_state.h" 41#include "brw_defines.h" 42 43/* Constant single cliprect for framebuffer object or DRI2 drawing */ 44static void upload_drawing_rect(struct brw_context *brw) 45{ 46 struct intel_context *intel = &brw->intel; 47 struct gl_context *ctx = &intel->ctx; 48 49 BEGIN_BATCH(4); 50 OUT_BATCH(_3DSTATE_DRAWING_RECTANGLE << 16 | (4 - 2)); 51 OUT_BATCH(0); /* xmin, ymin */ 52 OUT_BATCH(((ctx->DrawBuffer->Width - 1) & 0xffff) | 53 ((ctx->DrawBuffer->Height - 1) << 16)); 54 OUT_BATCH(0); 55 ADVANCE_BATCH(); 56} 57 58const struct brw_tracked_state brw_drawing_rect = { 59 .dirty = { 60 .mesa = _NEW_BUFFERS, 61 .brw = BRW_NEW_CONTEXT, 62 .cache = 0 63 }, 64 .emit = upload_drawing_rect 65}; 66 67/** 68 * Upload the binding table pointers, which point each stage's array of surface 69 * state pointers. 70 * 71 * The binding table pointers are relative to the surface state base address, 72 * which points at the batchbuffer containing the streamed batch state. 73 */ 74static void upload_binding_table_pointers(struct brw_context *brw) 75{ 76 struct intel_context *intel = &brw->intel; 77 78 BEGIN_BATCH(6); 79 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | (6 - 2)); 80 OUT_BATCH(brw->bind.bo_offset); 81 OUT_BATCH(0); /* gs */ 82 OUT_BATCH(0); /* clip */ 83 OUT_BATCH(0); /* sf */ 84 OUT_BATCH(brw->bind.bo_offset); 85 ADVANCE_BATCH(); 86} 87 88const struct brw_tracked_state brw_binding_table_pointers = { 89 .dirty = { 90 .mesa = 0, 91 .brw = (BRW_NEW_BATCH | 92 BRW_NEW_STATE_BASE_ADDRESS | 93 BRW_NEW_VS_BINDING_TABLE | 94 BRW_NEW_GS_BINDING_TABLE | 95 BRW_NEW_PS_BINDING_TABLE), 96 .cache = 0, 97 }, 98 .emit = upload_binding_table_pointers, 99}; 100 101/** 102 * Upload the binding table pointers, which point each stage's array of surface 103 * state pointers. 104 * 105 * The binding table pointers are relative to the surface state base address, 106 * which points at the batchbuffer containing the streamed batch state. 107 */ 108static void upload_gen6_binding_table_pointers(struct brw_context *brw) 109{ 110 struct intel_context *intel = &brw->intel; 111 112 BEGIN_BATCH(4); 113 OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS << 16 | 114 GEN6_BINDING_TABLE_MODIFY_VS | 115 GEN6_BINDING_TABLE_MODIFY_GS | 116 GEN6_BINDING_TABLE_MODIFY_PS | 117 (4 - 2)); 118 OUT_BATCH(brw->bind.bo_offset); /* vs */ 119 OUT_BATCH(brw->bind.bo_offset); /* gs */ 120 OUT_BATCH(brw->bind.bo_offset); /* wm/ps */ 121 ADVANCE_BATCH(); 122} 123 124const struct brw_tracked_state gen6_binding_table_pointers = { 125 .dirty = { 126 .mesa = 0, 127 .brw = (BRW_NEW_BATCH | 128 BRW_NEW_STATE_BASE_ADDRESS | 129 BRW_NEW_VS_BINDING_TABLE | 130 BRW_NEW_GS_BINDING_TABLE | 131 BRW_NEW_PS_BINDING_TABLE), 132 .cache = 0, 133 }, 134 .emit = upload_gen6_binding_table_pointers, 135}; 136 137/** 138 * Upload pointers to the per-stage state. 139 * 140 * The state pointers in this packet are all relative to the general state 141 * base address set by CMD_STATE_BASE_ADDRESS, which is 0. 142 */ 143static void upload_pipelined_state_pointers(struct brw_context *brw ) 144{ 145 struct intel_context *intel = &brw->intel; 146 147 if (intel->gen == 5) { 148 /* Need to flush before changing clip max threads for errata. */ 149 BEGIN_BATCH(1); 150 OUT_BATCH(MI_FLUSH); 151 ADVANCE_BATCH(); 152 } 153 154 BEGIN_BATCH(7); 155 OUT_BATCH(_3DSTATE_PIPELINED_POINTERS << 16 | (7 - 2)); 156 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 157 brw->vs.state_offset); 158 if (brw->gs.prog_active) 159 OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 160 brw->gs.state_offset | 1); 161 else 162 OUT_BATCH(0); 163 OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 164 brw->clip.state_offset | 1); 165 OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 166 brw->sf.state_offset); 167 OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 168 brw->wm.state_offset); 169 OUT_RELOC(brw->intel.batch.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 170 brw->cc.state_offset); 171 ADVANCE_BATCH(); 172 173 brw->state.dirty.brw |= BRW_NEW_PSP; 174} 175 176static void upload_psp_urb_cbs(struct brw_context *brw ) 177{ 178 upload_pipelined_state_pointers(brw); 179 brw_upload_urb_fence(brw); 180 brw_upload_cs_urb_state(brw); 181} 182 183const struct brw_tracked_state brw_psp_urb_cbs = { 184 .dirty = { 185 .mesa = 0, 186 .brw = (BRW_NEW_URB_FENCE | 187 BRW_NEW_BATCH | 188 BRW_NEW_STATE_BASE_ADDRESS), 189 .cache = (CACHE_NEW_VS_UNIT | 190 CACHE_NEW_GS_UNIT | 191 CACHE_NEW_GS_PROG | 192 CACHE_NEW_CLIP_UNIT | 193 CACHE_NEW_SF_UNIT | 194 CACHE_NEW_WM_UNIT | 195 CACHE_NEW_CC_UNIT) 196 }, 197 .emit = upload_psp_urb_cbs, 198}; 199 200uint32_t 201brw_depthbuffer_format(struct brw_context *brw) 202{ 203 struct intel_context *intel = &brw->intel; 204 struct gl_context *ctx = &intel->ctx; 205 struct gl_framebuffer *fb = ctx->DrawBuffer; 206 struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH); 207 struct intel_renderbuffer *srb; 208 209 if (!drb && 210 (srb = intel_get_renderbuffer(fb, BUFFER_STENCIL)) && 211 !srb->mt->stencil_mt && 212 (srb->Base.Format == MESA_FORMAT_S8_Z24 || 213 srb->Base.Format == MESA_FORMAT_Z32_FLOAT_X24S8)) { 214 drb = srb; 215 } 216 217 if (!drb) 218 return BRW_DEPTHFORMAT_D32_FLOAT; 219 220 switch (drb->mt->format) { 221 case MESA_FORMAT_Z16: 222 return BRW_DEPTHFORMAT_D16_UNORM; 223 case MESA_FORMAT_Z32_FLOAT: 224 return BRW_DEPTHFORMAT_D32_FLOAT; 225 case MESA_FORMAT_X8_Z24: 226 return BRW_DEPTHFORMAT_D24_UNORM_X8_UINT; 227 case MESA_FORMAT_S8_Z24: 228 return BRW_DEPTHFORMAT_D24_UNORM_S8_UINT; 229 case MESA_FORMAT_Z32_FLOAT_X24S8: 230 return BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT; 231 default: 232 _mesa_problem(ctx, "Unexpected depth format %s\n", 233 _mesa_get_format_name(drb->Base.Format)); 234 return BRW_DEPTHFORMAT_D16_UNORM; 235 } 236} 237 238static void emit_depthbuffer(struct brw_context *brw) 239{ 240 struct intel_context *intel = &brw->intel; 241 struct gl_context *ctx = &intel->ctx; 242 struct gl_framebuffer *fb = ctx->DrawBuffer; 243 /* _NEW_BUFFERS */ 244 struct intel_renderbuffer *depth_irb = intel_get_renderbuffer(fb, BUFFER_DEPTH); 245 struct intel_renderbuffer *stencil_irb = intel_get_renderbuffer(fb, BUFFER_STENCIL); 246 struct intel_mipmap_tree *stencil_mt = NULL; 247 struct intel_region *hiz_region = NULL; 248 unsigned int len; 249 bool separate_stencil = false; 250 251 if (depth_irb && 252 depth_irb->mt && 253 depth_irb->mt->hiz_mt) { 254 hiz_region = depth_irb->mt->hiz_mt->region; 255 } 256 257 /* 3DSTATE_DEPTH_BUFFER, 3DSTATE_STENCIL_BUFFER are both 258 * non-pipelined state that will need the PIPE_CONTROL workaround. 259 */ 260 if (intel->gen == 6) { 261 intel_emit_post_sync_nonzero_flush(intel); 262 intel_emit_depth_stall_flushes(intel); 263 } 264 265 /* Find the real separate stencil mt if present. */ 266 if (stencil_irb) { 267 stencil_mt = stencil_irb->mt; 268 if (stencil_mt->stencil_mt) 269 stencil_mt = stencil_mt->stencil_mt; 270 271 if (stencil_mt->format == MESA_FORMAT_S8) 272 separate_stencil = true; 273 } 274 275 /* If there's a packed depth/stencil bound to stencil only, we need to 276 * emit the packed depth/stencil buffer packet. 277 */ 278 if (!depth_irb && stencil_irb && !separate_stencil) 279 depth_irb = stencil_irb; 280 281 if (intel->gen >= 6) 282 len = 7; 283 else if (intel->is_g4x || intel->gen == 5) 284 len = 6; 285 else 286 len = 5; 287 288 if (!depth_irb && !separate_stencil) { 289 BEGIN_BATCH(len); 290 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); 291 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | 292 (BRW_SURFACE_NULL << 29)); 293 OUT_BATCH(0); 294 OUT_BATCH(0); 295 OUT_BATCH(0); 296 297 if (intel->is_g4x || intel->gen >= 5) 298 OUT_BATCH(0); 299 300 if (intel->gen >= 6) 301 OUT_BATCH(0); 302 303 ADVANCE_BATCH(); 304 305 } else if (!depth_irb && separate_stencil) { 306 /* 307 * There exists a separate stencil buffer but no depth buffer. 308 * 309 * The stencil buffer inherits most of its fields from 310 * 3DSTATE_DEPTH_BUFFER: namely the tile walk, surface type, width, and 311 * height. 312 * 313 * Since the stencil buffer has quirky pitch requirements, its region 314 * was allocated with half height and double cpp. So we need 315 * a multiplier of 2 to obtain the surface's real height. 316 * 317 * Enable the hiz bit because it and the separate stencil bit must have 318 * the same value. From Section 2.11.5.6.1.1 3DSTATE_DEPTH_BUFFER, Bit 319 * 1.21 "Separate Stencil Enable": 320 * [DevIL]: If this field is enabled, Hierarchical Depth Buffer 321 * Enable must also be enabled. 322 * 323 * [DevGT]: This field must be set to the same value (enabled or 324 * disabled) as Hierarchical Depth Buffer Enable 325 * 326 * The tiled bit must be set. From the Sandybridge PRM, Volume 2, Part 1, 327 * Section 7.5.5.1.1 3DSTATE_DEPTH_BUFFER, Bit 1.27 Tiled Surface: 328 * [DevGT+]: This field must be set to TRUE. 329 */ 330 struct intel_region *region = stencil_mt->region; 331 332 assert(intel->has_separate_stencil); 333 334 BEGIN_BATCH(len); 335 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); 336 OUT_BATCH((BRW_DEPTHFORMAT_D32_FLOAT << 18) | 337 (1 << 21) | /* separate stencil enable */ 338 (1 << 22) | /* hiz enable */ 339 (BRW_TILEWALK_YMAJOR << 26) | 340 (1 << 27) | /* tiled surface */ 341 (BRW_SURFACE_2D << 29)); 342 OUT_BATCH(0); 343 OUT_BATCH(((region->width - 1) << 6) | 344 (2 * region->height - 1) << 19); 345 OUT_BATCH(0); 346 OUT_BATCH(0); 347 348 if (intel->gen >= 6) 349 OUT_BATCH(0); 350 351 ADVANCE_BATCH(); 352 353 } else { 354 struct intel_region *region = depth_irb->mt->region; 355 uint32_t tile_x, tile_y, offset; 356 357 /* If using separate stencil, hiz must be enabled. */ 358 assert(!separate_stencil || hiz_region); 359 360 offset = intel_renderbuffer_tile_offsets(depth_irb, &tile_x, &tile_y); 361 362 assert(intel->gen < 6 || region->tiling == I915_TILING_Y); 363 assert(!hiz_region || region->tiling == I915_TILING_Y); 364 365 BEGIN_BATCH(len); 366 OUT_BATCH(_3DSTATE_DEPTH_BUFFER << 16 | (len - 2)); 367 OUT_BATCH(((region->pitch * region->cpp) - 1) | 368 (brw_depthbuffer_format(brw) << 18) | 369 ((hiz_region ? 1 : 0) << 21) | /* separate stencil enable */ 370 ((hiz_region ? 1 : 0) << 22) | /* hiz enable */ 371 (BRW_TILEWALK_YMAJOR << 26) | 372 ((region->tiling != I915_TILING_NONE) << 27) | 373 (BRW_SURFACE_2D << 29)); 374 OUT_RELOC(region->bo, 375 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 376 offset); 377 OUT_BATCH((BRW_SURFACE_MIPMAPLAYOUT_BELOW << 1) | 378 ((region->width - 1) << 6) | 379 ((region->height - 1) << 19)); 380 OUT_BATCH(0); 381 382 if (intel->is_g4x || intel->gen >= 5) 383 OUT_BATCH(tile_x | (tile_y << 16)); 384 else 385 assert(tile_x == 0 && tile_y == 0); 386 387 if (intel->gen >= 6) 388 OUT_BATCH(0); 389 390 ADVANCE_BATCH(); 391 } 392 393 if (hiz_region || separate_stencil) { 394 /* 395 * In the 3DSTATE_DEPTH_BUFFER batch emitted above, the 'separate 396 * stencil enable' and 'hiz enable' bits were set. Therefore we must 397 * emit 3DSTATE_HIER_DEPTH_BUFFER and 3DSTATE_STENCIL_BUFFER. Even if 398 * there is no stencil buffer, 3DSTATE_STENCIL_BUFFER must be emitted; 399 * failure to do so causes hangs on gen5 and a stall on gen6. 400 */ 401 402 /* Emit hiz buffer. */ 403 if (hiz_region) { 404 BEGIN_BATCH(3); 405 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); 406 OUT_BATCH(hiz_region->pitch * hiz_region->cpp - 1); 407 OUT_RELOC(hiz_region->bo, 408 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 409 0); 410 ADVANCE_BATCH(); 411 } else { 412 BEGIN_BATCH(3); 413 OUT_BATCH((_3DSTATE_HIER_DEPTH_BUFFER << 16) | (3 - 2)); 414 OUT_BATCH(0); 415 OUT_BATCH(0); 416 ADVANCE_BATCH(); 417 } 418 419 /* Emit stencil buffer. */ 420 if (separate_stencil) { 421 struct intel_region *region = stencil_mt->region; 422 BEGIN_BATCH(3); 423 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); 424 OUT_BATCH(region->pitch * region->cpp - 1); 425 OUT_RELOC(region->bo, 426 I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 427 0); 428 ADVANCE_BATCH(); 429 } else { 430 BEGIN_BATCH(3); 431 OUT_BATCH((_3DSTATE_STENCIL_BUFFER << 16) | (3 - 2)); 432 OUT_BATCH(0); 433 OUT_BATCH(0); 434 ADVANCE_BATCH(); 435 } 436 } 437 438 /* 439 * On Gen >= 6, emit clear params for safety. If using hiz, then clear 440 * params must be emitted. 441 * 442 * From Section 2.11.5.6.4.1 3DSTATE_CLEAR_PARAMS: 443 * 3DSTATE_CLEAR_PARAMS packet must follow the DEPTH_BUFFER_STATE packet 444 * when HiZ is enabled and the DEPTH_BUFFER_STATE changes. 445 */ 446 if (intel->gen >= 6 || hiz_region) { 447 if (intel->gen == 6) 448 intel_emit_post_sync_nonzero_flush(intel); 449 450 BEGIN_BATCH(2); 451 OUT_BATCH(_3DSTATE_CLEAR_PARAMS << 16 | (2 - 2)); 452 OUT_BATCH(0); 453 ADVANCE_BATCH(); 454 } 455} 456 457const struct brw_tracked_state brw_depthbuffer = { 458 .dirty = { 459 .mesa = _NEW_BUFFERS, 460 .brw = BRW_NEW_BATCH, 461 .cache = 0, 462 }, 463 .emit = emit_depthbuffer, 464}; 465 466 467 468/*********************************************************************** 469 * Polygon stipple packet 470 */ 471 472static void upload_polygon_stipple(struct brw_context *brw) 473{ 474 struct intel_context *intel = &brw->intel; 475 struct gl_context *ctx = &brw->intel.ctx; 476 GLuint i; 477 478 /* _NEW_POLYGON */ 479 if (!ctx->Polygon.StippleFlag) 480 return; 481 482 if (intel->gen == 6) 483 intel_emit_post_sync_nonzero_flush(intel); 484 485 BEGIN_BATCH(33); 486 OUT_BATCH(_3DSTATE_POLY_STIPPLE_PATTERN << 16 | (33 - 2)); 487 488 /* Polygon stipple is provided in OpenGL order, i.e. bottom 489 * row first. If we're rendering to a window (i.e. the 490 * default frame buffer object, 0), then we need to invert 491 * it to match our pixel layout. But if we're rendering 492 * to a FBO (i.e. any named frame buffer object), we *don't* 493 * need to invert - we already match the layout. 494 */ 495 if (ctx->DrawBuffer->Name == 0) { 496 for (i = 0; i < 32; i++) 497 OUT_BATCH(ctx->PolygonStipple[31 - i]); /* invert */ 498 } 499 else { 500 for (i = 0; i < 32; i++) 501 OUT_BATCH(ctx->PolygonStipple[i]); 502 } 503 CACHED_BATCH(); 504} 505 506const struct brw_tracked_state brw_polygon_stipple = { 507 .dirty = { 508 .mesa = (_NEW_POLYGONSTIPPLE | 509 _NEW_POLYGON), 510 .brw = BRW_NEW_CONTEXT, 511 .cache = 0 512 }, 513 .emit = upload_polygon_stipple 514}; 515 516 517/*********************************************************************** 518 * Polygon stipple offset packet 519 */ 520 521static void upload_polygon_stipple_offset(struct brw_context *brw) 522{ 523 struct intel_context *intel = &brw->intel; 524 struct gl_context *ctx = &brw->intel.ctx; 525 526 /* _NEW_POLYGON */ 527 if (!ctx->Polygon.StippleFlag) 528 return; 529 530 if (intel->gen == 6) 531 intel_emit_post_sync_nonzero_flush(intel); 532 533 BEGIN_BATCH(2); 534 OUT_BATCH(_3DSTATE_POLY_STIPPLE_OFFSET << 16 | (2-2)); 535 536 /* _NEW_BUFFERS 537 * 538 * If we're drawing to a system window (ctx->DrawBuffer->Name == 0), 539 * we have to invert the Y axis in order to match the OpenGL 540 * pixel coordinate system, and our offset must be matched 541 * to the window position. If we're drawing to a FBO 542 * (ctx->DrawBuffer->Name != 0), then our native pixel coordinate 543 * system works just fine, and there's no window system to 544 * worry about. 545 */ 546 if (brw->intel.ctx.DrawBuffer->Name == 0) 547 OUT_BATCH((32 - (ctx->DrawBuffer->Height & 31)) & 31); 548 else 549 OUT_BATCH(0); 550 CACHED_BATCH(); 551} 552 553const struct brw_tracked_state brw_polygon_stipple_offset = { 554 .dirty = { 555 .mesa = (_NEW_BUFFERS | 556 _NEW_POLYGON), 557 .brw = BRW_NEW_CONTEXT, 558 .cache = 0 559 }, 560 .emit = upload_polygon_stipple_offset 561}; 562 563/********************************************************************** 564 * AA Line parameters 565 */ 566static void upload_aa_line_parameters(struct brw_context *brw) 567{ 568 struct intel_context *intel = &brw->intel; 569 struct gl_context *ctx = &brw->intel.ctx; 570 571 if (!ctx->Line.SmoothFlag || !brw->has_aa_line_parameters) 572 return; 573 574 if (intel->gen == 6) 575 intel_emit_post_sync_nonzero_flush(intel); 576 577 OUT_BATCH(_3DSTATE_AA_LINE_PARAMETERS << 16 | (3 - 2)); 578 /* use legacy aa line coverage computation */ 579 OUT_BATCH(0); 580 OUT_BATCH(0); 581 CACHED_BATCH(); 582} 583 584const struct brw_tracked_state brw_aa_line_parameters = { 585 .dirty = { 586 .mesa = _NEW_LINE, 587 .brw = BRW_NEW_CONTEXT, 588 .cache = 0 589 }, 590 .emit = upload_aa_line_parameters 591}; 592 593/*********************************************************************** 594 * Line stipple packet 595 */ 596 597static void upload_line_stipple(struct brw_context *brw) 598{ 599 struct intel_context *intel = &brw->intel; 600 struct gl_context *ctx = &brw->intel.ctx; 601 GLfloat tmp; 602 GLint tmpi; 603 604 if (!ctx->Line.StippleFlag) 605 return; 606 607 if (intel->gen == 6) 608 intel_emit_post_sync_nonzero_flush(intel); 609 610 BEGIN_BATCH(3); 611 OUT_BATCH(_3DSTATE_LINE_STIPPLE_PATTERN << 16 | (3 - 2)); 612 OUT_BATCH(ctx->Line.StipplePattern); 613 tmp = 1.0 / (GLfloat) ctx->Line.StippleFactor; 614 tmpi = tmp * (1<<13); 615 OUT_BATCH(tmpi << 16 | ctx->Line.StippleFactor); 616 CACHED_BATCH(); 617} 618 619const struct brw_tracked_state brw_line_stipple = { 620 .dirty = { 621 .mesa = _NEW_LINE, 622 .brw = BRW_NEW_CONTEXT, 623 .cache = 0 624 }, 625 .emit = upload_line_stipple 626}; 627 628 629/*********************************************************************** 630 * Misc invarient state packets 631 */ 632 633static void upload_invarient_state( struct brw_context *brw ) 634{ 635 struct intel_context *intel = &brw->intel; 636 637 /* 3DSTATE_SIP, 3DSTATE_MULTISAMPLE, etc. are nonpipelined. */ 638 if (intel->gen == 6) 639 intel_emit_post_sync_nonzero_flush(intel); 640 641 /* Select the 3D pipeline (as opposed to media) */ 642 BEGIN_BATCH(1); 643 OUT_BATCH(brw->CMD_PIPELINE_SELECT << 16 | 0); 644 ADVANCE_BATCH(); 645 646 if (intel->gen < 6) { 647 /* Disable depth offset clamping. */ 648 BEGIN_BATCH(2); 649 OUT_BATCH(_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP << 16 | (2 - 2)); 650 OUT_BATCH_F(0.0); 651 ADVANCE_BATCH(); 652 } 653 654 if (intel->gen >= 6) { 655 int i; 656 int len = intel->gen >= 7 ? 4 : 3; 657 658 BEGIN_BATCH(len); 659 OUT_BATCH(_3DSTATE_MULTISAMPLE << 16 | (len - 2)); 660 OUT_BATCH(MS_PIXEL_LOCATION_CENTER | 661 MS_NUMSAMPLES_1); 662 OUT_BATCH(0); /* positions for 4/8-sample */ 663 if (intel->gen >= 7) 664 OUT_BATCH(0); 665 ADVANCE_BATCH(); 666 667 BEGIN_BATCH(2); 668 OUT_BATCH(_3DSTATE_SAMPLE_MASK << 16 | (2 - 2)); 669 OUT_BATCH(1); 670 ADVANCE_BATCH(); 671 672 if (intel->gen < 7) { 673 for (i = 0; i < 4; i++) { 674 BEGIN_BATCH(4); 675 OUT_BATCH(_3DSTATE_GS_SVB_INDEX << 16 | (4 - 2)); 676 OUT_BATCH(i << SVB_INDEX_SHIFT); 677 OUT_BATCH(0); 678 OUT_BATCH(0xffffffff); 679 ADVANCE_BATCH(); 680 } 681 } 682 } 683 684 BEGIN_BATCH(2); 685 OUT_BATCH(CMD_STATE_SIP << 16 | (2 - 2)); 686 OUT_BATCH(0); 687 ADVANCE_BATCH(); 688 689 BEGIN_BATCH(1); 690 OUT_BATCH(brw->CMD_VF_STATISTICS << 16 | 691 (unlikely(INTEL_DEBUG & DEBUG_STATS) ? 1 : 0)); 692 ADVANCE_BATCH(); 693} 694 695const struct brw_tracked_state brw_invarient_state = { 696 .dirty = { 697 .mesa = 0, 698 .brw = BRW_NEW_CONTEXT, 699 .cache = 0 700 }, 701 .emit = upload_invarient_state 702}; 703 704/** 705 * Define the base addresses which some state is referenced from. 706 * 707 * This allows us to avoid having to emit relocations for the objects, 708 * and is actually required for binding table pointers on gen6. 709 * 710 * Surface state base address covers binding table pointers and 711 * surface state objects, but not the surfaces that the surface state 712 * objects point to. 713 */ 714static void upload_state_base_address( struct brw_context *brw ) 715{ 716 struct intel_context *intel = &brw->intel; 717 718 /* FINISHME: According to section 3.6.1 "STATE_BASE_ADDRESS" of 719 * vol1a of the G45 PRM, MI_FLUSH with the ISC invalidate should be 720 * programmed prior to STATE_BASE_ADDRESS. 721 * 722 * However, given that the instruction SBA (general state base 723 * address) on this chipset is always set to 0 across X and GL, 724 * maybe this isn't required for us in particular. 725 */ 726 727 if (intel->gen >= 6) { 728 if (intel->gen == 6) 729 intel_emit_post_sync_nonzero_flush(intel); 730 731 BEGIN_BATCH(10); 732 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (10 - 2)); 733 /* General state base address: stateless DP read/write requests */ 734 OUT_BATCH(1); 735 /* Surface state base address: 736 * BINDING_TABLE_STATE 737 * SURFACE_STATE 738 */ 739 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 1); 740 /* Dynamic state base address: 741 * SAMPLER_STATE 742 * SAMPLER_BORDER_COLOR_STATE 743 * CLIP, SF, WM/CC viewport state 744 * COLOR_CALC_STATE 745 * DEPTH_STENCIL_STATE 746 * BLEND_STATE 747 * Push constants (when INSTPM: CONSTANT_BUFFER Address Offset 748 * Disable is clear, which we rely on) 749 */ 750 OUT_RELOC(intel->batch.bo, (I915_GEM_DOMAIN_RENDER | 751 I915_GEM_DOMAIN_INSTRUCTION), 0, 1); 752 753 OUT_BATCH(1); /* Indirect object base address: MEDIA_OBJECT data */ 754 OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 755 1); /* Instruction base address: shader kernels (incl. SIP) */ 756 757 OUT_BATCH(1); /* General state upper bound */ 758 OUT_BATCH(1); /* Dynamic state upper bound */ 759 OUT_BATCH(1); /* Indirect object upper bound */ 760 OUT_BATCH(1); /* Instruction access upper bound */ 761 ADVANCE_BATCH(); 762 } else if (intel->gen == 5) { 763 BEGIN_BATCH(8); 764 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (8 - 2)); 765 OUT_BATCH(1); /* General state base address */ 766 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 767 1); /* Surface state base address */ 768 OUT_BATCH(1); /* Indirect object base address */ 769 OUT_RELOC(brw->cache.bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 770 1); /* Instruction base address */ 771 OUT_BATCH(1); /* General state upper bound */ 772 OUT_BATCH(1); /* Indirect object upper bound */ 773 OUT_BATCH(1); /* Instruction access upper bound */ 774 ADVANCE_BATCH(); 775 } else { 776 BEGIN_BATCH(6); 777 OUT_BATCH(CMD_STATE_BASE_ADDRESS << 16 | (6 - 2)); 778 OUT_BATCH(1); /* General state base address */ 779 OUT_RELOC(intel->batch.bo, I915_GEM_DOMAIN_SAMPLER, 0, 780 1); /* Surface state base address */ 781 OUT_BATCH(1); /* Indirect object base address */ 782 OUT_BATCH(1); /* General state upper bound */ 783 OUT_BATCH(1); /* Indirect object upper bound */ 784 ADVANCE_BATCH(); 785 } 786 787 /* According to section 3.6.1 of VOL1 of the 965 PRM, 788 * STATE_BASE_ADDRESS updates require a reissue of: 789 * 790 * 3DSTATE_PIPELINE_POINTERS 791 * 3DSTATE_BINDING_TABLE_POINTERS 792 * MEDIA_STATE_POINTERS 793 * 794 * and this continues through Ironlake. The Sandy Bridge PRM, vol 795 * 1 part 1 says that the folowing packets must be reissued: 796 * 797 * 3DSTATE_CC_POINTERS 798 * 3DSTATE_BINDING_TABLE_POINTERS 799 * 3DSTATE_SAMPLER_STATE_POINTERS 800 * 3DSTATE_VIEWPORT_STATE_POINTERS 801 * MEDIA_STATE_POINTERS 802 * 803 * Those are always reissued following SBA updates anyway (new 804 * batch time), except in the case of the program cache BO 805 * changing. Having a separate state flag makes the sequence more 806 * obvious. 807 */ 808 809 brw->state.dirty.brw |= BRW_NEW_STATE_BASE_ADDRESS; 810} 811 812const struct brw_tracked_state brw_state_base_address = { 813 .dirty = { 814 .mesa = 0, 815 .brw = (BRW_NEW_BATCH | 816 BRW_NEW_PROGRAM_CACHE), 817 .cache = 0, 818 }, 819 .emit = upload_state_base_address 820}; 821