1/*
2 * QEMU PCI bus manager
3 *
4 * Copyright (c) 2004 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24#include "hw.h"
25#include "pci.h"
26#include "monitor.h"
27#include "net.h"
28#include "sysemu.h"
29
30//#define DEBUG_PCI
31
32struct PCIBus {
33    BusState qbus;
34    int bus_num;
35    int devfn_min;
36    pci_set_irq_fn set_irq;
37    pci_map_irq_fn map_irq;
38    uint32_t config_reg; /* XXX: suppress */
39    /* low level pic */
40    SetIRQFunc *low_set_irq;
41    qemu_irq *irq_opaque;
42    PCIDevice *devices[256];
43    PCIDevice *parent_dev;
44    PCIBus *next;
45    /* The bus IRQ state is the logical OR of the connected devices.
46       Keep a count of the number of devices with raised IRQs.  */
47    int nirq;
48    int irq_count[];
49};
50
51static void pci_update_mappings(PCIDevice *d);
52static void pci_set_irq(void *opaque, int irq_num, int level);
53
54target_phys_addr_t pci_mem_base;
55static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
56static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
57static PCIBus *first_bus;
58
59static void pcibus_save(QEMUFile *f, void *opaque)
60{
61    PCIBus *bus = (PCIBus *)opaque;
62    int i;
63
64    qemu_put_be32(f, bus->nirq);
65    for (i = 0; i < bus->nirq; i++)
66        qemu_put_be32(f, bus->irq_count[i]);
67}
68
69static int  pcibus_load(QEMUFile *f, void *opaque, int version_id)
70{
71    PCIBus *bus = (PCIBus *)opaque;
72    int i, nirq;
73
74    if (version_id != 1)
75        return -EINVAL;
76
77    nirq = qemu_get_be32(f);
78    if (bus->nirq != nirq) {
79        fprintf(stderr, "pcibus_load: nirq mismatch: src=%d dst=%d\n",
80                nirq, bus->nirq);
81        return -EINVAL;
82    }
83
84    for (i = 0; i < nirq; i++)
85        bus->irq_count[i] = qemu_get_be32(f);
86
87    return 0;
88}
89
90PCIBus *pci_register_bus(DeviceState *parent, const char *name,
91                         pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
92                         qemu_irq *pic, int devfn_min, int nirq)
93{
94    PCIBus *bus;
95    static int nbus = 0;
96
97    bus = FROM_QBUS(PCIBus, qbus_create(BUS_TYPE_PCI,
98                                        sizeof(PCIBus) + (nirq * sizeof(int)),
99                                        parent, name));
100    bus->set_irq = set_irq;
101    bus->map_irq = map_irq;
102    bus->irq_opaque = pic;
103    bus->devfn_min = devfn_min;
104    bus->nirq = nirq;
105    bus->next = first_bus;
106    first_bus = bus;
107    register_savevm("PCIBUS", nbus++, 1, pcibus_save, pcibus_load, bus);
108    return bus;
109}
110
111static PCIBus *pci_register_secondary_bus(PCIDevice *dev, pci_map_irq_fn map_irq)
112{
113    PCIBus *bus;
114    bus = qemu_mallocz(sizeof(PCIBus));
115    bus->map_irq = map_irq;
116    bus->parent_dev = dev;
117    bus->next = dev->bus->next;
118    dev->bus->next = bus;
119    return bus;
120}
121
122int pci_bus_num(PCIBus *s)
123{
124    return s->bus_num;
125}
126
127void pci_device_save(PCIDevice *s, QEMUFile *f)
128{
129    int i;
130
131    qemu_put_be32(f, 2); /* PCI device version */
132    qemu_put_buffer(f, s->config, 256);
133    for (i = 0; i < 4; i++)
134        qemu_put_be32(f, s->irq_state[i]);
135}
136
137int pci_device_load(PCIDevice *s, QEMUFile *f)
138{
139    uint32_t version_id;
140    int i;
141
142    version_id = qemu_get_be32(f);
143    if (version_id > 2)
144        return -EINVAL;
145    qemu_get_buffer(f, s->config, 256);
146    pci_update_mappings(s);
147
148    if (version_id >= 2)
149        for (i = 0; i < 4; i ++)
150            s->irq_state[i] = qemu_get_be32(f);
151
152    return 0;
153}
154
155static int pci_set_default_subsystem_id(PCIDevice *pci_dev)
156{
157    uint16_t *id;
158
159    id = (void*)(&pci_dev->config[PCI_SUBVENDOR_ID]);
160    id[0] = cpu_to_le16(pci_default_sub_vendor_id);
161    id[1] = cpu_to_le16(pci_default_sub_device_id);
162    return 0;
163}
164
165/*
166 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error
167 */
168static int pci_parse_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
169{
170    const char *p;
171    char *e;
172    unsigned long val;
173    unsigned long dom = 0, bus = 0;
174    unsigned slot = 0;
175
176    p = addr;
177    val = strtoul(p, &e, 16);
178    if (e == p)
179	return -1;
180    if (*e == ':') {
181	bus = val;
182	p = e + 1;
183	val = strtoul(p, &e, 16);
184	if (e == p)
185	    return -1;
186	if (*e == ':') {
187	    dom = bus;
188	    bus = val;
189	    p = e + 1;
190	    val = strtoul(p, &e, 16);
191	    if (e == p)
192		return -1;
193	}
194    }
195
196    if (dom > 0xffff || bus > 0xff || val > 0x1f)
197	return -1;
198
199    slot = val;
200
201    if (*e)
202	return -1;
203
204    /* Note: QEMU doesn't implement domains other than 0 */
205    if (dom != 0 || pci_find_bus(bus) == NULL)
206	return -1;
207
208    *domp = dom;
209    *busp = bus;
210    *slotp = slot;
211    return 0;
212}
213
214int pci_read_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
215{
216    char devaddr[32];
217
218    if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
219        return -1;
220
221    return pci_parse_devaddr(devaddr, domp, busp, slotp);
222}
223
224int pci_assign_devaddr(const char *addr, int *domp, int *busp, unsigned *slotp)
225{
226    char devaddr[32];
227
228    if (!get_param_value(devaddr, sizeof(devaddr), "pci_addr", addr))
229	return -1;
230
231    if (!strcmp(devaddr, "auto")) {
232        *domp = *busp = 0;
233        *slotp = -1;
234        /* want to support dom/bus auto-assign at some point */
235        return 0;
236    }
237
238    return pci_parse_devaddr(devaddr, domp, busp, slotp);
239}
240
241/* -1 for devfn means auto assign */
242static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
243                                         const char *name, int devfn,
244                                         PCIConfigReadFunc *config_read,
245                                         PCIConfigWriteFunc *config_write)
246{
247    if (devfn < 0) {
248        for(devfn = bus->devfn_min ; devfn < 256; devfn += 8) {
249            if (!bus->devices[devfn])
250                goto found;
251        }
252        return NULL;
253    found: ;
254    }
255    pci_dev->bus = bus;
256    pci_dev->devfn = devfn;
257    pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
258    memset(pci_dev->irq_state, 0, sizeof(pci_dev->irq_state));
259    pci_set_default_subsystem_id(pci_dev);
260
261    if (!config_read)
262        config_read = pci_default_read_config;
263    if (!config_write)
264        config_write = pci_default_write_config;
265    pci_dev->config_read = config_read;
266    pci_dev->config_write = config_write;
267    bus->devices[devfn] = pci_dev;
268    pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, 4);
269    return pci_dev;
270}
271
272PCIDevice *pci_register_device(PCIBus *bus, const char *name,
273                               int instance_size, int devfn,
274                               PCIConfigReadFunc *config_read,
275                               PCIConfigWriteFunc *config_write)
276{
277    PCIDevice *pci_dev;
278
279    pci_dev = qemu_mallocz(instance_size);
280    pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
281                                     config_read, config_write);
282    return pci_dev;
283}
284static target_phys_addr_t pci_to_cpu_addr(target_phys_addr_t addr)
285{
286    return addr + pci_mem_base;
287}
288
289static void pci_unregister_io_regions(PCIDevice *pci_dev)
290{
291    PCIIORegion *r;
292    int i;
293
294    for(i = 0; i < PCI_NUM_REGIONS; i++) {
295        r = &pci_dev->io_regions[i];
296        if (!r->size || r->addr == -1)
297            continue;
298        if (r->type == PCI_ADDRESS_SPACE_IO) {
299            isa_unassign_ioport(r->addr, r->size);
300        } else {
301            cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
302                                                     r->size,
303                                                     IO_MEM_UNASSIGNED);
304        }
305    }
306}
307
308int pci_unregister_device(PCIDevice *pci_dev)
309{
310    int ret = 0;
311
312    if (pci_dev->unregister)
313        ret = pci_dev->unregister(pci_dev);
314    if (ret)
315        return ret;
316
317    pci_unregister_io_regions(pci_dev);
318
319    qemu_free_irqs(pci_dev->irq);
320    pci_dev->bus->devices[pci_dev->devfn] = NULL;
321    qdev_free(&pci_dev->qdev);
322    return 0;
323}
324
325void pci_register_bar(PCIDevice *pci_dev, int region_num,
326                            uint32_t size, int type,
327                            PCIMapIORegionFunc *map_func)
328{
329    PCIIORegion *r;
330    uint32_t addr;
331
332    if ((unsigned int)region_num >= PCI_NUM_REGIONS)
333        return;
334
335    if (size & (size-1)) {
336        fprintf(stderr, "ERROR: PCI region size must be pow2 "
337                    "type=0x%x, size=0x%x\n", type, size);
338        exit(1);
339    }
340
341    r = &pci_dev->io_regions[region_num];
342    r->addr = -1;
343    r->size = size;
344    r->type = type;
345    r->map_func = map_func;
346    if (region_num == PCI_ROM_SLOT) {
347        addr = 0x30;
348    } else {
349        addr = 0x10 + region_num * 4;
350    }
351    *(uint32_t *)(pci_dev->config + addr) = cpu_to_le32(type);
352}
353
354static void pci_update_mappings(PCIDevice *d)
355{
356    PCIIORegion *r;
357    int cmd, i;
358    uint32_t last_addr, new_addr, config_ofs;
359
360    cmd = le16_to_cpu(*(uint16_t *)(d->config + PCI_COMMAND));
361    for(i = 0; i < PCI_NUM_REGIONS; i++) {
362        r = &d->io_regions[i];
363        if (i == PCI_ROM_SLOT) {
364            config_ofs = 0x30;
365        } else {
366            config_ofs = 0x10 + i * 4;
367        }
368        if (r->size != 0) {
369            if (r->type & PCI_ADDRESS_SPACE_IO) {
370                if (cmd & PCI_COMMAND_IO) {
371                    new_addr = le32_to_cpu(*(uint32_t *)(d->config +
372                                                         config_ofs));
373                    new_addr = new_addr & ~(r->size - 1);
374                    last_addr = new_addr + r->size - 1;
375                    /* NOTE: we have only 64K ioports on PC */
376                    if (last_addr <= new_addr || new_addr == 0 ||
377                        last_addr >= 0x10000) {
378                        new_addr = -1;
379                    }
380                } else {
381                    new_addr = -1;
382                }
383            } else {
384                if (cmd & PCI_COMMAND_MEMORY) {
385                    new_addr = le32_to_cpu(*(uint32_t *)(d->config +
386                                                         config_ofs));
387                    /* the ROM slot has a specific enable bit */
388                    if (i == PCI_ROM_SLOT && !(new_addr & 1))
389                        goto no_mem_map;
390                    new_addr = new_addr & ~(r->size - 1);
391                    last_addr = new_addr + r->size - 1;
392                    /* NOTE: we do not support wrapping */
393                    /* XXX: as we cannot support really dynamic
394                       mappings, we handle specific values as invalid
395                       mappings. */
396                    if (last_addr <= new_addr || new_addr == 0 ||
397                        last_addr == -1) {
398                        new_addr = -1;
399                    }
400                } else {
401                no_mem_map:
402                    new_addr = -1;
403                }
404            }
405            /* now do the real mapping */
406            if (new_addr != r->addr) {
407                if (r->addr != -1) {
408                    if (r->type & PCI_ADDRESS_SPACE_IO) {
409                        int class;
410                        /* NOTE: specific hack for IDE in PC case:
411                           only one byte must be mapped. */
412                        class = d->config[0x0a] | (d->config[0x0b] << 8);
413                        if (class == 0x0101 && r->size == 4) {
414                            isa_unassign_ioport(r->addr + 2, 1);
415                        } else {
416                            isa_unassign_ioport(r->addr, r->size);
417                        }
418                    } else {
419                        cpu_register_physical_memory(pci_to_cpu_addr(r->addr),
420                                                     r->size,
421                                                     IO_MEM_UNASSIGNED);
422                        qemu_unregister_coalesced_mmio(r->addr, r->size);
423                    }
424                }
425                r->addr = new_addr;
426                if (r->addr != -1) {
427                    r->map_func(d, i, r->addr, r->size, r->type);
428                }
429            }
430        }
431    }
432}
433
434uint32_t pci_default_read_config(PCIDevice *d,
435                                 uint32_t address, int len)
436{
437    uint32_t val;
438
439    switch(len) {
440    default:
441    case 4:
442	if (address <= 0xfc) {
443	    val = le32_to_cpu(*(uint32_t *)(d->config + address));
444	    break;
445	}
446	/* fall through */
447    case 2:
448        if (address <= 0xfe) {
449	    val = le16_to_cpu(*(uint16_t *)(d->config + address));
450	    break;
451	}
452	/* fall through */
453    case 1:
454        val = d->config[address];
455        break;
456    }
457    return val;
458}
459
460void pci_default_write_config(PCIDevice *d,
461                              uint32_t address, uint32_t val, int len)
462{
463    int can_write, i;
464    uint32_t end, addr;
465
466    if (len == 4 && ((address >= 0x10 && address < 0x10 + 4 * 6) ||
467                     (address >= 0x30 && address < 0x34))) {
468        PCIIORegion *r;
469        int reg;
470
471        if ( address >= 0x30 ) {
472            reg = PCI_ROM_SLOT;
473        }else{
474            reg = (address - 0x10) >> 2;
475        }
476        r = &d->io_regions[reg];
477        if (r->size == 0)
478            goto default_config;
479        /* compute the stored value */
480        if (reg == PCI_ROM_SLOT) {
481            /* keep ROM enable bit */
482            val &= (~(r->size - 1)) | 1;
483        } else {
484            val &= ~(r->size - 1);
485            val |= r->type;
486        }
487        *(uint32_t *)(d->config + address) = cpu_to_le32(val);
488        pci_update_mappings(d);
489        return;
490    }
491 default_config:
492    /* not efficient, but simple */
493    addr = address;
494    for(i = 0; i < len; i++) {
495        /* default read/write accesses */
496        switch(d->config[0x0e]) {
497        case 0x00:
498        case 0x80:
499            switch(addr) {
500            case 0x00:
501            case 0x01:
502            case 0x02:
503            case 0x03:
504            case 0x06:
505            case 0x07:
506            case 0x08:
507            case 0x09:
508            case 0x0a:
509            case 0x0b:
510            case 0x0e:
511            case 0x10 ... 0x27: /* base */
512            case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
513            case 0x30 ... 0x33: /* rom */
514            case 0x3d:
515                can_write = 0;
516                break;
517            default:
518                can_write = 1;
519                break;
520            }
521            break;
522        default:
523        case 0x01:
524            switch(addr) {
525            case 0x00:
526            case 0x01:
527            case 0x02:
528            case 0x03:
529            case 0x06:
530            case 0x07:
531            case 0x08:
532            case 0x09:
533            case 0x0a:
534            case 0x0b:
535            case 0x0e:
536            case 0x2c ... 0x2f: /* read-only subsystem ID & vendor ID */
537            case 0x38 ... 0x3b: /* rom */
538            case 0x3d:
539                can_write = 0;
540                break;
541            default:
542                can_write = 1;
543                break;
544            }
545            break;
546        }
547        if (can_write) {
548            /* Mask out writes to reserved bits in registers */
549            switch (addr) {
550	    case 0x05:
551                val &= ~PCI_COMMAND_RESERVED_MASK_HI;
552                break;
553            case 0x06:
554                val &= ~PCI_STATUS_RESERVED_MASK_LO;
555                break;
556            case 0x07:
557                val &= ~PCI_STATUS_RESERVED_MASK_HI;
558                break;
559            }
560            d->config[addr] = val;
561        }
562        if (++addr > 0xff)
563        	break;
564        val >>= 8;
565    }
566
567    end = address + len;
568    if (end > PCI_COMMAND && address < (PCI_COMMAND + 2)) {
569        /* if the command register is modified, we must modify the mappings */
570        pci_update_mappings(d);
571    }
572}
573
574void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len)
575{
576    PCIBus *s = opaque;
577    PCIDevice *pci_dev;
578    int config_addr, bus_num;
579
580#if defined(DEBUG_PCI) && 0
581    printf("pci_data_write: addr=%08x val=%08x len=%d\n",
582           addr, val, len);
583#endif
584    bus_num = (addr >> 16) & 0xff;
585    while (s && s->bus_num != bus_num)
586        s = s->next;
587    if (!s)
588        return;
589    pci_dev = s->devices[(addr >> 8) & 0xff];
590    if (!pci_dev)
591        return;
592    config_addr = addr & 0xff;
593#if defined(DEBUG_PCI)
594    printf("pci_config_write: %s: addr=%02x val=%08x len=%d\n",
595           pci_dev->name, config_addr, val, len);
596#endif
597    pci_dev->config_write(pci_dev, config_addr, val, len);
598}
599
600uint32_t pci_data_read(void *opaque, uint32_t addr, int len)
601{
602    PCIBus *s = opaque;
603    PCIDevice *pci_dev;
604    int config_addr, bus_num;
605    uint32_t val;
606
607    bus_num = (addr >> 16) & 0xff;
608    while (s && s->bus_num != bus_num)
609        s= s->next;
610    if (!s)
611        goto fail;
612    pci_dev = s->devices[(addr >> 8) & 0xff];
613    if (!pci_dev) {
614    fail:
615        switch(len) {
616        case 1:
617            val = 0xff;
618            break;
619        case 2:
620            val = 0xffff;
621            break;
622        default:
623        case 4:
624            val = 0xffffffff;
625            break;
626        }
627        goto the_end;
628    }
629    config_addr = addr & 0xff;
630    val = pci_dev->config_read(pci_dev, config_addr, len);
631#if defined(DEBUG_PCI)
632    printf("pci_config_read: %s: addr=%02x val=%08x len=%d\n",
633           pci_dev->name, config_addr, val, len);
634#endif
635 the_end:
636#if defined(DEBUG_PCI) && 0
637    printf("pci_data_read: addr=%08x val=%08x len=%d\n",
638           addr, val, len);
639#endif
640    return val;
641}
642
643/***********************************************************/
644/* generic PCI irq support */
645
646/* 0 <= irq_num <= 3. level must be 0 or 1 */
647static void pci_set_irq(void *opaque, int irq_num, int level)
648{
649    PCIDevice *pci_dev = (PCIDevice *)opaque;
650    PCIBus *bus;
651    int change;
652
653    change = level - pci_dev->irq_state[irq_num];
654    if (!change)
655        return;
656
657    pci_dev->irq_state[irq_num] = level;
658    for (;;) {
659        bus = pci_dev->bus;
660        irq_num = bus->map_irq(pci_dev, irq_num);
661        if (bus->set_irq)
662            break;
663        pci_dev = bus->parent_dev;
664    }
665    bus->irq_count[irq_num] += change;
666    bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
667}
668
669/***********************************************************/
670/* monitor info on PCI */
671
672typedef struct {
673    uint16_t class;
674    const char *desc;
675} pci_class_desc;
676
677static const pci_class_desc pci_class_descriptions[] =
678{
679    { 0x0100, "SCSI controller"},
680    { 0x0101, "IDE controller"},
681    { 0x0102, "Floppy controller"},
682    { 0x0103, "IPI controller"},
683    { 0x0104, "RAID controller"},
684    { 0x0106, "SATA controller"},
685    { 0x0107, "SAS controller"},
686    { 0x0180, "Storage controller"},
687    { 0x0200, "Ethernet controller"},
688    { 0x0201, "Token Ring controller"},
689    { 0x0202, "FDDI controller"},
690    { 0x0203, "ATM controller"},
691    { 0x0280, "Network controller"},
692    { 0x0300, "VGA controller"},
693    { 0x0301, "XGA controller"},
694    { 0x0302, "3D controller"},
695    { 0x0380, "Display controller"},
696    { 0x0400, "Video controller"},
697    { 0x0401, "Audio controller"},
698    { 0x0402, "Phone"},
699    { 0x0480, "Multimedia controller"},
700    { 0x0500, "RAM controller"},
701    { 0x0501, "Flash controller"},
702    { 0x0580, "Memory controller"},
703    { 0x0600, "Host bridge"},
704    { 0x0601, "ISA bridge"},
705    { 0x0602, "EISA bridge"},
706    { 0x0603, "MC bridge"},
707    { 0x0604, "PCI bridge"},
708    { 0x0605, "PCMCIA bridge"},
709    { 0x0606, "NUBUS bridge"},
710    { 0x0607, "CARDBUS bridge"},
711    { 0x0608, "RACEWAY bridge"},
712    { 0x0680, "Bridge"},
713    { 0x0c03, "USB controller"},
714    { 0, NULL}
715};
716
717static void pci_info_device(PCIDevice *d)
718{
719    Monitor *mon = cur_mon;
720    int i, class;
721    PCIIORegion *r;
722    const pci_class_desc *desc;
723
724    monitor_printf(mon, "  Bus %2d, device %3d, function %d:\n",
725                   d->bus->bus_num, d->devfn >> 3, d->devfn & 7);
726    class = le16_to_cpu(*((uint16_t *)(d->config + PCI_CLASS_DEVICE)));
727    monitor_printf(mon, "    ");
728    desc = pci_class_descriptions;
729    while (desc->desc && class != desc->class)
730        desc++;
731    if (desc->desc) {
732        monitor_printf(mon, "%s", desc->desc);
733    } else {
734        monitor_printf(mon, "Class %04x", class);
735    }
736    monitor_printf(mon, ": PCI device %04x:%04x\n",
737           le16_to_cpu(*((uint16_t *)(d->config + PCI_VENDOR_ID))),
738           le16_to_cpu(*((uint16_t *)(d->config + PCI_DEVICE_ID))));
739
740    if (d->config[PCI_INTERRUPT_PIN] != 0) {
741        monitor_printf(mon, "      IRQ %d.\n",
742                       d->config[PCI_INTERRUPT_LINE]);
743    }
744    if (class == 0x0604) {
745        monitor_printf(mon, "      BUS %d.\n", d->config[0x19]);
746    }
747    for(i = 0;i < PCI_NUM_REGIONS; i++) {
748        r = &d->io_regions[i];
749        if (r->size != 0) {
750            monitor_printf(mon, "      BAR%d: ", i);
751            if (r->type & PCI_ADDRESS_SPACE_IO) {
752                monitor_printf(mon, "I/O at 0x%04x [0x%04x].\n",
753                               r->addr, r->addr + r->size - 1);
754            } else {
755                monitor_printf(mon, "32 bit memory at 0x%08x [0x%08x].\n",
756                               r->addr, r->addr + r->size - 1);
757            }
758        }
759    }
760    if (class == 0x0604 && d->config[0x19] != 0) {
761        pci_for_each_device(d->config[0x19], pci_info_device);
762    }
763}
764
765void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d))
766{
767    PCIBus *bus = first_bus;
768    PCIDevice *d;
769    int devfn;
770
771    while (bus && bus->bus_num != bus_num)
772        bus = bus->next;
773    if (bus) {
774        for(devfn = 0; devfn < 256; devfn++) {
775            d = bus->devices[devfn];
776            if (d)
777                fn(d);
778        }
779    }
780}
781
782void pci_info(Monitor *mon)
783{
784    pci_for_each_device(0, pci_info_device);
785}
786
787static const char * const pci_nic_models[] = {
788    "ne2k_pci",
789    "i82551",
790    "i82557b",
791    "i82559er",
792    "rtl8139",
793    "e1000",
794    "pcnet",
795    "virtio",
796    NULL
797};
798
799static const char * const pci_nic_names[] = {
800    "ne2k_pci",
801    "i82551",
802    "i82557b",
803    "i82559er",
804    "rtl8139",
805    "e1000",
806    "pcnet",
807    "virtio-net-pci",
808    NULL
809};
810
811/* Initialize a PCI NIC.  */
812PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn,
813                  const char *default_model)
814{
815    DeviceState *dev;
816    int i;
817
818    qemu_check_nic_model_list(nd, pci_nic_models, default_model);
819
820    for (i = 0; pci_nic_models[i]; i++) {
821        if (strcmp(nd->model, pci_nic_models[i]) == 0) {
822            dev = qdev_create(&bus->qbus, pci_nic_names[i]);
823            qdev_set_prop_int(dev, "devfn", devfn);
824            qdev_set_netdev(dev, nd);
825            qdev_init(dev);
826            nd->private = dev;
827            return (PCIDevice *)dev;
828        }
829    }
830
831    return NULL;
832}
833
834typedef struct {
835    PCIDevice dev;
836    PCIBus *bus;
837} PCIBridge;
838
839static void pci_bridge_write_config(PCIDevice *d,
840                             uint32_t address, uint32_t val, int len)
841{
842    PCIBridge *s = (PCIBridge *)d;
843
844    if (address == 0x19 || (address == 0x18 && len > 1)) {
845        if (address == 0x19)
846            s->bus->bus_num = val & 0xff;
847        else
848            s->bus->bus_num = (val >> 8) & 0xff;
849#if defined(DEBUG_PCI)
850        printf ("pci-bridge: %s: Assigned bus %d\n", d->name, s->bus->bus_num);
851#endif
852    }
853    pci_default_write_config(d, address, val, len);
854}
855
856PCIBus *pci_find_bus(int bus_num)
857{
858    PCIBus *bus = first_bus;
859
860    while (bus && bus->bus_num != bus_num)
861        bus = bus->next;
862
863    return bus;
864}
865
866PCIDevice *pci_find_device(int bus_num, int slot, int function)
867{
868    PCIBus *bus = pci_find_bus(bus_num);
869
870    if (!bus)
871        return NULL;
872
873    return bus->devices[PCI_DEVFN(slot, function)];
874}
875
876PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint16_t vid, uint16_t did,
877                        pci_map_irq_fn map_irq, const char *name)
878{
879    PCIBridge *s;
880    s = (PCIBridge *)pci_register_device(bus, name, sizeof(PCIBridge),
881                                         devfn, NULL, pci_bridge_write_config);
882
883    pci_config_set_vendor_id(s->dev.config, vid);
884    pci_config_set_device_id(s->dev.config, did);
885
886    s->dev.config[0x04] = 0x06; // command = bus master, pci mem
887    s->dev.config[0x05] = 0x00;
888    s->dev.config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
889    s->dev.config[0x07] = 0x00; // status = fast devsel
890    s->dev.config[0x08] = 0x00; // revision
891    s->dev.config[0x09] = 0x00; // programming i/f
892    pci_config_set_class(s->dev.config, PCI_CLASS_BRIDGE_PCI);
893    s->dev.config[0x0D] = 0x10; // latency_timer
894    s->dev.config[PCI_HEADER_TYPE] =
895        PCI_HEADER_TYPE_MULTI_FUNCTION | PCI_HEADER_TYPE_BRIDGE; // header_type
896    s->dev.config[0x1E] = 0xa0; // secondary status
897
898    s->bus = pci_register_secondary_bus(&s->dev, map_irq);
899    return s->bus;
900}
901
902typedef struct {
903    DeviceInfo qdev;
904    pci_qdev_initfn init;
905} PCIDeviceInfo;
906
907static void pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
908{
909    PCIDevice *pci_dev = (PCIDevice *)qdev;
910    PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
911    PCIBus *bus;
912    int devfn;
913
914    bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
915    devfn = qdev_get_prop_int(qdev, "devfn", -1);
916    pci_dev = do_pci_register_device(pci_dev, bus, "FIXME", devfn,
917                                     NULL, NULL);//FIXME:config_read, config_write);
918    assert(pci_dev);
919    info->init(pci_dev);
920}
921
922void pci_qdev_register(const char *name, int size, pci_qdev_initfn init)
923{
924    PCIDeviceInfo *info;
925
926    info = qemu_mallocz(sizeof(*info));
927    info->qdev.name = qemu_strdup(name);
928    info->qdev.size = size;
929    info->init = init;
930    info->qdev.init = pci_qdev_init;
931    info->qdev.bus_type = BUS_TYPE_PCI;
932
933    qdev_register(&info->qdev);
934}
935
936PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
937{
938    DeviceState *dev;
939
940    dev = qdev_create(&bus->qbus, name);
941    qdev_set_prop_int(dev, "devfn", devfn);
942    qdev_init(dev);
943
944    return (PCIDevice *)dev;
945}
946