5be30072c5a750617dc3f9380776d074f26d9f32 |
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02-Oct-2014 |
Andreas Gampe <agampe@google.com> |
ART: Remove wrong DCHECK Bug: 17772057 Bug: 17763227 Bug: 17762845 Change-Id: If5d35b8e3e156173f2e47ae86ff48ebfc01ca02d
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02ff2d4187249d26fabe8e5eacc27b99984ee353 |
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04-Sep-2014 |
Serguei Katkov <serguei.i.katkov@intel.com> |
AddIntrinsicSlowPath with resume requires clobbering AddIntrinsicSlowPath with resume results in a call. So all temps must be clobbered at the point where AddIntrinsicSlowPath returns. (cherry-picked from 9863daf4fdc1a08339edac794452dbc719aef4f1) Change-Id: If9eb887e295ff5e59920f4da1cef63258ad490b0 Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
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fa9c8ec37c66574654e448513e1bb59af7cb9365 |
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07-Aug-2014 |
Zheng Xu <zheng.xu@arm.com> |
Add arraycopy intrinsic for arm and arm64. Implement intrinsic for java.lang.System.arraycopy(char[], int, char[], int, int). Bug: 16241558 (cherry picked from commit 947717a2b085f36ea007ac64f728e19ff1c8db0b) Change-Id: I8199f5c9ce9827f869f0f93aaff7ec359a84d922
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c76c614d681d187d815760eb909e5faf488a3c35 |
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05-Aug-2014 |
Andreas Gampe <agampe@google.com> |
ART: Refactor long ops in quick compiler Make GenArithOpLong virtual. Let the implementation in gen_common be very basic, without instruction-set checks, and meant as a fall-back. Backends should implement and dispatch to code for better implementations. This allows to remove the GenXXXLong virtual methods from Mir2Lir, and clean up the backends (especially removing some LOG(FATAL) implementations). Change-Id: I6366443c0c325c1999582d281608b4fa229343cf
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c763e350da562b0c6bebf10599588d4901140e45 |
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04-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Implement InexpensiveConstant methods. Implement IsInexpensiveConstant and friends for A64. Also extending the methods to take the opcode with respect to which the constant is inexpensive. Additionally, logical operations (i.e. and, or, xor) can now handle the immediates 0 and ~0 (which are not logical immediates). Change-Id: I46ce1287703765c5ab54983d13c1b3a1f5838622
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f29ecd69af2743a425314baa4abd6c44d8d88649 |
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29-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework ARM64 entry sequence Try to fold one sub of SP in the ARM64 entry sequence. When the framesize is small, generate a sub over the full frame-size, and adjust the spill offsets accordingly. If the framesize is too large, use a pre-indexed store and fill upwards from there. Change-Id: I1c15ac6276fb62b8164372de02fd92437f605938
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63999683329612292d534e6be09dbde9480f1250 |
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15-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
Revert "Revert "Enable Load Store Elimination for ARM and ARM64"" This patch refactors the implementation of the LoadStoreElimination optimisation pass. Please note that this pass was disabled and not functional for any of the backends. The current implementation tracks aliases and handles DalvikRegs as well as Heap memory regions. It has been tested and it is known to optimise out the following: * Load - Load * Store - Load * Store - Store * Load Literals Change-Id: I3aadb12a787164146a95bc314e85fa73ad91e12b
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c32447bcc8c36ee8ff265ed678c7df86936a9ebe |
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27-Jul-2014 |
Bill Buzbee <buzbee@android.com> |
Revert "Enable Load Store Elimination for ARM and ARM64" On extended testing, I'm seeing a CHECK failure at utility_arm.cc:1201. This reverts commit fcc36ba2a2b8fd10e6eebd21ecb6329606443ded. Change-Id: Icae3d49cd7c8fcab09f2f989cbcb1d7e5c6d137a
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fcc36ba2a2b8fd10e6eebd21ecb6329606443ded |
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15-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
Enable Load Store Elimination for ARM and ARM64 This patch refactors the implementation of the LoadStoreElimination optimisation pass. Please note that this pass was disabled and not functional for any of the backends. The current implementation tracks aliases and handles DalvikRegs as well as Heap memory regions. It has been tested and it is known to optimise out the following: * Load - Load * Store - Load * Store - Store * Load Literals Change-Id: Iefae9b696f87f833ef35c451ed4d49c5a1b6fde0
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984305917bf57b3f8d92965e4715a0370cc5bcfb |
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28-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Rework quick entrypoint code in Mir2Lir, cleanup To reduce the complexity of calling trampolines in generic code, introduce an enumeration for entrypoints. Introduce a header that lists the entrypoint enum and exposes a templatized method that translates an enum value to the corresponding thread offset value. Call helpers are rewritten to have an enum parameter instead of the thread offset. Also rewrite LoadHelper and GenConversionCall this way. It is now LoadHelper's duty to select the right thread offset size. Introduce InvokeTrampoline virtual method to Mir2Lir. This allows to further simplify the call helpers, as well as make OpThreadMem specific to X86 only (removed from Mir2Lir). Make GenInlinedCharAt virtual, move a copy to X86 backend, and simplify both copies. Remove LoadBaseIndexedDisp and OpRegMem from Mir2Lir, as they are now specific to X86 only. Remove StoreBaseIndexedDisp from Mir2Lir, as it was only ever used in the X86 backend. Remove OpTlsCmp from Mir2Lir, as it was only ever used in the X86 backend. Remove OpLea from Mir2Lir, as it was only ever defined in the X86 backend. Remove GenImmedCheck from Mir2Lir as it was neither used nor implemented. Change-Id: If0a6182288c5d57653e3979bf547840a4c47626e
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bebee4fd10e5db6cb07f59bc0f73297c900ea5f0 |
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16-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Refactor GenSelect, refactor gen_common accordingly This adds a GenSelect method meant for selection of constants. The general-purpose GenInstanceof code is refactored to take advantage of this. This cleans up code and squashes a branch-over on ARM64 to a cset. Also add a slow-path for type initialization in GenInstanceof. Bug: 16241558 (cherry picked from commit 90969af6deb19b1dbe356d62fe68d8f5698d3d8f) Change-Id: Ie4494858bb8c26d386cf2e628172b81bba911ae5
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147eb41b53729ec8d5c188d1cac90964a51afb8a |
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11-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Revert "Add implicit null and stack checks for x86"""" This reverts commit 0025a86411145eb7cd4971f9234fc21c7b4aced1. Bug: 16256184 Change-Id: Ie0760a0c293aa3b62e2885398a8c512b7a946a73 Conflicts: compiler/dex/quick/arm64/target_arm64.cc compiler/image_test.cc runtime/fault_handler.cc
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90969af6deb19b1dbe356d62fe68d8f5698d3d8f |
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16-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Refactor GenSelect, refactor gen_common accordingly This adds a GenSelect method meant for selection of constants. The general-purpose GenInstanceof code is refactored to take advantage of this. This cleans up code and squashes a branch-over on ARM64 to a cset. Also add a slow-path for type initialization in GenInstanceof. Change-Id: Ie4494858bb8c26d386cf2e628172b81bba911ae5
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69dfe51b684dd9d510dbcb63295fe180f998efde |
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11-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Revert "Revert "Add implicit null and stack checks for x86"""" This reverts commit 0025a86411145eb7cd4971f9234fc21c7b4aced1. Bug: 16256184 Change-Id: Ie0760a0c293aa3b62e2885398a8c512b7a946a73
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9522af985466b2a05ef5cdede0808777dea7236e |
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15-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Squash a cmp w/ zero and b.ls to cbz (ARM/ARM64) In case of array bounds checks at constant index 0 we generate a compare and a branch. Squash into a cbz. Change-Id: I1c6a6e37a7a2356b2c4580a3387cedb55436e251
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48f5c47907654350ce30a8dfdda0e977f5d3d39f |
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27-Jun-2014 |
Hans Boehm <hboehm@google.com> |
Replace memory barriers to better reflect Java needs. Replaces barriers that enforce ordering of one access type (e.g. Load) with respect to another (e.g. store) with more general ones that better reflect both Java requirements and actual hardware barrier/fence instructions. The old code was inconsistent and unclear about which barriers implied which others. Sometimes multiple barriers were generated and then eliminated; sometimes it was assumed that certain barriers implied others. The new barriers closely parallel those in C++11, though, for now, we use something closer to the old naming. Bug: 14685856 Change-Id: Ie1c80afe3470057fc6f2b693a9831dfe83add831
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381f8acbfbad0f84e60b7ebe9fb9584536fb373f |
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10-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix GenSelect and GenFusedLongCmpBranch for ARM64 Depending on the result, we need to issue a wide csel. Also need to handle constants, and src and dest being the same. In GenFusedLongCmpBranch there is an ordering issue. If we swap the inputs, we did not Load the second one. Change-Id: Icb9876ca1288602d078b9fb89ea964ec2c910e0c
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39c8a99a3fdd9876980502ab12ed74a27e6be369 |
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12-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Add another special case to GenSelect for ARM64 This adds a special case for a select of two constants that have a difference of exactly one. Change-Id: I6e8bea791cb25af1b855d62e2333fd7fe6ac4e3a
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7c6c2ac4252ac31b42967e0f0233e8d32c5b5abe |
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01-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: easy division and remainder for long ints. Also adding test 701 to test easy division and remainder for int and long integers. Change-Id: I8212c84e4d9eb3e9f3f4f1f1c3418537bb13dc55
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873c371eea7d8700c8037d790de168b5ed7c20d0 |
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11-Jul-2014 |
Stuart Monteith <stuart.monteith@arm.com> |
ART: Fix GenSelect for ARM64 Add CSINV and replace CSNEG in GenSelect. Some tests were failing in 083-complier-regression as CSNEG was used instead of CSINV. CSNEG on xzr yields 0, whereas CSINV negates the bits and yields -1, which was the intention. Change-Id: I60557e34483f98310f7d33f18d8db203fba6e78f Signed-off-by: Stuart Monteith <stuart.monteith@arm.com>
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7fb36ded9cd5b1d254b63b3091f35c1e6471b90e |
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10-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Revert "Add implicit null and stack checks for x86"" Fixes x86_64 cross compile issue. Removes command line options and property to set implicit checks - this is hard coded now. This reverts commit 3d14eb620716e92c21c4d2c2d11a95be53319791. Change-Id: I5404473b5aaf1a9c68b7181f5952cb174d93a90d
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0025a86411145eb7cd4971f9234fc21c7b4aced1 |
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11-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Revert "Revert "Revert "Add implicit null and stack checks for x86""" Broke the build. This reverts commit 7fb36ded9cd5b1d254b63b3091f35c1e6471b90e. Change-Id: I9df0e7446ff0913a0e1276a558b2ccf6c8f4c949
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34e826ccc80dc1cf7c4c045de6b7f8360d504ccf |
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29-May-2014 |
Dave Allison <dallison@google.com> |
Add implicit null and stack checks for x86 This adds compiler and runtime changes for x86 implicit checks. 32 bit only. Both host and target are supported. By default, on the host, the implicit checks are null pointer and stack overflow. Suspend is implemented but not switched on. Change-Id: I88a609e98d6bf32f283eaa4e6ec8bbf8dc1df78a
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3d14eb620716e92c21c4d2c2d11a95be53319791 |
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10-Jul-2014 |
Dave Allison <dallison@google.com> |
Revert "Add implicit null and stack checks for x86" It breaks cross compilation with x86_64. This reverts commit 34e826ccc80dc1cf7c4c045de6b7f8360d504ccf. Change-Id: I34ba07821fc0a022fda33a7ae21850957bbec5e7
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63fe93d9f9d2956b1ee2b98cdd6ddd2153f5f9cf |
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30-Jun-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable Inlining. This patch fixes the remaining issues with inlining for ARM64. Change-Id: I2d85b7c4f3fb2b667bf6029fbc271ab954378889 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com> Signed-off-by: Matteo Franchin <matteo.franchin@arm.com>
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b5860fb459f1ed71f39d8a87b45bee6727d79fe8 |
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22-Jun-2014 |
buzbee <buzbee@google.com> |
Register promotion support for 64-bit targets Not sufficiently tested for 64-bit targets, but should be fairly close. A significant amount of refactoring could stil be done, (in later CLs). With this change we are not making any changes to the vmap scheme. As a result, it is a requirement that if a vreg is promoted to both a 32-bit view and the low half of a 64-bit view it must share the same physical register. We may change this restriction later on to allow for more flexibility for 32-bit Arm. For example, if v4, v5, v4/v5 and v5/v6 are all hot enough to promote, we'd end up with something like: v4 (as an int) -> r10 v4/v5 (as a long) -> r10 v5 (as an int) -> r11 v5/v6 (as a long) -> r11 Fix a couple of ARM64 bugs on the way... Change-Id: I6a152b9c164d9f1a053622266e165428045362f3
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255e014542b2180620230e4d9d6000ae06846bbd |
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04-Jul-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
Aarch64: fix references handling in Load*Indexed. Fix the way we handle references in Load/StoreBaseIndexed and friends. We assume references are 64-bit RegStorage entities, with the difference that they are load as 32-bit values. Change-Id: I7fe987ef9e97e9a5042b85378b33d1e85710d8b5
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23abec955e2e733999a1e2c30e4e384e46e5dde4 |
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02-Jul-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add few more inline functions This patch adds inlining support for the following functions: * Math.max/min(long, long) * Math.max/min(float, float) * Math.max/min(double, double) * Integer.reverse(int) * Long.reverse(long) Change-Id: Ia2b1619fd052358b3a0d23e5fcbfdb823d2029b9 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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4b537a851b686402513a7c4a4e60f5457bb8d7c1 |
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01-Jul-2014 |
Andreas Gampe <agampe@google.com> |
ART: Quick compiler: More size checks, add TargetReg variants Add variants for TargetReg for requesting specific register usage, e.g., wide and ref. More register size checks. With code adapted from https://android-review.googlesource.com/#/c/98605/. Change-Id: I852d3be509d4dcd242c7283da702a2a76357278d
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baa7c88a34fdfd230a2a383c2e388945f4d907b6 |
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30-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Rename A64_/A32_ register prefix to x/w. A64/A32 look like architecture name, but they are all for arm64. Use lower-case to name the registers defined in "ARM ARM" which can also be directly used in assembly file. Use upper-case to name the registers which are other aliases. Change-Id: I0ac38ed75f977fdc362288b01179b84feaee5614
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de68676b24f61a55adc0b22fe828f036a5925c41 |
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24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter" This reverts commit 2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d. Breaks the build. Change-Id: I9faad4e9a83b32f5f38b2ef95d6f9a33345efa33
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3c12c512faf6837844d5465b23b9410889e5eb11 |
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24-Jun-2014 |
Andreas Gampe <agampe@google.com> |
Revert "Revert "ART: Split out more cases of Load/StoreRef, volatile as parameter"" This reverts commit de68676b24f61a55adc0b22fe828f036a5925c41. Fixes an API comment, and differentiates between inserting and appending. Change-Id: I0e9a21bb1d25766e3cbd802d8b48633ae251a6bf
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2689fbad6b5ec1ae8f8c8791a80c6fd3cf24144d |
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23-Jun-2014 |
Andreas Gampe <agampe@google.com> |
ART: Split out more cases of Load/StoreRef, volatile as parameter Splits out more cases of ref registers being loaded or stored. For code clarity, adds volatile as a flag parameter instead of a separate method. On ARM64, continue cleanup. Add flags to print/fatal on size mismatches. Change-Id: I30ed88433a6b4ff5399aefffe44c14a5e6f4ca4e
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c61b3c984c509d5f7c8eb71b853c81a34b5c28ef |
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18-Jun-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: implement easy division and reminder. This implements easy division and reminder for integer only (32-bit). The optimisation applies to div/rem by powers of 2 and to div by small literals (between 3-15). Change-Id: I71be7c4de5d2e2e738b88984f13efb08f4388a19
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7c1c263f3227169e055200cc481c022f1cf37213 |
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17-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix OpCmpMemImmBranch. The temp register can be 64-bit in some cases(ArgReg or RefReg). Always compare 32-bit value no matter what the temp register is. Change-Id: Ib237dd081da0b5900b8c2418df1621d3245cb03d
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33ae5583bdd69847a7316ab38a8fa8ccd63093ef |
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12-Jun-2014 |
buzbee <buzbee@google.com> |
Arm64 hard-float Basic enabling of hard-float for Arm64. In future CLs we'll consolidate the various targets - there is a lot of overlap. Compilation remains turned off in this CL, but I expect to enable a subset shortly. With compilation fully enabled (including the EXPERIMENTAL opcodes with the exception of REM and THROW), we get the following run-test results: 003-omnibus-opcode failures: Classes.checkCast Classes.arrayInstance UnresTest2 Haven't gone deep, but these appear to be related to throw/catch and/or stacktrace. For REM, the generated code looks reasonable to me - my guess is that we've got something wrong on the transition to the runtime. Haven't looked deeper yet, though. The bulk of the other failure also appear to be related to transitioning to the runtime system, or handling try/catch. run-test status: Status with optimizations disabled, REM_FLOAT/DOUBLE and THROW disabled: succeeded tests: 94 failed tests: 22 failed: 003-omnibus-opcodes failed: 004-annotations failed: 009-instanceof2 failed: 024-illegal-access failed: 025-access-controller failed: 031-class-attributes failed: 044-proxy failed: 045-reflect-array failed: 046-reflect failed: 058-enum-order failed: 062-character-encodings failed: 063-process-manager failed: 064-field-access failed: 068-classloader failed: 071-dexfile failed: 083-compiler-regressions failed: 084-class-init failed: 086-null-super failed: 087-gc-after-link failed: 100-reflect2 failed: 107-int-math2 failed: 201-built-in-exception-detail-messages Change-Id: Ib66209285cad8998d77a14781de300af02a96b15
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e2eb29e98be3ba72cce7da40847ab3d605b9455d |
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12-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Enable MOVE_*, some CONST_*, CMP_*. With the fixes of GenArithImmOpLong, GenShiftOpLong, OpRegImm, OpRegRegImm, OpRegRegImm64, EncodeLogicalImmediate and fmov. Change-Id: I8cae4f921d5150a6b8e4803ca4dee553928d1a58
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169489b4f4be8c5dd880ba6f152948324d22ff79 |
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11-Jun-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Add support for inlined methods This patch adds support for Arm64 inlined methods. Change-Id: Ic6aeed6d2d32f65cd1e63cf482f83cdcf958798a
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8dea81ca9c0201ceaa88086b927a5838a06a3e69 |
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06-Jun-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite use/def masks to support 128 bits. Reduce LIR memory usage by holding masks by pointers in the LIR rather than directly and using pre-defined const masks for the common cases, allocating very few on the arena. Change-Id: I0f6d27ef6867acd157184c8c74f9612cebfe6c16
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511c8a653d5896e81428393a1c3d427da64e36f3 |
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03-Jun-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Fix cmp-long and method with long arguments. 1. Fix cmp-long. 2. Use single register to pass long argument. 3. Flush StackReference<ArtMethod> on arm64 the same as in common code. 3. Fix the mismatch in calculate reg offset. Change-Id: Ie2723260fb143512e4da6ee88d4f3aded80d3d5e
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a0cd2d701f29e0bc6275f1b13c0edfd4ec391879 |
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01-Jun-2014 |
buzbee <buzbee@google.com> |
Quick compiler: reference cleanup For 32-bit targets, object references are 32 bits wide both in Dalvik virtual registers and in core physical registers. Because of this, object references and non-floating point values were both handled as if they had the same register class (kCoreReg). However, for 64-bit systems, references are 32 bits in Dalvik vregs, but 64 bits in physical registers. Although the same underlying physical core registers will still be used for object reference and non-float values, different register class views will be used to represent them. For example, an object reference in arm64 might be held in x3 at some point, while the same underlying physical register, w3, would be used to hold a 32-bit int. This CL breaks apart the handling of object reference and non-float values to allow the proper register class (or register view) to be used. A new register class, kRefReg, is introduced which will map to a 32-bit core register on 32-bit targets, and 64-bit core registers on 64-bit targets. From this point on, object references should be allocated registers in the kRefReg class rather than kCoreReg. Change-Id: I6166827daa8a0ea3af326940d56a6a14874f5810
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ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
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03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE Merge ART from AOSP to lmp-preview-dev. Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
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05e27ff942b42e123ea9519d13d31070ab96f0ac |
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28-May-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable extended MIR This patch enables all the extended MIR opcodes for ARM64. Please note that currently the compiler will never generate these opcodes since the BB optimisations are not enabled. Change-Id: Ia712b071f62301db868297d37567795128b5bf2e Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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48241e786121e1c4c050d9cfad3d22de270a3e75 |
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23-May-2014 |
Zheng Xu <zheng.xu@arm.com> |
AArch64: Add suspend check in managed code. TODO: Remove x19 in the frame in runtime, generic jni, compiled jni. Change-Id: Ibdc292c9e7adb3a5d3eff353c22f60ffc101f549
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ed65c5e982705defdb597d94d1aa3f2997239c9b |
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22-May-2014 |
Serban Constantinescu <serban.constantinescu@arm.com> |
AArch64: Enable LONG_* and INT_* opcodes. This patch fixes some of the issues with LONG and INT opcodes. The patch has been tested and passes all the dalvik tests except for 018 and 107. Change-Id: Idd1923ed935ee8236ab0c7e5fa969eaefeea8708 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
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bc6d197cdb02eeac0c98ec4ed37f530b003a4e7a |
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13-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: fixes in A64 code generation. - Disabled special method compilation, as it requires hard-float ABI, - Disabled suspend checks, as runtime is not yet ready (e.g. trampolines are not setting the suspend register, etc), - Changing definition of zero register (the zero register has now 0x3f as its register number), - Fixing some issues with handling of cmp instructions in the assembler: we now use the shift-register rather than the extended-register variant of cmp and cmn, - Partially fixing register setup (register sN is now mapped to dN), - Fixing and completing implementation of register spills/unspills, - Fixing LoadBaseDispBody() and StoreBaseDispBody(). Change-Id: Ia49ba48b6ca0f782380066345b7a198cb6c1dc1d
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b14329f90f725af0f67c45dfcb94933a426d63ce |
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15-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Fix MonitorExit code on ARM We do not emit barriers on non-SMP systems. But on ARM, we have places that need to conditionally execute, which is done through an IT instruction. The guide of said instruction thus changes between SMP and non-SMP systems. To cleanly approach this, change the API so that GenMemBarrier returns whether it generated an instruction. ARM will have to query the result and update any dependent IT. Throw a build system error if TARGET_CPU_SMP is not set. Fix runtime/Android.mk to work with new multilib host. Bug: 14989275 Change-Id: I9e611b770e8a1cd4ca19367d7dae0573ec08dc61
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2f244e9faccfcca68af3c5484c397a01a1c3a342 |
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08-May-2014 |
Andreas Gampe <agampe@google.com> |
ART: Add more ThreadOffset in Mir2Lir and backends This duplicates all methods with ThreadOffset parameters, so that both ThreadOffset<4> and ThreadOffset<8> can be handled. Dynamic checks against the compilation unit's instruction set determine which pointer size to use and therefore which methods to call. Methods with unsupported pointer sizes should fatally fail, as this indicates an issue during method selection. Change-Id: Ifdb445b3732d3dc5e6a220db57374a55e91e1bf6
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e45fb9e7976c8462b94a58ad60b006b0eacec49f |
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06-May-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Change arm64 backend to produce A64 code. The arm backend clone is changed to produce A64 code. At the moment this backend can only compile simple methods (both leaf and non-leaf). Most of the work on the assembler (assembler_arm64.cc) has been done. Some work on the LIR generation layer (functions such as OpRegRegImm & friends) is still necessary. The register allocator still needs to be adapted to the A64 instruction set (it is mostly unchanged from the arm backend). Offsets for helpers in gen_invoke.cc still need to be changed to work on 64-bit. Change-Id: I388f99eeb832857981c7d9d5cb5b71af64a4b921
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455759b5702b9435b91d1b4dada22c4cce7cae3c |
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06-May-2014 |
Vladimir Marko <vmarko@google.com> |
Remove LoadBaseDispWide and StoreBaseDispWide. Just pass k64 or kDouble to non-wide versions. Change-Id: I000619c3b78d3a71db42edc747c8a0ba1ee229be
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43ec8737d8356dbff0a90bee521fb0e73438da47 |
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31-Mar-2014 |
Matteo Franchin <matteo.franchin@arm.com> |
AArch64: Added arm64 quick backend as an arm clone. Created a new directory arm64 under compiler/dex/quick which contains a copy of the 32-bit arm backend. In following CLs, this code will be replaced/modified to support Aarch64. Change-Id: I06c468db8d588e339eecf4d7d85276d5e334a17a
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