| e50383288a75244255d3ecedcc79ffe9caf774cb |
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04-Jul-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Support fields in optimizing compiler.
- Required support for temporaries, to be only used by baseline compiler.
- Also fixed a few invalid assumptions around locations and instructions
that don't need materialization. These instructions should not have an Out.
Change-Id: Idc4a30dd95dd18015137300d36bec55fc024cf62
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| 31d76b42ef5165351499da3f8ee0ac147428c5ed |
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09-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Plug code generator into liveness analysis.
Also implement spill slot support.
Change-Id: If5e28811e9fbbf3842a258772c633318a2f4fafc
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| ec7e4727e99aa1416398ac5a684f5024817a25c7 |
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06-Jun-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Fix some bugs in graph construction/simplification methods.
Also fix a brano during SSA construction. The code should
not have been commented out. Added a test to cover what the code
intends.
Change-Id: Ia00ae79dcf75eb0d412f07649d73e7f94dbfb6f0
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| ffddfdf6fec0b9d98a692e27242eecb15af5ead2 |
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03-Jun-2014 |
Tim Murray <timmurray@google.com> |
DO NOT MERGE
Merge ART from AOSP to lmp-preview-dev.
Change-Id: I0f578733a4b8756fd780d4a052ad69b746f687a9
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| a7062e05e6048c7f817d784a5b94e3122e25b1ec |
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22-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a linear scan register allocator to the optimizing compiler.
This is a "by-the-book" implementation. It currently only deals
with allocating registers, with no hint optimizations.
The changes remaining to make it functional are:
- Allocate spill slots.
- Resolution and placements of Move instructions.
- Connect it to the code generator.
Change-Id: Ie0b2f6ba1b98da85425be721ce4afecd6b4012a4
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| a5b8fde2d2bc3167078694fad417fddfe442a6fd |
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23-May-2014 |
Vladimir Marko <vmarko@google.com> |
Rewrite BitVector index iterator.
The BitVector::Iterator was not iterating over the bits but
rather over indexes of the set bits. Therefore, we rename it
to IndexIterator and provide a BitVector::Indexes() to get
a container-style interface with begin() and end() for range
based for loops.
Also, simplify InsertPhiNodes where the tmp_blocks isn't
needed since the phi_nodes and input_blocks cannot lose any
blocks in subsequent iterations, so we can do the Union()
directly in those bit vectors and we need to repeat the loop
only if we have new input_blocks, rather than on phi_nodes
change. And move the temporary bit vectors to scoped arena.
Change-Id: I6cb87a2f60724eeef67c6aaa34b36ed5acde6d43
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| ddb311fdeca82ca628fed694c4702f463b5c4927 |
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16-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Build live ranges in preparation for register allocation.
Change-Id: I7ae24afaa4e49276136bf34f4ba7d62db7f28c01
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| 0d3f578909d0d1ea072ca68d78301b6fb7a44451 |
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14-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Linearize the graph before creating live ranges.
Change-Id: I02eb5671e3304ab062286131745c1366448aff58
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| f635e63318447ca04731b265a86a573c9ed1737c |
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14-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add a compilation tracing mechanism to the new compiler.
Code mostly imported from: https://android-review.googlesource.com/#/c/81653/.
Change-Id: I150fe942be0fb270e03fabb19032180f7a065d13
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| 622d9c31febd950255b36a48b47e1f630197c5fe |
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12-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Add loop recognition and CFG simplifications in new compiler.
We do three simplifications:
- Split critical edges, for code generation from SSA (new).
- Ensure one back edge per loop, to simplify loop recognition (new).
- Ensure only one pre header for a loop, to simplify SSA creation (existing).
Change-Id: I9bfccd4b236a00486a261078627b091c8a68be33
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| 804d09372cc3d80d537da1489da4a45e0e19aa5d |
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02-May-2014 |
Nicolas Geoffray <ngeoffray@google.com> |
Build live-in, live-out and kill sets for each block.
This information will be used when computing live ranges of
instructions.
Change-Id: I345ee833c1ccb4a8e725c7976453f6d58d350d74
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