c86950cb3f50ead0c9a9d0366b870d6c6e1b91c8 |
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15-Jul-2014 |
Duane Sand <duane.sand@imgtec.com> |
[MIPSR6] setjmp supports mips32r6 and FP64A/FPXX reg models Save and restore floating point registers via 64-bit load/stores when possible. Use assembler's builtin macro ops to generate pairs of 32-bit load/stores on Mips I cpus. Some cpus or FR modes have only 16 even-numbered dp fp regs. This is exposed by _MIPS_FPSET, defined by existing compilers. (cherry picked from commit dd37251c473e1483faba0fd5aaf30e7a55582e8a) Change-Id: Ibd43653701a363a77af85121d3cbd229d132a06a
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851e68a2402fa414544e66650e09dfdaac813e51 |
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20-Feb-2014 |
Elliott Hughes <enh@google.com> |
Unify our assembler macros. Our <machine/asm.h> files were modified from upstream, to the extent that no architecture was actually using the upstream ENTRY or END macros, assuming that architecture even had such a macro upstream. This patch moves everyone to the same macros, with just a few tweaks remaining in the <machine/asm.h> files, which no one should now use directly. I've removed most of the unused cruft from the <machine/asm.h> files, though there's still rather a lot in the mips/mips64 ones. Bug: 12229603 Change-Id: I2fff287dc571ac1087abe9070362fb9420d85d6d
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645d0312c2d6b6492cc4b3891bc1a91908dc24b7 |
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06-Feb-2014 |
Chris Dearman <chris.dearman@imgtec.com> |
[MIPS64] libc/libm support libc/libm support for MIPS64 targets Change-Id: I8271941d418612a286be55495f0e95822f90004f Signed-off-by: Chris Dearman <chris.dearman@imgtec.com> Signed-off-by: Raghu Gandham <raghu.gandham@imgtec.com>
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