| fe47bf8fa07e12b70ff8b234fa1f6b97c8d2753d |
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17-Jul-2013 |
Hal Finkel <hfinkel@anl.gov> |
PPC: Implement base pointer and stack realignment
This builds on some frame-lowering code that has existed since 2005 (r24224)
but was disabled in 2008 (r48188) because it needed base pointer support to
function correctly. This implementation follows the strategy suggested by Dale
Johannesen in r48188 where the following comment was added:
This does not currently work, because the delta between old and new stack
pointers is added to offsets that reference incoming parameters after the
prolog is generated, and the code that does that doesn't handle a variable
delta. You don't want to do that anyway; a better approach is to reserve
another register that retains to the incoming stack pointer, and reference
parameters relative to that.
And now we do exactly that. If we don't need a frame pointer, then we use r31
as a base pointer. If we do need a frame pointer, then we use r30 as a base
pointer. The base pointer retains the value of the stack pointer before it was
decremented in the prologue. We then use the base pointer to resolve all
negative frame indicies. The basic scheme follows that for base pointers in the
X86 backend.
We use a base pointer when we need to dynamically realign the incoming stack
pointer. This currently applies only to static objects (dynamic allocas with
large alignments, and base-pointer support in SjLj lowering will come in future
commits).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186478 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| a0ec3f9b7b826b9b40b80199923b664bad808cce |
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14-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Use SmallVectorImpl& instead of SmallVector to avoid repeating small vector size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186274 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| fb6fe0aea2d1adde6d5e86f43797b5795ff2dc36 |
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15-Apr-2013 |
Hal Finkel <hfinkel@anl.gov> |
Fix PPC64 CR spill location for callee-saved registers
This fixes an ABI bug for non-Darwin PPC64. For the callee-saved condition
registers, the spill location is specified relative to the stack pointer (SP +
8). However, this is not relative to the SP after the new stack frame is
established, but instead relative to the caller's stack pointer (it is stored
into the linkage area of the parent's stack frame).
So, like with the link register, we don't directly spill the CRs with other
callee-saved registers, but just mark them to be spilled during prologue
generation.
In practice, this reverts r179457 for PPC64 (but leaves it in place for PPC32).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179500 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 3f2c047f32c9b488d9c49bb2dc87b979530dab3f |
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23-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Note in PPCFunctionInfo VRSAVE spills
In preparation for using the new register scavenger capability for providing
more than one register simultaneously, specifically note functions that have
spilled VRSAVE (currently, this can happen only in functions that use the
setjmp intrinsic). As with CR spilling, such functions will need to provide two
emergency spill slots to the scavenger.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177832 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 324972904353594ad4a0cdfc79370f85e9fb9c8f |
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17-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Improve PPC VR (Altivec) register spilling
This change cleans up two issues with Altivec register spilling:
1. The spilling code was inefficient (using two instructions, and add and a
load, when just one would do)
2. The code assumed that r0 would always be available (true for now, but this
will change)
The new code handles VR spilling just like GPR spills but forced into r+r mode.
As a result, when any VR spills are present, we must now always allocate the
register-scavenger spill slot.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177231 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 0cfb42adb5072fb19a01dba3ea58a33fd5927947 |
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15-Mar-2013 |
Hal Finkel <hfinkel@anl.gov> |
Allocate the RS spill slot for any PPC function with spills and a large stack frame
For spills into a large stack frame, the FI-elimination code uses the register
scavenger to obtain a free GPR for use with an r+r-addressed load or store.
When there are no available GPRs, the scavenger gets one by using its spill
slot. Previously, we were not always allocating that spill slot and the RS
would assert when the spill slot was needed.
I don't currently have a small test that triggered the assert, but I've
created a small regression test that verifies that the spill slot is now
added when the stack frame is sufficiently large.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 4edd84da1b3f7fd73e96a13b6b7e183ad04ac7c4 |
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24-Feb-2013 |
Bill Schmidt <wschmidt@linux.vnet.ibm.com> |
Fix PR14364.
This removes a const_cast hack from PPCRegisterInfo::hasReservedSpillSlot().
The proper place to save the frame index for the CR spill slot is in the
PPCFunctionInfo object, not the PPCRegisterInfo object.
No new test cases, as this just reimplements existing function. Existing
tests such as test/CodeGen/PowerPC/crsave.ll are sufficient.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175998 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 2d24e2a396a1d211baaeedf32148a3b657240170 |
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20-Dec-2011 |
David Blaikie <dblaikie@gmail.com> |
Unweaken vtables as per http://llvm.org/docs/CodingStandards.html#ll_virtual_anch
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146960 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 1e93df6f0b5ee6e36d7ec18e6035f0f5a53e5ec6 |
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17-Apr-2010 |
Dan Gohman <gohman@apple.com> |
Move per-function state out of TargetLowering subclasses and into
MachineFunctionInfo subclasses.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@101634 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 2392efef1bd2599231ab659dd6ba4233bf5df94c |
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06-Jun-2009 |
Dan Gohman <gohman@apple.com> |
Add explicit keywords.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@72969 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| c12e5812be4dacc30781db84b045775c46580240 |
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24-Oct-2008 |
Dale Johannesen <dalej@apple.com> |
Rewrite logic to figure out whether LR needs to
be saved/restored in the prolog/epilog. We need
to do this iff something in the function stores
into it.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@58116 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 30e62c098b5841259f8026df1c5c45c7c1182a38 |
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30-Apr-2008 |
Arnold Schwaighofer <arnold.schwaighofer@gmail.com> |
Tail call optimization improvements:
Move platform independent code (lowering of possibly overwritten
arguments, check for tail call optimization eligibility) from
target X86ISelectionLowering.cpp to TargetLowering.h and
SelectionDAGISel.cpp.
Initial PowerPC tail call implementation:
Support ppc32 implemented and tested (passes my tests and
test-suite llvm-test).
Support ppc64 implemented and half tested (passes my tests).
On ppc tail call optimization is performed if
caller and callee are fastcc
call is a tail call (in tail call position, call followed by ret)
no variable argument lists or byval arguments
option -tailcallopt is enabled
Supported:
* non pic tail calls on linux/darwin
* module-local tail calls on linux(PIC/GOT)/darwin(PIC)
* inter-module tail calls on darwin(PIC)
If constraints are not met a normal call will be emitted.
A test checking the argument lowering behaviour on x86-64 was added.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@50477 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 7194aaf738a1b89441635340403f1c5b06ae18ef |
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03-Mar-2008 |
Bill Wendling <isanbard@gmail.com> |
This is the initial check-in for adding register scavenging to PPC. (Currently,
PPC-64 doesn't work.) This also lowers the spilling of the CR registers so that
it uses a register other than the default R0 register (the scavenger scrounges
for one). A significant part of this patch fixes how kill information is
handled.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@47863 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 4ee451de366474b9c228b4e5fa573795a715216d |
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29-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
Remove attribution from file headers, per discussion on llvmdev.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45418 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 3fc027df4fca0355717515abb4d6e3753e6dee2a |
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08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
implement __builtin_return_addr(0) on ppc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44700 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 73944fb22270697e75408cba52cca276be371a1f |
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08-Dec-2007 |
Chris Lattner <sabre@nondot.org> |
refactor some code to avoid overloading the name 'usesLR' in
different places to mean different things. Document what the
one in PPCFunctionInfo means and when it is valid.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@44699 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| d313a9b1484c52e3f784de5064ce86bdbd9b26dc |
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27-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Duplicate use of LR, take 2.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34666 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 3d3d6275134f3c6d35a97a028a8556fd2e62243a |
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27-Feb-2007 |
Evan Cheng <evan.cheng@apple.com> |
Backing out Jim's LR spill changes. This was causing llvm-gcc bootstrapping
to infinite loop:
PPCMachineFunctionInfo.h updated: 1.2 -> 1.3
PPCRegisterInfo.cpp updated: 1.110 -> 1.111
PPCRegisterInfo.h updated: 1.28 -> 1.29
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34652 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 2a27a7598b90359696e31cb665914206f369d1f0 |
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23-Feb-2007 |
Jim Laskey <jlaskey@mac.com> |
Don't spill LR as a callee saved register.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34533 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 24652d16f84e4fd605aaffdd5112a606be6c8074 |
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25-Nov-2006 |
Reid Spencer <rspencer@reidspencer.com> |
Add newline at end of file.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31902 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
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| 2f616bff7ef1e2e08d6d23c2a8b42ec2bfebb173 |
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16-Nov-2006 |
Jim Laskey <jlaskey@mac.com> |
This is a general clean up of the PowerPC ABI. Address several problems and
bugs including making sure that the TOS links back to the previous frame,
that the maximum call frame size is not included twice when using frame
pointers, no longer growing the frame on calls, double storing of SP and
a cleaner/faster dynamic alloca.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@31792 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/PowerPC/PPCMachineFunctionInfo.h
|