| cd81d94322a39503e4a3e87b6ee03d4fcb3465fb |
|
21-Jul-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for rebase to r212749.
Includes a cherry-pick of:
r212948 - fixes a small issue with atomic calls
Change-Id: Ib97bd980b59f18142a69506400911a6009d9df18
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| dce4a407a24b04eebc6a376f8e62b41aaa7b071f |
|
29-May-2014 |
Stephen Hines <srhines@google.com> |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 36b56886974eae4f9c5ebc96befd3e7bfe5de338 |
|
24-Apr-2014 |
Stephen Hines <srhines@google.com> |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 3560dd2dcd67d42eeb8e59975581d598d71669df |
|
18-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
R600/SI: Fix moveToVALU when the first operand is VSrc.
Moving into a VSrc doesn't always work, since it could be
replaced with an SGPR later.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195042 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 9bc4b2c0dae143e72624984dfd5e3a4ff2e95eb2 |
|
18-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
R600/SI: Fix multiple SGPR reads when using VCC.
No other SGPR operands are allowed, so if VCC is
used, move the other to a VGPR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195041 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 3e38856f04a01651819c6bc16fac4434a5d2b4c6 |
|
18-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
R600/SI: Move patterns to match add / sub to scalar instructions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195034 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
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| 836c5133c66edecedeaa79448964b4c103f99271 |
|
18-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
R600/SI: Fix extra defs of VCC / SCC.
When replacing scalar operations with vector,
the wrong implicit output register was used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@195033 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| c3ec7e2273a26d8ae3b8d98160e13f8f44299ad2 |
|
15-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Make method static
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194858 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
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| 29a651af8a4b522daf1f9102c93e4c8ecc2ef3c2 |
|
14-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Indentation fixes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194688 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
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| 54f009f5a427c640266d223826eed851a8a340c3 |
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14-Nov-2013 |
Matt Arsenault <Matthew.Arsenault@amd.com> |
Add a comment
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194684 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
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| 7c94599d1b34fbe3a3857edf41946dc62f9cfba2 |
|
14-Nov-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Fix uninitialized variable usage
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194632 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| a2b4eb6d15a13de257319ac6231b5ab622cd02b1 |
|
14-Nov-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Add support for private address space load/store
Private address space is emulated using the register file with
MOVRELS and MOVRELD instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| b52bf6a3b31596a309f4b12884522e9b4a344654 |
|
14-Nov-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Prefer SALU instructions for bit shift operations
All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.
This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.
This patch includes some fixes from Matt Arsenault.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 661bd3df7518a3d984dada66473602a0401618ba |
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28-Oct-2013 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/R600: Un-tab-ify.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193510 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| e18273b7be11878999a2ee199d0b1ec468474c9c |
|
22-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Use llvm_unreachable() for an always false assert
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193183 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 47a7c382fdc6292a1d9fb45139d742e0a706a93d |
|
22-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Fix warning on non-asserts build
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193180 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 04c559569f87d755c3f2828a765f5eb7308e6753 |
|
22-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Simplify handling of private address space
The AMDGPUIndirectAddressing pass was previously responsible for
lowering private loads and stores to indirect addressing instructions.
However, this pass was buggy and way too complicated. The only
advantage it had over the new simplified code was that it saved one
instruction per direct write to private memory. This optimization
likely has a minimal impact on performance, and we may be able
to duplicate it using some other transformation.
For the private address space, we now:
1. Lower private loads/store to Register(Load|Store) instructions
2. Reserve part of the register file as 'private memory'
3. After regalloc lower the Register(Load|Store) instructions to
MOV instructions that use indirect addressing.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193179 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 34adeaf8b9e82e68d1dc8de916a307143ddd290c |
|
22-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Remove unused InstrInfo::getMovImmInstr() function
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193178 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 484091a50aa27dbf8d7483352b7f311def5d6036 |
|
16-Oct-2013 |
Vincent Lejeune <vljn@ovi.com> |
R600/SI: Remove some leftover MI dump call
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192743 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 47fbbc2dc5696d27f4e3c8a5432777976dd8da0a |
|
10-Oct-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Implement SIInstrInfo::verifyInstruction() for VOP*
The function is used by the machine verifier and checks that VOP*
instructions have legal operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192367 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 1edd1a336a79c4cb804d32cb492738549154c69c |
|
18-Aug-2013 |
Dmitri Gribenko <gribozavr@gmail.com> |
Remove unused stdio.h includes
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188626 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| ebd4eec5386e946dc80f4d80e803125af55c2a68 |
|
16-Aug-2013 |
Michel Danzer <michel.daenzer@amd.com> |
R600/SI: Fix broken encoding of DS_WRITE_B32
The logic in SIInsertWaits::getHwCounts() only really made sense for SMRD
instructions, and trying to shoehorn it into handling DS_WRITE_B32 caused
it to corrupt the encoding of that by clobbering the first operand with
the second one.
Undo that damage and only apply the SMRD logic to that.
Fixes some derivates related piglit regressions with radeonsi.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188558 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| df4626ef15ba0eb5f571a3ee6314e5c388258927 |
|
15-Aug-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Assign a register class to the $vaddr operand for MIMG instructions
The previous code declared the operand as unknown:$vaddr, which made
it possible for scalar registers to be used instead of vector registers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188425 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 787e71df693e94cc512f3e439bf91609a8ec9bae |
|
15-Jul-2013 |
Craig Topper <craig.topper@gmail.com> |
Make some arrays 'static const'
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186307 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| b5632b5b456db647b42239cbd4d8b58c82290c4e |
|
07-Jun-2013 |
Bill Wendling <isanbard@gmail.com> |
Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change.
No functionality change intended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183561 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 4d0e8a8a3e2e5b98f598acad4d57452b99d52e74 |
|
10-Apr-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: dynamical figure out the reg class of MIMG
Depending on the number of bits set in the writemask.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179166 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| e49230895d9c666b84beaa748259fbf1f6715122 |
|
27-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add cummuting of rev instructions
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178127 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 3851e9869f8da4bf0a733bdd0510bd6579d00b09 |
|
26-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: improve vector interpolation
Prevent loading M0 multiple times.
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178023 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 66501123d1b7b0395a9de091bf72b2cd42a04dc6 |
|
01-Mar-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: handle all registers in copyPhysReg v2
v2: based on Michels patch, but now allows copying of all registers sizes.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176346 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| b3d1eaded7d7a874bbda2b0d322df7389c724bfc |
|
26-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: add some more instruction flags
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176102 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| e25e490793241e471036c3e2f969ce6a068e5ce1 |
|
16-Feb-2013 |
Christian Konig <christian.koenig@amd.com> |
R600/SI: cleanup literal handling v3
Seems to be allot simpler, and also paves the
way for further improvements.
v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
use VGPR0 in dummy EXP, avoid compiler warning, break
after encoding the first literal.
v3: correctly use V_ADD_F32_e64
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175354 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 60fc58262f4dba20c1ea5ede63e5a2c322489d32 |
|
07-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600/SI: Handle VGPR64 destination in copyPhysReg().
Allows nexuiz to run with radeonsi.
Patch by: Michel Dänzer
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174655 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| c0b0c677a1138f0a5ce1435fc1e70cef38fd95c8 |
|
06-Feb-2013 |
Tom Stellard <thomas.stellard@amd.com> |
R600: Support for indirect addressing v4
Only implemented for R600 so far. SI is missing implementations of a
few callbacks used by the Indirect Addressing pass and needs code to
handle frame indices.
At the moment R600 only supports array sizes of 16 dwords or less.
Register packing of vector types is currently disabled, which means that a
vec4 is stored in T0_X, T1_X, T2_X, T3_X, rather than T0_XYZW. In order
to correctly pack registers in all cases, we will need to implement an
analysis pass for R600 that determines the correct vector width for each
array.
v2:
- Add support for i8 zext load from stack.
- Coding style fixes
v3:
- Don't reserve registers for indirect addressing when it isn't
being used.
- Fix bug caused by LLVM limiting the number of SubRegIndex
declarations.
v4:
- Fix 64-bit defines
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@174525 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 58a2cbef4aac9ee7d530dfb690c78d6fc11a2371 |
|
02-Jan-2013 |
Chandler Carruth <chandlerc@gmail.com> |
Resort the #include lines in include/... and lib/... with the
utils/sort_includes.py script.
Most of these are updating the new R600 target and fixing up a few
regressions that have creeped in since the last time I sorted the
includes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@171362 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| 6b207d3cfa6b7be87ebde25c6c002f776f3d1595 |
|
20-Dec-2012 |
NAKAMURA Takumi <geek4civic@gmail.com> |
Target/R600: Update MIB according to r170588.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170620 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|
| f98f2ce29e6e2996fa58f38979143eceaa818335 |
|
11-Dec-2012 |
Tom Stellard <thomas.stellard@amd.com> |
Add R600 backend
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@169915 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/lib/Target/R600/SIInstrInfo.cpp
|