| 1b91231347c00bf1be46bdd5b27ae8c45fdc0d0c |
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08-Nov-2013 |
Artyom Skrobov <Artyom.Skrobov@arm.com> |
[ARM] In ARMAsmParser, MatchCoprocessorOperandName() permitted p10 and p11 as operands for coprocessor instructions, resulting in encodings that clash with FP/NEON instruction encodings
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194253 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-only-conditionals.s
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| c19bd321362166805194cbaf170e06a4790d2da9 |
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26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: fix more cases where predication may or may not be allowed
Unfortunately this addresses two issues (by the time I'd disentangled the logic
it wasn't worth putting it back to half-broken):
+ Coprocessor instructions should all be predicable in Thumb mode.
+ BKPT should never be predicable.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184965 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-only-conditionals.s
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| c1a91dd97b000128189421eda6c5bb7905b1f467 |
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26-Jun-2013 |
Tim Northover <tnorthover@apple.com> |
ARM: allow predicated barriers in Thumb mode
The barrier instructions are only "always-execute" in ARM mode, they can quite
happily sit inside an IT block in Thumb.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@184964 91177308-0d34-0410-b5e6-96231b3b80d8
/external/llvm/test/MC/ARM/thumb-only-conditionals.s
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