| cc44aa77490e1360b099eb0b887266f434298b4f |
|
21-Jul-2012 |
Eric Anholt <eric@anholt.net> |
i965: Remove unused param conversion code.
Ever since ctx->NativeIntegers was set, the conversion flag has been
PARAM_NO_CONVERT.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 6a26005c1e298ec205c339b1b53b3dff6e1fd03c |
|
08-Jan-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965: Correct misspellings of "invariant".
$ dict invarient
No definitions found for "invarient", perhaps you mean:
gcide: Invariant
wn: invariant
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
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| a9e97d022cb68266639eb54947517454c8ffe45e |
|
05-Aug-2011 |
Eric Anholt <eric@anholt.net> |
intel: Fix warnings from gl_constant_parameter changes.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 16f8c823898fd71a3545457eacd2dc31ddeb3592 |
|
11-Nov-2010 |
Eric Anholt <eric@anholt.net> |
i965: Move payload reg setup to compile, not lookup time.
Payload reg setup on gen6 depends more on the dispatch width as well
as the uses_depth, computes_depth, and other flags. That's something
we want to decide at compile time, not at cache lookup. As a bonus,
the fragment shader program cache lookup should be cheaper now that
there's less to compute for the hash key.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| bb1540835056cdea5db6f55b19c0c87358f14cd1 |
|
03-Nov-2010 |
Eric Anholt <eric@anholt.net> |
intel: Annotate debug printout checks with unlikely().
This provides the optimizer with hints about code hotness, which we're
quite certain about for debug printouts (or, rather, while we
developers often hit the checks for debug printouts, we don't care
about performance while doing so).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 9e3641bd0d739a87a6998300ca29580cb557f380 |
|
25-Oct-2010 |
Eric Anholt <eric@anholt.net> |
i965: Make FS uniforms be the actual type of the uniform at upload time.
This fixes some insanity that would otherwise be required for GLSL
1.30 bit ops or gen6 integer uniform operations in general, at the
cost of upload-time pain. Given that we only have that pain because
mesa's mangling our integer uniforms to be floats, this something that
should be fixed outside of the shader codegen.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 501c9dc62774a73c080d500a1eab773b0da9577e |
|
17-Aug-2010 |
Eric Anholt <eric@anholt.net> |
i965: Rename nr_depth_regs to nr_payload_regs.
Only 8 out of the up to 13 regs are for source/dest depth, so the name
wasn't particularly appropriate. Note that this doesn't count the
constant or URB payload regs. Also, don't pre-divide by 2, so it's
actually a number of registers.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
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| ec2b92f98c2e7f161521b447cc1d9a36bce3707c |
|
11-Jun-2010 |
Brian Paul <brianp@vmware.com> |
mesa: rename src/mesa/shader/ to src/mesa/program/
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 298be2b028263b2c343a707662c6fbfa18293cb2 |
|
19-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Replace the _mesa_*printf() wrappers with the plain libc versions
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| c5413839b3e99c7b162f1260142f3c175502b0ce |
|
11-Nov-2009 |
Eric Anholt <eric@anholt.net> |
i965: avoid memsetting all the BRW_WM_MAX_INSN arrays for every compile.
For an app that's blowing out the state cache, like sauerbraten, the
memset of the giant arrays ended up taking 11% of the CPU even when only a
"few" of the entries got used. With this, the WM program compile drops back
down to 1% of CPU time.
Bug #24981 (bisected to BRW_WM_MAX_INSN increase).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
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| a8d233e509a2c1aada7cd4e83b126ba06cb90565 |
|
29-Oct-2009 |
Brian Paul <brianp@vmware.com> |
i965: use macros to get/set prog_instruction::Aux field
This makes things a bit easier to remember/understand.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 536476f2432168fb15ac06b52c953a594ad851ad |
|
12-Aug-2009 |
Eric Anholt <eric@anholt.net> |
i965: Handle scalar result swizzling in shared GLSL/non-GLSL code.
This is preparation for merging of brw_wm_glsl.c and
brw_wm_emit.c, and glsl.c doesn't swizzle channel results around.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 7db7ff878d3e5a6b345228e6eaee4797bb68b360 |
|
15-Apr-2009 |
Brian Paul <brianp@vmware.com> |
mesa: merge the prog_src_register::NegateBase and NegateAbs fields
There's really no need for two negation fields. This came from the
GL_NV_fragment_program extension. The new, unified Negate bitfield applies
after the absolute value step.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 8ae7e7749b708fc5a46180d3de2503ba7e2ab1f3 |
|
24-Feb-2009 |
Brian Paul <brianp@vmware.com> |
mesa: replace old prog_instruction::Sampler field with Aux field
The i965 driver needs an extra instruction field for color output information.
It was using the Sampler field for this. Use the Aux field instead. This
will probaby be revisited at some point...
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| e0d907308150b4863cc4f24543e70e14207e966a |
|
20-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: use the new prog_instruction::TexShadow field
GLSL shadow() sampler calls are properly propogated down to the driver now.
The glean glsl1 shadow() tests work (except for the alpha channel).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 97937e0ac8d5f46722af98ca40fba3f7a989d97d |
|
13-Feb-2009 |
Brian Paul <brianp@vmware.com> |
i965: the return value of translate_insn() is never used. Make it void.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| faa48915d27634a12f123eaa6e954ec79565e365 |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: fix bug in pass0_precalc_mov()
Previously, "in-place" swizzles such as:
MOV t, t.xxyx;
were handled incorrectly. Fixed by splitting the one loop into two loops so we
get all the refs before assigning them (to avoid potential clobbering).
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 2ace634024dc14ab15087f3718f8f84e23fba47c |
|
28-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: minor comment additions/edits
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| af0e6336e9d7dc19d74950ce13b33e1fa1b2081d |
|
17-Jan-2009 |
Brian Paul <brianp@vmware.com> |
i965: whitespace changes and reformatting
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| fcb7cb9e72ecac7c165a3a6ed7a033e2e6793a26 |
|
13-Mar-2008 |
Zou Nan hai <nanhai.zou@intel.com> |
[i965] multiple rendering target support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 35707dbe57873adb5a8088cd47c13bd216e143e4 |
|
12-Apr-2007 |
Zou Nan hai <nanhai.zou@intel.com> |
Initial 965 GLSL support
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 064ae479a770bf434958d673baf6f7530f642697 |
|
23-Feb-2007 |
Brian <brian@yutani.localnet.net> |
Update DRI drivers for new glsl compiler.
Mostly:
- update #includes
- update STATE_* token code
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|
| 9f344b3e7d6e23674dd4747faec253f103563b36 |
|
09-Aug-2006 |
Eric Anholt <anholt@FreeBSD.org> |
Add Intel i965G/Q DRI driver.
This driver comes from Tungsten Graphics, with a few further modifications by
Intel.
/external/mesa3d/src/mesa/drivers/dri/i965/brw_wm_pass0.c
|