| 006c1a3c652803e2ff8d5f7ea55c9cb5d8353279 |
|
07-Aug-2012 |
Eric Anholt <eric@anholt.net> |
i965: Add perf debug for stalls during shader compiles.
v2: fix bad comment from before I gave up and decided to just use doubles.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| bce58e155db7202a98642c10e6132dee4e08162b |
|
04-Jul-2012 |
Eric Anholt <eric@anholt.net> |
intel: Convert to using private depth/stencil buffers (v2)
This means that GLX buffer sharing of these no longer works. On the
other hand, just *look* at this code reduction.
v2:
- [chad] Fix intelCreateBuffer for gen < 6. When the branch for
!screen->hw_has_separate_stencil was taken,
intel_create_private_renderbuffer was incorrectly not used.
- [chad] Remove all code in intel_process_dri2_buffer for processing
depth, stencil, and hiz buffers. That code is now dead.
CC: Eric Anholt <eric@anholt.net>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 252d3118dd40e9e3c577702b4c65a2d6cfd343b6 |
|
30-Mar-2012 |
Kenneth Graunke <kenneth@whitecape.org> |
i965/aub: Dump a final bitmap from DestroyContext.
Certain applications don't call SwapBuffers before exiting. Yet, we'd
really like to see a bitmap containing the final rendered image even if
they choose never to present it.
In particular, Piglit tests (at least with -auto -fbo) fall into this
category. Many of them failed to dump any images at all.
Dumping one final image at context destruction time seems to work.
We may wish to pursue a more elegant solution later.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| d09fce51f0cf91c9c07f69063fe2180cc319d8df |
|
06-Mar-2012 |
Eric Anholt <eric@anholt.net> |
i965: Change the hiz-override env var to a driconf option.
The force-enable option is dropped, now that the hardware we were
concerned about has HiZ on by default. Now, instead of doing
INTEL_HIZ=0 to test disabling hiz, you can set hiz=false.
v2: Disable separate stencil on gen6 when HIZ is turned off.
(previously, this had to be done manually in addition).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v1)
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| f172eae8b23d0612865895c52af745021ae20a4c |
|
02-Mar-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
i965: fixup W-tile offset computation to take swizzling into account
There's even a comment in the code containing the right swizzling
computations!
Previously this has not been noticed because we need to manually
enabled swizzling on snb/ivb (kernel 3.4 will do that) and we
don't use the separate stencil on ilk (where the bios enables
swizzling). This fixes
piglit ./bin/fbo-stencil readpixels GL_DEPTH32F_STENCIL8 -auto
on recent drm-intel-next kernels.
Also remove the comment about ivb, it's stale now.
Swizzling detection is done by allocating a temporary x-tiled
buffer object. Unfortunately kernels before v3.2 lie on snb/ivb
because they claim that swizzling is enable, but it isn't. The
kernel commit that fixes this for backport to pre-v3.2 is
commit acc83eb5a1e0ae7dbbf89ca2a1a943ade224bb84
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Mon Sep 12 20:49:16 2011 +0200
drm/i915: fix swizzling on gen6+
But if the kernel doesn't lie, this now works on swizzling and
not swizzling machines.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 7def293204977c41ea35198af147f743a31b1889 |
|
01-Feb-2012 |
Eugeni Dodonov <eugeni.dodonov@intel.com> |
intel: verify if hardware has LLC support
Rely on libdrm HAS_LLC parameter to verify if hardware supports it. In
case the libdrm version does not supports this check, fallback to older
way of detecting it which assumed that GPUs newer than GEN6 have it.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| cd2a24a4c2cf3aab8cbaf831d9712bc3c09cba66 |
|
30-Dec-2011 |
Eric Anholt <eric@anholt.net> |
i965/gen7: Enable transform feedback as long as kernel support is present.
The last major issue (intervening-read) is fixed, so let's turn this
on for real. The only other known issue is a hardware limitation for
tesselation with flat shading.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eugeni Dodonov <eugeni.dodonov@intel.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 2e5a1a254ed81b1d3efa6064f48183eefac784d0 |
|
07-Oct-2011 |
Kenneth Graunke <kenneth@whitecape.org> |
intel: Convert from GLboolean to 'bool' from stdbool.h.
I initially produced the patch using this bash command:
for file in {intel,i915,i965}/*.{c,cpp,h}; do [ ! -h $file ] && sed -i
's/GLboolean/bool/g' $file && sed -i 's/GL_TRUE/true/g' $file && sed -i
's/GL_FALSE/false/g' $file; done
Then I manually added #include <stdbool.h> to fix compilation errors,
and converted a few functions back to GLboolean that were used in core
Mesa's function pointer table to avoid "incompatible pointer" warnings.
Finally, I cleaned up some whitespace issues introduced by the change.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Chad Versace <chad@chad-versace.us>
Acked-by: Paul Berry <stereotype441@gmail.com>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| f7dbcba280e4397cadb14f230aa925b4143cdde4 |
|
18-Jul-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Fix stencil buffer to be W tiled
Until now, the stencil buffer was allocated as a Y tiled buffer, because
in several locations the PRM states that it is. However, it is actually
W tiled. From the PRM, 2011 Sandy Bridge, Volume 1, Part 2, Section
4.5.2.1 W-Major Format:
W-Major Tile Format is used for separate stencil.
The GTT is incapable of W fencing, so we allocate the stencil buffer with
I915_TILING_NONE and decode the tile's layout in software.
This fix touches the following portions of code:
- In intel_allocate_renderbuffer_storage(), allocate the stencil
buffer with I915_TILING_NONE.
- In intel_verify_dri2_has_hiz(), verify that the stencil buffer is
not tiled.
- In the stencil buffer's span functions, the tile's layout must be
decoded in software.
This commit mutually depends on the xf86-video-intel commit
dri: Do not tile stencil buffer
Author: Chad Versace <chad@chad-versace.us>
Date: Mon Jul 18 00:38:00 2011 -0700
On Gen6 with separate stencil enabled, fixes the following Piglit tests:
bugs/fdo23670-drawpix_stencil
general/stencil-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX16-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX1-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX4-readpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-copypixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-drawpixels
spec/EXT_framebuffer_object/fbo-stencil-GL_STENCIL_INDEX8-readpixels
spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-copypixels
spec/EXT_packed_depth_stencil/fbo-stencil-GL_DEPTH24_STENCIL8-readpixels
spec/EXT_packed_depth_stencil/readpixels-24_8
Note: This is a candidate for the 7.11 branch.
Signed-off-by: Chad Versace <chad@chad-versace.us>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| aea2236af60aee329e6ea73a41f2410d8eacc7b6 |
|
04-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Request DRI2 buffers for separate stencil and hiz
When it is sensible to do so,
1) intelCreateBuffer() now attaches separate depth and stencil
buffers
to the framebuffer it creates.
2) intel_update_renderbuffers() requests for the framebuffer
a separate stencil buffer (DRI2BufferStencil).
The criteria for "sensible" is:
- The GLX config has nonzero depth and stencil bits.
- The hardware supports separate stencil.
- The X driver supports separate stencil, or its support has not yet
been determined.
If the hardware supports hiz too, then intel_update_renderbuffers()
also requests DRI2BufferHiz.
If after requesting DRI2BufferStencil we determine that X driver did not
actually support separate stencil, we clean up the mistake and never ask
for DRI2BufferStencil again.
CC: Ian Romanick <idr@freedesktop.org>
CC: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 6b2bf272ee173bd8ee6c731500861de21fa01b5f |
|
27-May-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Add flags to intel_screen for hiz and separate stencil
Add the fields below to intel_screen. The expression in parens is the
value to which intelInitScreen2() currently sets the field.
GLboolean hw_has_separate_stencil (true iff gen >= 7)
GLboolean hw_must_use_separate_stencil (true iff gen >= 7)
GLboolean hw_has_hiz (always false)
enum intel_dri2_has_hiz dri2_has_hiz (INTEL_DRI2_HAS_HIZ_UNKNOWN)
The analogous fields in intel_context now inherit their values from
intel_screen.
When hiz and separate stencil become completely implemented for a given
chipset, then the respective fields need to be enabled.
CC: Ian Romanick <idr@freedesktop.org>
CC: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| df9f533c67e06713ae1b7f759c3644ca610058fd |
|
01-Jun-2011 |
Chad Versace <chad@chad-versace.us> |
intel: Define enum intel_dri2_has_hiz
... which indicates if the X driver supports DRI2BufferHiz and
DRI2BufferStencil.
I'm placing this in its own commit due to the large comment block.
CC: Ian Romanick <idr@freedesktop.org>
CC: Kristian Høgsberg <krh@bitplanet.net>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 7363088f9f9558b2bad3ac6da48947514a8cd790 |
|
25-Apr-2011 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Set gen in intelInitScreen, just copy value in intelInitContext
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 900a5c91eeb3acae7ee0ad331154531c4dba96e1 |
|
01-Mar-2011 |
Chris Wilson <chris@chris-wilson.co.uk> |
i965: Use negative relocation deltas to minimse vertex uploads
With relaxed relocation checking in the kernel, we can specify a
negative delta (i.e. pointing outside of the target bo) in order to fake
a range in a large buffer. We only then need to upload the elements used
and adjust the buffer offset such that they correspond with the indices
used in the DrawArrays.
(Depends on libdrm 0209428b3918c4336018da9293cdcbf7f8fedfb6)
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| bb35000b4b6dfe60048b2f5d60bc102c4a7fd791 |
|
05-Mar-2010 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-kernel-exec-fencing support.
Shaves 60k off the driver from removing the broken spans code. This
means we now require 2.6.29, which seems fair given that it's a year
old and we've removed support for non-KMS already in the last release
of 2D.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 2d99588b3556928a0879b4160210ac771dbf1f0b |
|
11-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
intel: Track named regions and make sure we only have one region per named bo
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| cc57baff5f40ba0ab3d3044c4fcd867e5b0e640e |
|
11-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
i915: Remove always-true irq_active struct intel_screen field
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| c9b0f04b1f3ba4765733fcbb91a7cc314bf83e5c |
|
11-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
i915: Remove a few DRI1 era struct intel_screen fields
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 5777dee02c6497207e6b4b9d68de072e7be7c06e |
|
11-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
i915: Drop intelScreenPrivate typedef and just call it struct intel_screen
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| cbfd4147ca5dea70a225f3b53629c270508ed2f6 |
|
11-Feb-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
i915: Remove unused intelRegion struct
Phew, sure is nice to only have one struct called intel region.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| d61f07318c8678901b948fdaa8ccdf37aa3203e9 |
|
01-Jan-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Remove leftover __DRI{screen,drawable,context}Private references
As part of the DRI driver interface rewrite I merged __DRIscreenPrivate
and __DRIscreen, and likewise for __DRIdrawablePrivate and
__DRIcontextPrivate. I left typedefs in place though, to avoid renaming
all the *Private use internal to the driver. That was probably a
mistake, and it turns out a one-line find+sed combo can do the mass
rename. Better late than never.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 827ba44f6ee83ab21c6a2b09323f6f1df4a7d4c8 |
|
18-Nov-2009 |
Eric Anholt <eric@anholt.net> |
intel: Remove non-GEM support.
This really isn't supported at this point. GEM's been in the kernel for
a year, and the fake bufmgr never really worked.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| e7aef006e50d0b859c621267af8376f5a0f43445 |
|
06-Apr-2009 |
Eric Anholt <eric@anholt.net> |
i965: Use GTT maps when available to upload vertex arrays and system VBOs.
This speeds up OA on my GM45 by 21% (more than the original CPU cost of
the upload path). We might still be able to squeeze a few more percent out
by avoiding repeatedly mapping/unmapping buffers as we upload elements into
them.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| aae2729aeb3f6eed26e8f7673f47f2b978786bb1 |
|
26-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: make intelUpdateScreenFromSAREA() static
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 6fcebbe719eab1f8e292c8dcd6c3e898b0f8d261 |
|
26-Jan-2009 |
Brian Paul <brianp@vmware.com> |
intel: Move swap-related functions from intel_buffers.c to new intel_swapbuffers.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 39e6d0d8108fe6d222865e7bb9de1e3cea18b4c4 |
|
20-Jan-2009 |
Timo Aaltonen <tjaalton@cc.hut.fi> |
[intel] Go back to using the typedef for the sarea struct
The upstream linux kernel headers and libdrm kernel headers disagree on the
tag name for the sarea struct: _drm_i915_sarea vs drm_i915_sarea. They
both typedef it to drm_i915_sarea_t though, so just use that.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| b359350017a8f0328912f19d233bcdcc256aded1 |
|
20-Dec-2008 |
Dave Airlie <airlied@redhat.com> |
Remove third buffer support from Mesa.
This is part of the deprecated pageflipping infrastructure.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| cd031749a75883a6fbf8fb7bf989b77a7c705819 |
|
28-Nov-2008 |
Dave Airlie <airlied@redhat.com> |
intel: restore old vertex submit paths for i8xx hardware.
Intel docs state that only 830/845 have VBOs, 855/865 don't. So
lets just not use them on i8xx at all.
This restores the old pre-vbo code and uses it on all 8xx hw.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 201d3419a6432a0f35dff48e606649092afb7ff7 |
|
11-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: Remove dead allow_batchbuffer param.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 3628185f566e178a12b493fb89abf52b4b281f99 |
|
06-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: track bufmgr move to libdrm_intel and bufmgr_fake irq emit/wait change.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 7e0bbdcf033981282978554c2e68ce48b55aa291 |
|
04-Sep-2008 |
Eric Anholt <eric@anholt.net> |
intel: Move the bufmgr back to the screen.
Mesa requires that we be able to share objects between contexts, which means
that the objects need to be created by the same bufmgr, and the bufmgr
internally requires pthread protection for thread safety.
Rely on the bufmgr having appropriate locking.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| f75843a517bd188639e6866db2a7b04de3524e16 |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
|
24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 2e841880cfc1006a2818d4a8bfefd21136dc39a9 |
|
11-Jul-2008 |
Eric Anholt <eric@anholt.net> |
drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 19f585a3cf65887e249d630fe43e83e7e7618dfa |
|
02-Jul-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Fix Y-tiling span setup.
The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode. Instead, guess the correct
tiling in screen setup.
Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is
32 scanlines, not 8.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 537bbe6dec780f6f85838fe7e6036579c509f8a6 |
|
06-May-2008 |
Keith Packard <keithp@keithp.com> |
[intel-GEM] Add tiling support to swrast.
Accessing tiled surfaces without using the fence registers requires that
software deal with the address swizzling itself.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 1c718c0d78cf4eae9e02b03a0abbec384db948a6 |
|
22-Feb-2008 |
Alan Hourihane <alanh@tungstengraphics.com> |
Use drm_i915_sarea instead of drmI830Sarea and remove i830_common.h
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 46eb02b60920a920b782bacb15f01b44e18f888d |
|
22-Jan-2008 |
Kristian Høgsberg <krh@temari.boston.redhat.com> |
[intel] Clean up references to screen buffer metrics.
The screen wide info such as pitch and cpp are obsoleted by the FBO
changes, so clean up the last few references to those, except for
setting up the legacy screen regions.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| 7c71ef3a3d0cf2620525f468960cdc76a0fb0d33 |
|
12-Dec-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move bufmgr back to context instead of screen, fixing glthreads.
Putting the bufmgr in the screen is not thread-safe since the emit_reloc
changes. It also led to a significant performance hit from pthread usage
for the attempted thread-safety (up to 12% of a cpu spent on refcounting
protection in single-threaded 965). The motivation had been to allow
multi-context bufmgr sharing in classic mode, but it wasn't worth the cost.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| a8fee3a498c8c4966d57a5273408477f3aa3ce73 |
|
15-Nov-2007 |
Keith Whitwell <keith@tungstengraphics.com> |
i915: Catch cases where not all state is emitted for a new batchbuffer.
This could lead to incorrect rendering or even lockups.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
|
| f00a64999c197e6a96e65fd00f64224a6f22c9fa |
|
17-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Add 965 support to shared intel_blit.c
This requires that regions grow a marker of whether they are tiled or not,
because fence (surface) registers are ignored by the 965 2D engine.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
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| 9724dc1ac7ddd6f547a8aa6d57fa51ed1040db3a |
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10-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[i915] Remove old frontbuffer rotation hack.
This was replaced in previous releases of xserver/dri/libGL by reporting the
damage to the frontbuffer so that the server and driver could handle it
appropriately.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
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| 77a5bcaff43df8d54e0e0ef833726e4b41d7eb36 |
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07-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move over files that will be shared with 965-fbo work.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_screen.h
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