| f172eae8b23d0612865895c52af745021ae20a4c |
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02-Mar-2012 |
Daniel Vetter <daniel.vetter@ffwll.ch> |
i965: fixup W-tile offset computation to take swizzling into account
There's even a comment in the code containing the right swizzling
computations!
Previously this has not been noticed because we need to manually
enabled swizzling on snb/ivb (kernel 3.4 will do that) and we
don't use the separate stencil on ilk (where the bios enables
swizzling). This fixes
piglit ./bin/fbo-stencil readpixels GL_DEPTH32F_STENCIL8 -auto
on recent drm-intel-next kernels.
Also remove the comment about ivb, it's stale now.
Swizzling detection is done by allocating a temporary x-tiled
buffer object. Unfortunately kernels before v3.2 lie on snb/ivb
because they claim that swizzling is enable, but it isn't. The
kernel commit that fixes this for backport to pre-v3.2 is
commit acc83eb5a1e0ae7dbbf89ca2a1a943ade224bb84
Author: Daniel Vetter <daniel.vetter@ffwll.ch>
Date: Mon Sep 12 20:49:16 2011 +0200
drm/i915: fix swizzling on gen6+
But if the kernel doesn't lie, this now works on swizzling and
not swizzling machines.
NOTE: This is a candidate for the 8.0 branch.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| 1839a7fc9faae81d32ffc0cdc908b933f4524e28 |
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16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: remove intel_span_supports_format()
It always returned True.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| 14da67d9b9b9e30740ef1687c3952a0b5e8b0a54 |
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16-Jan-2012 |
Brian Paul <brianp@vmware.com> |
intel: make intel_renderbuffer_map/unmap() static
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| 92054cd94e2188c9f4d56ddf9377c5aeb8a4e64e |
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11-Oct-2011 |
Eric Anholt <eric@anholt.net> |
intel: Add an implementation of MapRenderbuffer.
v2: Add separate stencil S8 W-tile swizzling/deswizzling. Tested for
the swizzling case with env INTEL_SEPARATE_STENCIL=1 INTEL_HIZ=1
./bin/hiz-depth-stencil-test-fbo-d24-s8
v3: Apply Chad's fix for S8 window system buffers.
Reviewed-by: Chad Versace <chad@chad-versace.us>
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| e339b669a14f37698b842c0c51c1f5e4001ef12f |
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10-Dec-2010 |
Eric Anholt <eric@anholt.net> |
intel: Add a couple of helper functions to reduce rb code duplication.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| f9995b30756140724f41daf963fa06167912be7f |
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12-Oct-2010 |
Kristian Høgsberg <krh@bitplanet.net> |
Drop GLcontext typedef and use struct gl_context instead
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| 7d4b7460b0e565d0574c00d1d40c426cfebc290d |
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29-Jul-2009 |
Eric Anholt <eric@anholt.net> |
i915: Enable ARB_vertex_shader for both i915 and i830.
Since the TNL is all done in software anyway, it should be the same to
the user who's probably using ARB_vertex_program otherwise, but gives them
a nicer programming environment.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| f75843a517bd188639e6866db2a7b04de3524e16 |
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24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Revert "Merge branch 'drm-gem'""
This reverts commit 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| 7c81124d7c4a4d1da9f48cbf7e82ab1a3a970a7a |
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24-Aug-2008 |
Dave Airlie <airlied@linux.ie> |
Revert "Merge branch 'drm-gem'"
This reverts commit 53675e5c05c0598b7ea206d5c27dbcae786a2c03.
Conflicts:
src/mesa/drivers/dri/i965/brw_wm_surface_state.c
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| bdaa06ad639821368ac8d1af7b7561fd7e83fb13 |
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15-Jul-2008 |
Eric Anholt <eric@anholt.net> |
intel: move renderbuffer mapping to separate functions.
This lets us avoid duplicated code for doing so, including the depthstencil
paths that aren't covered by SpanRenderStart/Finish. Those paths were
missing the span funcs setup, leading to a null dereference in the fbotexture
demo.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| 2e841880cfc1006a2818d4a8bfefd21136dc39a9 |
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11-Jul-2008 |
Eric Anholt <eric@anholt.net> |
drm-gem: Use new GEM ioctls for tiling state, and support new swizzle modes.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| 19f585a3cf65887e249d630fe43e83e7e7618dfa |
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02-Jul-2008 |
Eric Anholt <eric@anholt.net> |
intel-gem: Fix Y-tiling span setup.
The boolean that the server gives us for whether the region is tiled was
getting used as the enum for what tiling mode. Instead, guess the correct
tiling in screen setup.
Also, fix the Y-tiling pitch setup. The pitch to the next tile in Y is
32 scanlines, not 8.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| 537bbe6dec780f6f85838fe7e6036579c509f8a6 |
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06-May-2008 |
Keith Packard <keithp@keithp.com> |
[intel-GEM] Add tiling support to swrast.
Accessing tiled surfaces without using the fence registers requires that
software deal with the address swizzling itself.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
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| 77a5bcaff43df8d54e0e0ef833726e4b41d7eb36 |
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07-Nov-2007 |
Eric Anholt <eric@anholt.net> |
[intel] Move over files that will be shared with 965-fbo work.
/external/mesa3d/src/mesa/drivers/dri/intel/intel_span.h
|