Searched defs:Imm (Results 51 - 75 of 90) sorted by relevance

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/external/llvm/lib/Target/Sparc/AsmParser/
H A DSparcAsmParser.cpp175 struct ImmOp Imm; member in union:__anon25293::SparcOperand::__anon25294
210 return Imm.Val;
241 case k_Immediate: OS << "Imm: " << getImm() << "\n"; break;
312 Op->Imm.Val = Val;
375 const MCExpr *Imm = Op->getImm(); local
379 Op->Mem.Off = Imm;
/external/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp425 // Return true if MI is a shift of type Opcode by Imm bits.
426 static bool isShift(MachineInstr *MI, int Opcode, int64_t Imm) { argument
429 MI->getOperand(3).getImm() == Imm);
720 uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB; local
722 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
724 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
/external/llvm/lib/CodeGen/SelectionDAG/
H A DFastISel.cpp410 uint64_t Imm = CI->getZExtValue(); local
415 isPowerOf2_64(Imm)) {
416 Imm = Log2_64(Imm);
422 isPowerOf2_64(Imm)) {
423 --Imm;
428 Op0IsKill, Imm, VT.getSimpleVT());
1249 unsigned FastISel::FastEmit_i(MVT, MVT, unsigned, uint64_t /*Imm*/) {
1261 uint64_t /*Imm*/) {
1276 uint64_t /*Imm*/) {
1284 FastEmit_ri_(MVT VT, unsigned Opcode, unsigned Op0, bool Op0IsKill, uint64_t Imm, MVT ImmType) argument
1425 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
1497 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
1551 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument
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H A DTargetLowering.cpp1450 APInt Imm = APInt::getLowBitsSet(ExtDstTyBits, ExtSrcTyBits); local
1452 DAG.getConstant(Imm, Op0Ty));
/external/llvm/lib/Target/AArch64/
H A DAArch64FastISel.cpp208 int Imm; local
211 Imm = AArch64_AM::getFP64Imm(Val);
214 Imm = AArch64_AM::getFP32Imm(Val);
219 .addImm(Imm);
825 uint64_t Imm = CI->getZExtValue(); local
826 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
890 uint64_t Imm; local
898 Imm = (isZExt) ? CIVal.getZExtValue() : CIVal.getSExtValue();
901 Imm = -Imm;
1765 unsigned Imm = 0; local
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H A DAArch64ISelDAGToDAG.cpp191 /// operand. If so Imm will receive the 32-bit value.
192 static bool isIntImmediate(const SDNode *N, uint64_t &Imm) { argument
194 Imm = C->getZExtValue();
201 // If so Imm will receive the value.
202 static bool isIntImmediate(SDValue N, uint64_t &Imm) { argument
203 return isIntImmediate(N.getNode(), Imm);
208 // If so Imm will receive the 32 bit value.
210 uint64_t &Imm) {
212 isIntImmediate(N->getOperand(1).getNode(), Imm);
1592 uint64_t Imm local
209 isOpcWithIntImmediate(const SDNode *N, unsigned Opc, uint64_t &Imm) argument
1599 getUsefulBitsFromBitfieldMoveOpd(SDValue Op, APInt &UsefulBits, uint64_t Imm, uint64_t MSB, unsigned Depth) argument
1628 uint64_t Imm = local
1666 uint64_t Imm = local
1908 uint64_t Imm; local
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/external/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAG.cpp118 SDValue XformMskToBitPosU5Imm(uint32_t Imm) { argument
120 bitPos = Log2_32(Imm);
128 SDValue XformMskToBitPosU4Imm(uint16_t Imm) { argument
129 return XformMskToBitPosU5Imm(Imm);
134 SDValue XformMskToBitPosU3Imm(uint8_t Imm) { argument
135 return XformMskToBitPosU5Imm(Imm);
149 inline SDValue XformM5ToU5Imm(signed Imm) { argument
150 assert( (Imm >= -31 && Imm <= -1) && "Constant out of range for Memops");
151 return CurDAG->getTargetConstant( - Imm, MV
157 XformU7ToU7M1Imm(signed Imm) argument
163 XformSToSM1Imm(signed Imm) argument
168 XformUToUM1Imm(unsigned Imm) argument
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H A DHexagonISelLowering.cpp1625 bool HexagonTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { argument
1658 bool HexagonTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
1659 return Imm >= -512 && Imm <= 511;
/external/llvm/lib/Target/NVPTX/
H A DNVPTXAsmPrinter.cpp922 int Imm = (int) MO.getImm(); local
924 O << "_" << vecelem[Imm];
926 if ((Imm < 0) || (Imm > 3))
929 if ((Imm < 4) || (Imm > 7))
932 if (Imm < 0)
933 Imm = 0;
934 O << "_" << vecelem[Imm % 4];
936 if ((Imm <
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/external/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp324 struct ImmOp Imm; member in union:__anon25233::PPCOperand::__anon25234
341 Imm = o.Imm;
363 return Imm.Val;
383 return (unsigned) Imm.Val;
388 return (unsigned) Imm.Val;
393 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
398 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
403 return 7 - countTrailingZeros<uint64_t>(Imm.Val);
581 Op->Imm
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/external/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp110 unsigned FastEmit_i(MVT Ty, MVT RetTy, unsigned Opc, uint64_t Imm) override;
114 uint64_t Imm);
157 unsigned PPCMaterialize32BitInt(int64_t Imm,
159 unsigned PPCMaterialize64BitInt(int64_t Imm,
716 uint64_t Imm = CI->getZExtValue(); local
717 MachineBasicBlock *Target = (Imm == 0) ? FBB : TBB;
748 long Imm = 0; local
757 Imm = (IsZExt) ? (long)CIVal.getZExtValue() : (long)CIVal.getSExtValue();
758 if ((IsZExt && isUInt<16>(Imm)) || (!IsZExt && isInt<16>(Imm)))
1127 int Imm = (int)CIVal.getSExtValue(); local
1921 PPCMaterialize32BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
1953 PPCMaterialize64BitInt(int64_t Imm, const TargetRegisterClass *RC) argument
2039 int64_t Imm = CI->getZExtValue(); local
2180 FastEmit_i(MVT Ty, MVT VT, unsigned Opc, uint64_t Imm) argument
2217 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
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H A DPPCISelDAGToDAG.cpp82 inline SDValue getI32Imm(unsigned Imm) { argument
83 return CurDAG->getTargetConstant(Imm, MVT::i32);
88 inline SDValue getI64Imm(uint64_t Imm) { argument
89 return CurDAG->getTargetConstant(Imm, MVT::i64);
93 inline SDValue getSmallIPtrImm(unsigned Imm) { argument
94 return CurDAG->getTargetConstant(Imm, PPCLowering->getPointerTy());
295 static bool isIntS16Immediate(SDNode *N, short &Imm) { argument
299 Imm = (short)cast<ConstantSDNode>(N)->getZExtValue();
301 return Imm == (int32_t)cast<ConstantSDNode>(N)->getZExtValue();
303 return Imm
306 isIntS16Immediate(SDValue Op, short &Imm) argument
313 isInt32Immediate(SDNode *N, unsigned &Imm) argument
323 isInt64Immediate(SDNode *N, uint64_t &Imm) argument
333 isInt32Immediate(SDValue N, unsigned &Imm) argument
341 isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) argument
498 unsigned Imm; local
539 uint64_t Imm; local
746 unsigned Imm; local
933 int64_t Imm = cast<ConstantSDNode>(N)->getZExtValue(); local
1037 unsigned Imm; local
1147 unsigned Imm, Imm2, SH, MB, ME; local
1220 unsigned Imm, SH, MB, ME; local
1232 unsigned Imm, SH, MB, ME; local
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/external/llvm/lib/Target/R600/
H A DR600ISelLowering.cpp2054 SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) {
2160 if (!Imm.getNode())
2162 ConstantSDNode *C = dyn_cast<ConstantSDNode>(Imm);
2166 Imm = DAG.getTargetConstant(ImmValue, MVT::i32);
2291 SDValue &Imm = Ops[ImmIdx]; local
2292 if (FoldOperand(Node, i, Src, Neg, Abs, Sel, Imm, DAG))
2053 FoldOperand(SDNode *ParentNode, unsigned SrcIdx, SDValue &Src, SDValue &Neg, SDValue &Abs, SDValue &Sel, SDValue &Imm, SelectionDAG &DAG) argument
H A DSIISelLowering.cpp281 bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm, argument
285 return TII->isInlineConstant(Imm);
1201 } Imm; local
1207 Imm.I = Node->getSExtValue();
1211 Imm.F = Node->getValueAPF().convertToFloat();
1215 if ((Imm.I >= -16 && Imm.I <= 64) ||
1216 Imm.F == 0.5f || Imm.F == -0.5f ||
1217 Imm
1410 int32_t Imm = analyzeImmediate(Node->getOperand(i).getNode()); local
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H A DSIInstrInfo.cpp486 bool SIInstrInfo::isInlineConstant(const APInt &Imm) const {
487 int32_t Val = Imm.getSExtValue();
500 return (APInt::floatToBits(0.0f) == Imm) ||
501 (APInt::floatToBits(1.0f) == Imm) ||
502 (APInt::floatToBits(-1.0f) == Imm) ||
503 (APInt::floatToBits(0.5f) == Imm) ||
504 (APInt::floatToBits(-0.5f) == Imm) ||
505 (APInt::floatToBits(2.0f) == Imm) ||
506 (APInt::floatToBits(-2.0f) == Imm) ||
507 (APInt::floatToBits(4.0f) == Imm) ||
1296 uint32_t Imm = OffsetWidthOp.getImm(); local
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H A DAMDGPUISelLowering.cpp399 bool AMDGPUTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const { argument
/external/llvm/lib/Target/SystemZ/AsmParser/
H A DSystemZAsmParser.cpp103 const MCExpr *Imm; member in union:__anon25306::SystemZOperand::__anon25307
148 Op->Imm = Expr;
196 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
200 return Imm;
/external/llvm/lib/Target/X86/
H A DX86ISelLowering.h669 bool isLegalICmpImmediate(int64_t Imm) const override;
675 bool isLegalAddImmediate(int64_t Imm) const override;
720 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
769 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
828 void addLegalFPImmediate(const APFloat& Imm) { argument
829 LegalFPImmediates.push_back(Imm);
H A DX86ISelDAGToDAG.cpp208 bool SelectMOV64Imm32(SDValue N, SDValue &Imm);
275 inline SDValue getI8Imm(unsigned Imm) { argument
276 return CurDAG->getTargetConstant(Imm, MVT::i8);
281 inline SDValue getI32Imm(unsigned Imm) { argument
282 return CurDAG->getTargetConstant(Imm, MVT::i32);
343 if (ConstantSDNode *Imm = dyn_cast<ConstantSDNode>(Op1))
344 if (Imm->getAPIntValue().isSignedIntN(8))
1394 bool X86DAGToDAGISel::SelectMOV64Imm32(SDValue N, SDValue &Imm) { argument
1400 Imm = CurDAG->getTargetConstant(ImmVal, MVT::i64);
1418 Imm
2584 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i8); local
2656 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i16); local
2678 SDValue Imm = CurDAG->getTargetConstant(C->getZExtValue(), MVT::i32); local
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H A DX86InstrInfo.cpp1847 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm(); local
1848 return Imm & ShiftCountMask;
/external/valgrind/main/VEX/priv/
H A Dhost_mips_defs.h237 } Imm; member in union:__anon31043::__anon31044
/external/llvm/lib/Target/ARM/
H A DARMFastISel.cpp123 uint64_t Imm);
128 uint64_t Imm);
131 uint64_t Imm);
371 uint64_t Imm) {
382 .addImm(Imm));
386 .addImm(Imm));
398 uint64_t Imm) {
411 .addImm(Imm));
416 .addImm(Imm));
426 uint64_t Imm) {
368 FastEmitInst_ri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, uint64_t Imm) argument
394 FastEmitInst_rri(unsigned MachineInstOpcode, const TargetRegisterClass *RC, unsigned Op0, bool Op0IsKill, unsigned Op1, bool Op1IsKill, uint64_t Imm) argument
424 FastEmitInst_i(unsigned MachineInstOpcode, const TargetRegisterClass *RC, uint64_t Imm) argument
475 int Imm; local
532 unsigned Imm = (unsigned)~(CI->getSExtValue()); local
934 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; local
948 signed Imm = (Addr.Offset < 0) ? (0x100 | -Addr.Offset) : Addr.Offset; local
1310 uint64_t Imm = CI->getZExtValue(); local
1375 int Imm = 0; local
1638 int Imm = 0; local
2623 uint32_t Imm : 8; // All instructions have either a shift or a mask. member in struct:InstructionTable
2685 unsigned Imm = ITP->Imm; local
2914 const uint64_t Imm = MI->getOperand(2).getImm(); local
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H A DARMISelDAGToDAG.cpp86 inline SDValue getI32Imm(unsigned Imm) { argument
87 return CurDAG->getTargetConstant(Imm, MVT::i32);
189 inline bool is_so_imm(unsigned Imm) const {
190 return ARM_AM::getSOImmVal(Imm) != -1;
193 inline bool is_so_imm_not(unsigned Imm) const {
194 return ARM_AM::getSOImmVal(~Imm) != -1;
197 inline bool is_t2_so_imm(unsigned Imm) const {
198 return ARM_AM::getT2SOImmVal(Imm) != -1;
201 inline bool is_t2_so_imm_not(unsigned Imm) const {
202 return ARM_AM::getT2SOImmVal(~Imm) !
281 isInt32Immediate(SDNode *N, unsigned &Imm) argument
291 isInt32Immediate(SDValue N, unsigned &Imm) argument
298 isOpcWithIntImmediate(SDNode *N, unsigned Opc, unsigned& Imm) argument
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/external/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp590 // Returns true and sets Imm if:
597 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) { argument
611 Imm = SplatValue;
1439 unsigned Opc, SDValue Imm,
1448 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) {
1470 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm);
1472 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG);
2446 APInt Imm(32, 0);
2453 Imm <<
1438 lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc, SDValue Imm, bool BigEndian) argument
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/external/llvm/lib/Target/X86/AsmParser/
H A DX86AsmParser.cpp254 int64_t Imm; member in class:__anon25327::X86AsmParser::IntelExprStateMachine
263 Scale(1), Imm(imm), Sym(nullptr), StopOnLBrac(stoponlbrac),
271 int64_t getImm() { return Imm + IC.execute(); }
501 IC.pushOperand(IC_IMM, -TmpInt); // Push -Imm.
511 IC.pushOperand(IC_IMM, ~TmpInt); // Push ~Imm.
1225 const MCExpr *Imm = MCConstantExpr::Create(SM.getImm(), getContext()); local
1227 Disp = MCBinaryExpr::CreateAdd(Disp, Imm, getContext());
1229 Disp = Imm; // An immediate displacement only.
1430 // .Imm gets lexed as a real.
1525 const MCExpr *Imm local
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